Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29509	1			T1	169		T2	10		T3	78
auto[PWRUP]	109	1			T38	1		T36	2		T37	1
auto[ONEST_0]	67	1			T1	1		T8	1		T38	1
auto[ONEST_021]	13	1			T36	1		T39	1		T13	1
auto[ONEST_1]	92	1			T1	1		T3	2		T38	1
auto[ONEST_DONE]	4	1			T39	1		T29	1		T169	1
auto[LP_0]	119	1			T1	2		T38	1		T36	1
auto[LP_021]	23	1			T36	1		T37	1		T170	1
auto[LP_1]	125	1			T1	2		T8	2		T38	2
auto[LP_EVAL]	70	1			T1	1		T8	1		T12	2
auto[LP_SLP]	493	1			T1	3		T3	3		T8	5
auto[LP_PWRUP]	28	1			T27	1		T13	1		T31	1
auto[NP_0]	144	1			T1	1		T8	2		T36	1
auto[NP_021]	35	1			T8	1		T13	1		T29	1
auto[NP_1]	146	1			T1	1		T3	1		T38	2
auto[NP_EVAL]	34	1			T37	1		T39	2		T171	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T40

1

T171

1

T31

1

min

28918

1

T1

164

T2

10

T3

77

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28924	1			T1	164		T2	10		T3	77
pow[0x1]	6	1			T39	1		T172	1		T167	1
pow[0x2]	14	1			T40	1		T172	1		T173	1
pow[0x3]	36	1			T1	1		T38	2		T36	1
pow[0x4]	53	1			T1	1		T8	3		T38	2
pow[0x5]	125	1			T1	1		T8	1		T38	3
pow[0x6]	273	1			T1	1		T3	2		T8	3
pow[0x7]	514	1			T1	5		T3	1		T8	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

191

1

T1

7

T8

1

T37

5

min

28444

1

T1

159

T2

10

T3

75

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28444	1			T1	159		T2	10		T3	75
pow[0x3]	1	1			T174	1		-	-		-	-
pow[0x5]	1	1			T175	1		-	-		-	-
pow[0x7]	1	1			T176	1		-	-		-	-
pow[0x8]	6	1			T39	1		T31	1		T85	1
pow[0x9]	10	1			T29	1		T177	1		T178	1
pow[0xa]	19	1			T27	1		T171	1		T31	2
pow[0xb]	44	1			T3	1		T36	1		T37	1
pow[0xc]	65	1			T38	1		T36	2		T39	1
pow[0xd]	143	1			T1	1		T38	2		T36	3
pow[0xe]	295	1			T1	1		T3	1		T8	4
pow[0xf]	572	1			T1	7		T3	1		T8	2