Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2358	1			T1	21		T3	23		T8	11
auto[PWRUP]	141	1			T3	1		T38	1		T36	1
auto[ONEST_0]	92	1			T1	1		T3	1		T38	4
auto[ONEST_021]	21	1			T13	1		T331	1		T333	1
auto[ONEST_1]	81	1			T1	3		T37	1		T39	1
auto[ONEST_DONE]	3	1			T1	1		T334	1		T335	1
auto[LP_0]	136	1			T1	2		T8	1		T36	3
auto[LP_021]	43	1			T3	1		T39	1		T13	1
auto[LP_1]	127	1			T1	1		T3	1		T8	4
auto[LP_EVAL]	68	1			T3	2		T12	1		T36	1
auto[LP_SLP]	536	1			T1	5		T3	2		T8	6
auto[LP_PWRUP]	23	1			T37	1		T27	1		T336	1
auto[NP_0]	225	1			T1	1		T8	1		T12	3
auto[NP_021]	44	1			T3	2		T27	1		T13	2
auto[NP_1]	237	1			T1	2		T3	7		T12	5
auto[NP_EVAL]	24	1			T39	1		T40	1		T28	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

12

1

T8

1

T85

1

T331

1

min

2016

1

T1

11

T3

25

T8

7

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2022	1			T1	11		T3	25		T8	7
pow[0x1]	7	1			T33	1		T337	1		T338	1
pow[0x2]	15	1			T37	1		T29	1		T333	1
pow[0x3]	34	1			T3	1		T38	1		T37	2
pow[0x4]	67	1			T3	1		T12	1		T36	1
pow[0x5]	140	1			T1	1		T3	4		T8	2
pow[0x6]	249	1			T1	2		T3	3		T8	1
pow[0x7]	543	1			T1	14		T3	2		T8	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

202

1

T1

2

T3

1

T8

1

min

1382

1

T1

4

T3

20

T12

12

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1388	1			T1	4		T3	20		T12	12
pow[0x1]	15	1			T3	2		T12	6		T29	1
pow[0x2]	12	1			T3	1		T337	1		T243	2
pow[0x3]	46	1			T25	1		T29	1		T30	1
pow[0x4]	76	1			T3	1		T12	1		T27	2
pow[0x5]	1	1			T339	1		-	-		-	-
pow[0x6]	1	1			T340	1		-	-		-	-
pow[0x7]	3	1			T341	1		T312	1		T342	1
pow[0x8]	3	1			T171	1		T29	1		T343	1
pow[0x9]	11	1			T36	1		T171	1		T331	1
pow[0xa]	21	1			T1	1		T37	1		T40	1
pow[0xb]	27	1			T36	1		T37	1		T39	1
pow[0xc]	73	1			T1	1		T38	1		T36	1
pow[0xd]	159	1			T1	1		T8	2		T36	2
pow[0xe]	275	1			T1	6		T3	1		T8	3
pow[0xf]	605	1			T1	5		T3	3		T8	5