Assert Coverage for Module :
adc_ctrl_fsm_sva
Assertion Details
FsmDebugOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31979285 |
31898548 |
0 |
0 |
T1 |
2057 |
1677 |
0 |
0 |
T2 |
32719 |
32660 |
0 |
0 |
T3 |
6604 |
6337 |
0 |
0 |
T4 |
81465 |
81403 |
0 |
0 |
T5 |
100347 |
100267 |
0 |
0 |
T6 |
35231 |
35177 |
0 |
0 |
T7 |
100441 |
100369 |
0 |
0 |
T8 |
74 |
1 |
0 |
0 |
T9 |
39419 |
39347 |
0 |
0 |
T10 |
7867 |
7776 |
0 |
0 |
FsmStateHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1164 |
1164 |
0 |
0 |
T1 |
5 |
5 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
6 |
6 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
FsmStateSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31979285 |
6608 |
0 |
0 |
T2 |
32719 |
10 |
0 |
0 |
T3 |
6604 |
0 |
0 |
0 |
T4 |
81465 |
13 |
0 |
0 |
T5 |
100347 |
21 |
0 |
0 |
T6 |
35231 |
8 |
0 |
0 |
T7 |
100441 |
15 |
0 |
0 |
T8 |
74 |
0 |
0 |
0 |
T9 |
39419 |
10 |
0 |
0 |
T10 |
7867 |
0 |
0 |
0 |
T11 |
99334 |
27 |
0 |
0 |
T26 |
0 |
20 |
0 |
0 |
T34 |
0 |
15 |
0 |
0 |
T76 |
0 |
13 |
0 |
0 |
LpSampleCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1164 |
1164 |
0 |
0 |
T1 |
5 |
5 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
6 |
6 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
LpSampleCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31979285 |
6608 |
0 |
0 |
T2 |
32719 |
10 |
0 |
0 |
T3 |
6604 |
0 |
0 |
0 |
T4 |
81465 |
13 |
0 |
0 |
T5 |
100347 |
21 |
0 |
0 |
T6 |
35231 |
8 |
0 |
0 |
T7 |
100441 |
15 |
0 |
0 |
T8 |
74 |
0 |
0 |
0 |
T9 |
39419 |
10 |
0 |
0 |
T10 |
7867 |
0 |
0 |
0 |
T11 |
99334 |
27 |
0 |
0 |
T26 |
0 |
20 |
0 |
0 |
T34 |
0 |
15 |
0 |
0 |
T76 |
0 |
13 |
0 |
0 |
NpSampleCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1164 |
1164 |
0 |
0 |
T1 |
5 |
5 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
6 |
6 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
NpSampleCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31979285 |
6608 |
0 |
0 |
T2 |
32719 |
10 |
0 |
0 |
T3 |
6604 |
0 |
0 |
0 |
T4 |
81465 |
13 |
0 |
0 |
T5 |
100347 |
21 |
0 |
0 |
T6 |
35231 |
8 |
0 |
0 |
T7 |
100441 |
15 |
0 |
0 |
T8 |
74 |
0 |
0 |
0 |
T9 |
39419 |
10 |
0 |
0 |
T10 |
7867 |
0 |
0 |
0 |
T11 |
99334 |
27 |
0 |
0 |
T26 |
0 |
20 |
0 |
0 |
T34 |
0 |
15 |
0 |
0 |
T76 |
0 |
13 |
0 |
0 |
PwrupTimerCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1164 |
1164 |
0 |
0 |
T1 |
5 |
5 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
6 |
6 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
PwrupTimerCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31979285 |
6608 |
0 |
0 |
T2 |
32719 |
10 |
0 |
0 |
T3 |
6604 |
0 |
0 |
0 |
T4 |
81465 |
13 |
0 |
0 |
T5 |
100347 |
21 |
0 |
0 |
T6 |
35231 |
8 |
0 |
0 |
T7 |
100441 |
15 |
0 |
0 |
T8 |
74 |
0 |
0 |
0 |
T9 |
39419 |
10 |
0 |
0 |
T10 |
7867 |
0 |
0 |
0 |
T11 |
99334 |
27 |
0 |
0 |
T26 |
0 |
20 |
0 |
0 |
T34 |
0 |
15 |
0 |
0 |
T76 |
0 |
13 |
0 |
0 |
WakeupTimerCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1164 |
1164 |
0 |
0 |
T1 |
5 |
5 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
6 |
6 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
WakeupTimerCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31979285 |
6608 |
0 |
0 |
T2 |
32719 |
10 |
0 |
0 |
T3 |
6604 |
0 |
0 |
0 |
T4 |
81465 |
13 |
0 |
0 |
T5 |
100347 |
21 |
0 |
0 |
T6 |
35231 |
8 |
0 |
0 |
T7 |
100441 |
15 |
0 |
0 |
T8 |
74 |
0 |
0 |
0 |
T9 |
39419 |
10 |
0 |
0 |
T10 |
7867 |
0 |
0 |
0 |
T11 |
99334 |
27 |
0 |
0 |
T26 |
0 |
20 |
0 |
0 |
T34 |
0 |
15 |
0 |
0 |
T76 |
0 |
13 |
0 |
0 |