Line Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Module :
prim_sync_reqack
| Total | Covered | Percent |
Conditions | 6 | 3 | 50.00 |
Logical | 6 | 3 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_sync_reqack
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_sync_reqack
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
4714083 |
0 |
0 |
T1 |
680388 |
1508 |
0 |
0 |
T2 |
2781185 |
4859 |
0 |
0 |
T3 |
3767280 |
7508 |
0 |
0 |
T4 |
509160 |
11494 |
0 |
0 |
T5 |
2006985 |
14789 |
0 |
0 |
T6 |
4227940 |
5307 |
0 |
0 |
T7 |
2511065 |
14833 |
0 |
0 |
T8 |
1085050 |
1532 |
0 |
0 |
T9 |
2463745 |
5278 |
0 |
0 |
T10 |
4721195 |
409 |
0 |
0 |
T11 |
782060 |
312 |
0 |
0 |
T12 |
0 |
103 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
174241617 |
3110535 |
0 |
0 |
T1 |
54426 |
918 |
0 |
0 |
T2 |
163595 |
3172 |
0 |
0 |
T3 |
581100 |
4963 |
0 |
0 |
T4 |
407325 |
8129 |
0 |
0 |
T5 |
501735 |
9606 |
0 |
0 |
T6 |
176155 |
3569 |
0 |
0 |
T7 |
502205 |
9760 |
0 |
0 |
T8 |
80365 |
936 |
0 |
0 |
T9 |
197095 |
3374 |
0 |
0 |
T10 |
39335 |
278 |
0 |
0 |
T11 |
198668 |
312 |
0 |
0 |
T12 |
0 |
103 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
655067 |
0 |
0 |
T1 |
226796 |
239 |
0 |
0 |
T2 |
556237 |
705 |
0 |
0 |
T3 |
753456 |
1072 |
0 |
0 |
T4 |
101832 |
1368 |
0 |
0 |
T5 |
401397 |
2118 |
0 |
0 |
T6 |
845588 |
721 |
0 |
0 |
T7 |
502213 |
2074 |
0 |
0 |
T8 |
217010 |
236 |
0 |
0 |
T9 |
492749 |
670 |
0 |
0 |
T10 |
944239 |
51 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34865703 |
654787 |
0 |
0 |
T1 |
18142 |
238 |
0 |
0 |
T2 |
32719 |
705 |
0 |
0 |
T3 |
116220 |
1067 |
0 |
0 |
T4 |
81465 |
1368 |
0 |
0 |
T5 |
100347 |
2118 |
0 |
0 |
T6 |
35231 |
721 |
0 |
0 |
T7 |
100441 |
2074 |
0 |
0 |
T8 |
16073 |
236 |
0 |
0 |
T9 |
39419 |
670 |
0 |
0 |
T10 |
7867 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
647449 |
0 |
0 |
T1 |
226796 |
176 |
0 |
0 |
T2 |
556237 |
697 |
0 |
0 |
T3 |
753456 |
1008 |
0 |
0 |
T4 |
101832 |
1385 |
0 |
0 |
T5 |
401397 |
2095 |
0 |
0 |
T6 |
845588 |
719 |
0 |
0 |
T7 |
502213 |
2068 |
0 |
0 |
T8 |
217010 |
186 |
0 |
0 |
T9 |
492749 |
697 |
0 |
0 |
T10 |
944239 |
51 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34865703 |
636719 |
0 |
0 |
T1 |
18142 |
175 |
0 |
0 |
T2 |
32719 |
685 |
0 |
0 |
T3 |
116220 |
996 |
0 |
0 |
T4 |
81465 |
1362 |
0 |
0 |
T5 |
100347 |
2051 |
0 |
0 |
T6 |
35231 |
705 |
0 |
0 |
T7 |
100441 |
2033 |
0 |
0 |
T8 |
16073 |
185 |
0 |
0 |
T9 |
39419 |
682 |
0 |
0 |
T10 |
7867 |
51 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T2,T3,T4 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T2,T3,T4 |
ODD |
- |
0 |
Covered |
T2,T3,T4 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T2,T3,T4 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T2,T3,T4 |
ODD |
- |
0 |
Covered |
T2,T3,T4 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
84785 |
0 |
0 |
T2 |
556237 |
94 |
0 |
0 |
T3 |
753456 |
122 |
0 |
0 |
T4 |
101832 |
209 |
0 |
0 |
T5 |
401397 |
259 |
0 |
0 |
T6 |
845588 |
119 |
0 |
0 |
T7 |
502213 |
286 |
0 |
0 |
T8 |
217010 |
1 |
0 |
0 |
T9 |
492749 |
105 |
0 |
0 |
T10 |
944239 |
0 |
0 |
0 |
T11 |
391030 |
266 |
0 |
0 |
T12 |
0 |
75 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34865703 |
83815 |
0 |
0 |
T2 |
32719 |
94 |
0 |
0 |
T3 |
116220 |
120 |
0 |
0 |
T4 |
81465 |
209 |
0 |
0 |
T5 |
100347 |
259 |
0 |
0 |
T6 |
35231 |
119 |
0 |
0 |
T7 |
100441 |
286 |
0 |
0 |
T8 |
16073 |
1 |
0 |
0 |
T9 |
39419 |
105 |
0 |
0 |
T10 |
7867 |
0 |
0 |
0 |
T11 |
99334 |
266 |
0 |
0 |
T12 |
0 |
75 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T1,T2,T3 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T1,T2,T3 |
ODD |
- |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
3309205 |
0 |
0 |
T1 |
226796 |
1093 |
0 |
0 |
T2 |
556237 |
3347 |
0 |
0 |
T3 |
753456 |
5280 |
0 |
0 |
T4 |
101832 |
8474 |
0 |
0 |
T5 |
401397 |
10270 |
0 |
0 |
T6 |
845588 |
3713 |
0 |
0 |
T7 |
502213 |
10353 |
0 |
0 |
T8 |
217010 |
1107 |
0 |
0 |
T9 |
492749 |
3775 |
0 |
0 |
T10 |
944239 |
307 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34865703 |
1717640 |
0 |
0 |
T1 |
18142 |
505 |
0 |
0 |
T2 |
32719 |
1672 |
0 |
0 |
T3 |
116220 |
2754 |
0 |
0 |
T4 |
81465 |
5132 |
0 |
0 |
T5 |
100347 |
5131 |
0 |
0 |
T6 |
35231 |
1989 |
0 |
0 |
T7 |
100441 |
5315 |
0 |
0 |
T8 |
16073 |
512 |
0 |
0 |
T9 |
39419 |
1886 |
0 |
0 |
T10 |
7867 |
176 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 36 | 36 | 100.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 194 | 1 | 1 | 100.00 |
CONT_ASSIGN | 195 | 1 | 1 | 100.00 |
ALWAYS | 219 | 12 | 12 | 100.00 |
ALWAYS | 263 | 12 | 12 | 100.00 |
ALWAYS | 307 | 5 | 5 | 100.00 |
ALWAYS | 316 | 5 | 5 | 100.00 |
CONT_ASSIGN | 335 | 0 | 0 | |
ALWAYS | 339 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
194 |
1 |
1 |
195 |
1 |
1 |
219 |
1 |
1 |
222 |
1 |
1 |
223 |
1 |
1 |
225 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
|
|
|
MISSING_ELSE |
241 |
1 |
1 |
242 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
263 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
269 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
277 |
1 |
1 |
278 |
1 |
1 |
|
|
|
MISSING_ELSE |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
|
|
|
MISSING_ELSE |
307 |
1 |
1 |
308 |
1 |
1 |
309 |
1 |
1 |
311 |
1 |
1 |
312 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
318 |
1 |
1 |
320 |
1 |
1 |
321 |
1 |
1 |
335 |
|
unreachable |
339 |
|
unreachable |
340 |
|
unreachable |
341 |
|
unreachable |
342 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync
| Total | Covered | Percent |
Conditions | 4 | 3 | 75.00 |
Logical | 4 | 3 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 194
EXPRESSION (src_req_i & src_ack_o)
----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T3,T4 |
1 | 1 | Covered | T2,T3,T4 |
LINE 195
EXPRESSION (dst_req_o & dst_ack_i)
----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T2,T3,T4 |
Branch Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync
| Line No. | Total | Covered | Percent |
Branches |
|
12 |
12 |
100.00 |
CASE |
225 |
4 |
4 |
100.00 |
CASE |
269 |
4 |
4 |
100.00 |
IF |
307 |
2 |
2 |
100.00 |
IF |
316 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 225 case (gen_nrz_hs_protocol.src_fsm_cs)
-2-: 233 if (gen_nrz_hs_protocol.src_handshake)
-3-: 245 if (gen_nrz_hs_protocol.src_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T2,T3,T4 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T2,T3,T4 |
ODD |
- |
0 |
Covered |
T2,T3,T4 |
LineNo. Expression
-1-: 269 case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-: 277 if (gen_nrz_hs_protocol.dst_handshake)
-3-: 289 if (gen_nrz_hs_protocol.dst_handshake)
Branches:
-1- | -2- | -3- | Status | Tests |
EVEN |
1 |
- |
Covered |
T2,T3,T4 |
EVEN |
0 |
- |
Covered |
T1,T2,T3 |
ODD |
- |
1 |
Covered |
T2,T3,T4 |
ODD |
- |
0 |
Covered |
T2,T3,T4 |
LineNo. Expression
-1-: 307 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 316 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync
Assertion Details
SyncReqAckAckNeedsReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
17577 |
0 |
0 |
T2 |
556237 |
16 |
0 |
0 |
T3 |
753456 |
26 |
0 |
0 |
T4 |
101832 |
58 |
0 |
0 |
T5 |
401397 |
47 |
0 |
0 |
T6 |
845588 |
35 |
0 |
0 |
T7 |
502213 |
52 |
0 |
0 |
T8 |
217010 |
2 |
0 |
0 |
T9 |
492749 |
31 |
0 |
0 |
T10 |
944239 |
0 |
0 |
0 |
T11 |
391030 |
46 |
0 |
0 |
T12 |
0 |
28 |
0 |
0 |
SyncReqAckHoldReq
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34778805 |
17574 |
0 |
0 |
T2 |
32719 |
16 |
0 |
0 |
T3 |
116220 |
26 |
0 |
0 |
T4 |
81465 |
58 |
0 |
0 |
T5 |
100347 |
47 |
0 |
0 |
T6 |
35231 |
35 |
0 |
0 |
T7 |
100441 |
52 |
0 |
0 |
T8 |
16073 |
2 |
0 |
0 |
T9 |
39419 |
31 |
0 |
0 |
T10 |
7867 |
0 |
0 |
0 |
T11 |
99334 |
46 |
0 |
0 |
T12 |
0 |
28 |
0 |
0 |