Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1986	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2007	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2039	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2178	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1947	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1861	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1844	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1888	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2071	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1937	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1941	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1905	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1753	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2077	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2003	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1886	0	0
adc_en_ctl_rd_A	2147483647	1529	0	0
adc_fsm_rst_rd_A	2147483647	1533	0	0
adc_intr_ctl_rd_A	2147483647	2038	0	0
adc_lp_sample_ctl_rd_A	2147483647	1391	0	0
adc_pd_ctl_rd_A	2147483647	1840	0	0
adc_sample_ctl_rd_A	2147483647	1313	0	0
adc_wakeup_ctl_rd_A	2147483647	1566	0	0
intr_enable_rd_A	2147483647	2135	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1986	0	0
T3	753456	34	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	24	0	0
T14	0	15	0	0
T15	0	28	0	0
T16	0	47	0	0
T17	0	25	0	0
T18	0	15	0	0
T19	0	50	0	0
T20	0	14	0	0
T21	0	36	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2007	0	0
T3	753456	32	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	24	0	0
T14	0	9	0	0
T15	0	3	0	0
T16	0	29	0	0
T17	0	33	0	0
T18	0	2	0	0
T19	0	53	0	0
T20	0	8	0	0
T21	0	35	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2039	0	0
T3	753456	18	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	21	0	0
T14	0	17	0	0
T15	0	13	0	0
T16	0	39	0	0
T17	0	29	0	0
T18	0	21	0	0
T19	0	40	0	0
T20	0	10	0	0
T21	0	30	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2178	0	0
T3	753456	25	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	34	0	0
T14	0	29	0	0
T15	0	15	0	0
T16	0	39	0	0
T17	0	30	0	0
T18	0	13	0	0
T19	0	33	0	0
T20	0	21	0	0
T21	0	52	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1947	0	0
T3	753456	40	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	35	0	0
T14	0	27	0	0
T15	0	19	0	0
T16	0	32	0	0
T17	0	26	0	0
T18	0	7	0	0
T19	0	58	0	0
T20	0	5	0	0
T21	0	65	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1861	0	0
T3	753456	43	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	23	0	0
T14	0	22	0	0
T15	0	20	0	0
T16	0	23	0	0
T17	0	45	0	0
T18	0	10	0	0
T19	0	29	0	0
T20	0	20	0	0
T21	0	51	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1844	0	0
T3	753456	33	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	32	0	0
T14	0	7	0	0
T15	0	21	0	0
T16	0	39	0	0
T17	0	33	0	0
T18	0	3	0	0
T19	0	33	0	0
T20	0	14	0	0
T21	0	35	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1888	0	0
T3	753456	28	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	23	0	0
T14	0	8	0	0
T15	0	15	0	0
T16	0	37	0	0
T17	0	39	0	0
T18	0	5	0	0
T19	0	40	0	0
T20	0	9	0	0
T21	0	35	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2071	0	0
T3	753456	26	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	17	0	0
T14	0	21	0	0
T15	0	24	0	0
T16	0	29	0	0
T17	0	63	0	0
T18	0	1	0	0
T19	0	45	0	0
T20	0	18	0	0
T21	0	45	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1937	0	0
T3	753456	16	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	20	0	0
T14	0	26	0	0
T15	0	21	0	0
T16	0	29	0	0
T17	0	42	0	0
T18	0	9	0	0
T19	0	32	0	0
T20	0	12	0	0
T21	0	47	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1941	0	0
T3	753456	33	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	8	0	0
T14	0	25	0	0
T15	0	25	0	0
T16	0	47	0	0
T17	0	43	0	0
T18	0	11	0	0
T19	0	51	0	0
T20	0	3	0	0
T21	0	36	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1905	0	0
T3	753456	11	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	29	0	0
T14	0	20	0	0
T15	0	18	0	0
T16	0	40	0	0
T17	0	29	0	0
T18	0	7	0	0
T19	0	45	0	0
T20	0	16	0	0
T21	0	31	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1753	0	0
T3	753456	29	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	32	0	0
T14	0	17	0	0
T15	0	25	0	0
T16	0	41	0	0
T17	0	42	0	0
T18	0	19	0	0
T19	0	26	0	0
T20	0	7	0	0
T21	0	31	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2077	0	0
T3	753456	29	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	18	0	0
T14	0	25	0	0
T15	0	21	0	0
T16	0	48	0	0
T17	0	39	0	0
T18	0	9	0	0
T19	0	46	0	0
T20	0	8	0	0
T21	0	43	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2003	0	0
T3	753456	37	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	33	0	0
T14	0	17	0	0
T15	0	22	0	0
T16	0	34	0	0
T17	0	29	0	0
T18	0	3	0	0
T19	0	34	0	0
T20	0	9	0	0
T21	0	40	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1886	0	0
T3	753456	40	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	14	0	0
T14	0	16	0	0
T15	0	21	0	0
T16	0	43	0	0
T17	0	38	0	0
T18	0	12	0	0
T19	0	37	0	0
T20	0	19	0	0
T21	0	42	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1529	0	0
T3	753456	40	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	29	0	0
T14	0	15	0	0
T15	0	21	0	0
T16	0	36	0	0
T17	0	49	0	0
T18	0	5	0	0
T19	0	39	0	0
T20	0	7	0	0
T21	0	26	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1533	0	0
T3	753456	32	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	13	0	0
T14	0	18	0	0
T15	0	22	0	0
T16	0	42	0	0
T17	0	54	0	0
T18	0	8	0	0
T19	0	45	0	0
T20	0	16	0	0
T21	0	38	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2038	0	0
T3	753456	34	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	23	0	0
T14	0	16	0	0
T15	0	16	0	0
T16	0	42	0	0
T17	0	43	0	0
T18	0	8	0	0
T19	0	29	0	0
T20	0	8	0	0
T21	0	36	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1391	0	0
T3	753456	54	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	27	0	0
T14	0	22	0	0
T15	0	23	0	0
T16	0	24	0	0
T17	0	38	0	0
T18	0	6	0	0
T19	0	46	0	0
T20	0	12	0	0
T21	0	23	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1840	0	0
T3	753456	27	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	19	0	0
T14	0	12	0	0
T15	0	24	0	0
T16	0	15	0	0
T17	0	37	0	0
T18	0	12	0	0
T19	0	38	0	0
T20	0	21	0	0
T21	0	40	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1313	0	0
T3	753456	28	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	36	0	0
T14	0	20	0	0
T15	0	19	0	0
T16	0	31	0	0
T17	0	28	0	0
T18	0	10	0	0
T19	0	44	0	0
T20	0	2	0	0
T21	0	40	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1566	0	0
T3	753456	44	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	32	0	0
T14	0	23	0	0
T15	0	19	0	0
T16	0	35	0	0
T17	0	28	0	0
T18	0	12	0	0
T19	0	42	0	0
T20	0	15	0	0
T21	0	23	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2135	0	0
T3	753456	52	0	0
T4	101832	0	0	0
T5	401397	0	0	0
T6	845588	0	0	0
T7	502213	0	0	0
T8	217010	0	0	0
T9	492749	0	0	0
T10	944239	0	0	0
T11	391030	0	0	0
T12	695736	0	0	0
T13	0	26	0	0
T14	0	21	0	0
T15	0	26	0	0
T16	0	23	0	0
T17	0	68	0	0
T18	0	13	0	0
T22	0	4	0	0
T23	0	5	0	0
T24	0	5	0	0