Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6543	1			T9	6		T10	20		T12	72
testmodes[AdcCtrlTestmodeNormal]	5304	1			T1	2		T3	2		T4	2
testmodes[AdcCtrlTestmodeLowpower]	5391	1			T2	1		T5	2		T6	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3437	1			T9	4		T10	19		T12	29
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1696	1			T9	2		T12	26		T68	14
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1309	1			T12	17		T68	12		T47	15
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1705	1			T9	1		T12	21		T68	16
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1942	1			T1	1		T3	1		T4	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1307	1			T12	15		T68	10		T47	12
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1288	1			T12	21		T68	10		T47	13
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1317	1			T12	10		T68	12		T47	13
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2537	1			T5	1		T6	2		T7	2