| | | | | | | |
tb.dut.AdcKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.AlertsKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 2147483647 | 70 | 0 | 0 |
|
tb.dut.IntrKnown
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.TlOAReadyKnown
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.TlODValidKnown
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.WakeKnown
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_0_rd_A
| 0 | 0 | 2147483647 | 1972 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_1_rd_A
| 0 | 0 | 2147483647 | 1922 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_2_rd_A
| 0 | 0 | 2147483647 | 1538 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_3_rd_A
| 0 | 0 | 2147483647 | 1894 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_4_rd_A
| 0 | 0 | 2147483647 | 2061 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_5_rd_A
| 0 | 0 | 2147483647 | 2166 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_6_rd_A
| 0 | 0 | 2147483647 | 1996 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_7_rd_A
| 0 | 0 | 2147483647 | 1835 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_0_rd_A
| 0 | 0 | 2147483647 | 1978 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_1_rd_A
| 0 | 0 | 2147483647 | 2008 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_2_rd_A
| 0 | 0 | 2147483647 | 1822 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_3_rd_A
| 0 | 0 | 2147483647 | 2093 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_4_rd_A
| 0 | 0 | 2147483647 | 2057 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_5_rd_A
| 0 | 0 | 2147483647 | 1838 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_6_rd_A
| 0 | 0 | 2147483647 | 1823 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_7_rd_A
| 0 | 0 | 2147483647 | 1978 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_en_ctl_rd_A
| 0 | 0 | 2147483647 | 1673 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_fsm_rst_rd_A
| 0 | 0 | 2147483647 | 1460 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_intr_ctl_rd_A
| 0 | 0 | 2147483647 | 2304 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_lp_sample_ctl_rd_A
| 0 | 0 | 2147483647 | 1516 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_pd_ctl_rd_A
| 0 | 0 | 2147483647 | 1810 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_sample_ctl_rd_A
| 0 | 0 | 2147483647 | 1416 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_wakeup_ctl_rd_A
| 0 | 0 | 2147483647 | 1700 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.intr_enable_rd_A
| 0 | 0 | 2147483647 | 2438 | 0 | 0 |
|
tb.dut.tlul_assert_device.aKnown_A
| 0 | 0 | 2147483647 | 22777869 | 0 | 0 |
|
tb.dut.tlul_assert_device.aKnown_AKnownEnable
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.tlul_assert_device.aReadyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.tlul_assert_device.dKnown_A
| 0 | 0 | 2147483647 | 4843707 | 0 | 0 |
|
tb.dut.tlul_assert_device.dKnown_AKnownEnable
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.tlul_assert_device.dReadyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.aDataKnown_M
| 0 | 0 | 2147483647 | 15137197 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A
| 0 | 0 | 2147483647 | 3521 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.contigMask_M
| 0 | 0 | 2147483647 | 13756630 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.dDataKnown_A
| 0 | 0 | 2147483647 | 4015571 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A
| 0 | 0 | 2147483647 | 3355 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAParam_M
| 0 | 0 | 2147483647 | 22777960 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalDParam_A
| 0 | 0 | 2147483647 | 4843766 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M
| 0 | 0 | 2147483647 | 22777960 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A
| 0 | 0 | 2147483647 | 4843766 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respOpcode_A
| 0 | 0 | 2147483647 | 4843766 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A
| 0 | 0 | 2147483647 | 4843766 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A
| 0 | 0 | 2147483647 | 2945 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A
| 0 | 0 | 2147483647 | 3193 | 0 | 0 |
|
tb.dut.tlul_assert_device.p_dbw.TlDbw_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.MaxFilters_A
| 0 | 0 | 34564869 | 34260785 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck00_A
| 0 | 0 | 34564869 | 9761408 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck01_A
| 0 | 0 | 34564869 | 2596959 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck10_A
| 0 | 0 | 34564869 | 2977853 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck11_A
| 0 | 0 | 34564869 | 18924565 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck00_A
| 0 | 0 | 34564869 | 11864896 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck01_A
| 0 | 0 | 34564869 | 1280747 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck10_A
| 0 | 0 | 34564869 | 1200579 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck11_A
| 0 | 0 | 34564869 | 19914563 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck00_A
| 0 | 0 | 34564869 | 11990952 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck01_A
| 0 | 0 | 34564869 | 866148 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck10_A
| 0 | 0 | 34564869 | 836301 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck11_A
| 0 | 0 | 34564869 | 20567384 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck00_A
| 0 | 0 | 34564869 | 12583829 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck01_A
| 0 | 0 | 34564869 | 247517 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck10_A
| 0 | 0 | 34564869 | 475794 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck11_A
| 0 | 0 | 34564869 | 20953645 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck00_A
| 0 | 0 | 34564869 | 13224137 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck01_A
| 0 | 0 | 34564869 | 33031 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck10_A
| 0 | 0 | 34564869 | 101 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck11_A
| 0 | 0 | 34564869 | 21003516 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck00_A
| 0 | 0 | 34564869 | 14115263 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck01_A
| 0 | 0 | 34564869 | 20 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck10_A
| 0 | 0 | 34564869 | 36600 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck11_A
| 0 | 0 | 34564869 | 20108902 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck00_A
| 0 | 0 | 34564869 | 12614239 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck01_A
| 0 | 0 | 34564869 | 104786 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck10_A
| 0 | 0 | 34564869 | 140166 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck11_A
| 0 | 0 | 34564869 | 21401594 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck00_A
| 0 | 0 | 34564869 | 13404416 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck01_A
| 0 | 0 | 34564869 | 164849 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck10_A
| 0 | 0 | 34564869 | 98007 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck11_A
| 0 | 0 | 34564869 | 20593513 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.LpSampleCntCfg_M
| 0 | 0 | 32235969 | 32156042 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrMisMatch_A
| 0 | 0 | 32235969 | 172924 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A
| 0 | 0 | 32235969 | 92310 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpSampleCntCfg_M
| 0 | 0 | 32235969 | 32156042 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmDebugOut_A
| 0 | 0 | 32235969 | 32156042 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmStateHwReset_A
| 0 | 0 | 1144 | 1144 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmStateSwReset_A
| 0 | 0 | 32235969 | 6682 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.LpSampleCntHwReset_A
| 0 | 0 | 1144 | 1144 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.LpSampleCntSwReset_A
| 0 | 0 | 32235969 | 6682 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.NpSampleCntHwReset_A
| 0 | 0 | 1144 | 1144 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.NpSampleCntSwReset_A
| 0 | 0 | 32235969 | 6682 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.PwrupTimerCntHwReset_A
| 0 | 0 | 1144 | 1144 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.PwrupTimerCntSwReset_A
| 0 | 0 | 32235969 | 6682 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.WakeupTimerCntHwReset_A
| 0 | 0 | 1144 | 1144 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.WakeupTimerCntSwReset_A
| 0 | 0 | 32235969 | 6682 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o.IntrTKind_A
| 0 | 0 | 755 | 755 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 2147483647 | 17060 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.SyncReqAckHoldReq
| 0 | 0 | 34564869 | 17060 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.DstPulseCheck_A
| 0 | 0 | 2147483647 | 6090 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.SrcPulseCheck_M
| 0 | 0 | 34564869 | 6092 | 0 | 0 |
|
tb.dut.u_reg.en2addrHit
| 0 | 0 | 2147483647 | 2411171 | 0 | 0 |
|
tb.dut.u_reg.reAfterRv
| 0 | 0 | 2147483647 | 2411171 | 0 | 0 |
|
tb.dut.u_reg.rePulse
| 0 | 0 | 2147483647 | 2122058 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1822068 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2147 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2147 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 2147 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 2088 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2157 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1665903 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1998 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1998 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 1998 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 1943 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2009 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1702130 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2035 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2035 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 2035 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 1973 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2045 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1661465 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2013 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2013 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 2013 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 1954 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2024 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1655840 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2019 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2019 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 2019 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 1965 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2032 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1663018 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2018 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2018 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 2018 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 1963 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2030 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1667943 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2037 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2037 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 2037 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 1975 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2047 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1622622 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1997 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1997 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 1997 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 1935 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2006 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1769401 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2141 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2141 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 2141 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 2081 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2152 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1624433 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2003 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2003 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 2003 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 1944 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2014 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1644397 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2018 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2018 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 2018 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 1961 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2029 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1669807 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2050 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2050 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 2050 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 1990 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2063 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1642140 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2041 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2041 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 2041 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 1978 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2051 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1604970 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2003 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2003 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 2003 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 1942 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2013 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1628712 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2012 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2012 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 2012 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 1953 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2023 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1641880 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2030 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2030 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 2030 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 1970 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2041 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 34652062 | 647911 | 0 | 920 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 34652062 | 648096 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 2147483647 | 648107 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 34652062 | 647803 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 34652062 | 633544 | 0 | 920 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 34652062 | 641302 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 2147483647 | 641306 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 34652062 | 630977 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 31804127 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 36609 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 36609 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 36620 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 36545 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 36666 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 16434022 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 19237 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 19237 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 19237 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 19178 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 19249 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 101464 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 87 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 34652062 | 3263623 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 2147483647 | 3263747 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 34652062 | 1691764 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 78 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 365 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 11364842 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 13770 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 13770 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 13770 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 13684 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 13815 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 14760780 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 17491 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 17491 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 17491 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 17433 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 17506 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 11402888 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 13754 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 13754 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 13754 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 13671 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 13799 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1132427 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1475 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1475 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 34652062 | 1475 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 1421 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 1485 | 0 | 0 |
|
tb.dut.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 62700151 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.DstReqKnown_A
| 0 | 0 | 34652062 | 34315644 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 68820 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 34652062 | 15243 | 0 | 920 |
|
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 34652062 | 15311 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 2147483647 | 84131 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 34652062 | 83180 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 34652062 | 68766 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 68832 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 920 | 920 | 0 | 0 |
|
tb.dut.u_reg.wePulse
| 0 | 0 | 2147483647 | 289113 | 0 | 0 |
|