Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25424

1

T1

34

T2

11

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21782

1

T2

11

T3

16

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

3642

1

T1

34

T5

45

T7

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19305

1

T1

19

T2

11

T5

18

auto[1]

6119

1

T1

15

T3

16

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21406

1

T1

25

T2

11

T3

2

auto[1]

4018

1

T1

9

T3

14

T5

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	95	1			T223	27		T45	24		T224	1
values[1]	581	1			T5	18		T7	15		T65	13
values[2]	562	1			T12	6		T65	17		T164	1
values[3]	852	1			T59	13		T62	9		T67	3
values[4]	590	1			T2	11		T59	12		T67	29
values[5]	769	1			T1	15		T7	19		T177	7
values[6]	681	1			T47	7		T48	14		T177	10
values[7]	712	1			T158	1		T56	12		T176	1
values[8]	816	1			T1	19		T158	2		T57	35
values[9]	3461	1			T3	16		T4	2		T5	27
minimum	16305	1			T9	12		T10	20		T12	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	753	1			T5	18		T65	13		T164	2
values[1]	700	1			T7	15		T12	6		T65	17
values[2]	658	1			T62	3		T67	3		T181	9
values[3]	769	1			T2	11		T7	7		T59	12
values[4]	741	1			T7	12		T177	17		T159	5
values[5]	724	1			T1	15		T158	1		T47	7
values[6]	2804	1			T3	16		T4	2		T6	44
values[7]	867	1			T1	19		T5	27		T158	1
values[8]	828	1			T160	11		T179	11		T117	2
values[9]	248	1			T157	1		T56	12		T62	15
minimum	16332	1			T9	12		T10	20		T12	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

4168

1

T1

23

T2

10

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T164	2		T225	11		T226	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T5	15		T65	6		T172	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	1		T65	7		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	15		T77	16		T153	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T62	1		T181	9		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T67	1		T153	12		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	11		T59	1		T49	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	7		T67	15		T49	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T7	12		T177	7		T159	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T177	10		T179	10		T227	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T47	5		T48	3		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	13		T158	1		T56	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1499	1			T3	2		T4	2		T6	44
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T176	1		T182	1		T172	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T158	1		T176	1		T229	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T1	12		T5	15		T57	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T117	1		T121	1		T180	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T160	11		T179	11		T230	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T62	1		T205	11		T196	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T157	1		T56	8		T231	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16180	1			T9	12		T10	20		T12	169
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T225	8		T226	3		T113	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	3		T65	7		T172	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	5		T65	10		T59	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T77	14		T153	10		T120	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T62	2		T226	8		T172	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T67	2		T153	11		T232	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T59	11		T49	1		T77	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T67	14		T49	7		T114	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T51	6		T114	6		T120	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T227	12		T233	11		T234	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T47	2		T48	11		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	2		T56	4		T52	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	949	1			T3	14		T8	24		T133	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T182	12		T172	17		T50	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T229	12		T228	11		T165	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	7		T5	12		T57	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T117	1		T34	6		T197	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T230	6		T196	1		T168	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T62	14		T196	16		T44	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T56	4		T53	1		T235	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T47	1		T13	1		T52	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T45	12		T224	1		T236	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T223	14		T237	1		T238	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T157	1		T164	2		T225	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T5	15		T7	15		T65	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T12	1		T65	7		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T77	16		T153	1		T239	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T59	1		T62	2		T181	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T67	1		T153	23		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	11		T59	1		T49	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T67	15		T114	1		T230	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T7	12		T177	7		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	13		T7	7		T49	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T47	5		T48	3		T159	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T177	10		T173	16		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T159	14		T228	1		T113	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T158	1		T56	8		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T158	2		T228	1		T165	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T1	12		T57	19		T225	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1622	1			T3	2		T4	2		T6	44
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	528	1			T5	15		T157	1		T56	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16164	1			T9	12		T10	20		T12	169
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T45	12		T240	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T223	13		T238	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T225	8		T226	3		T30	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T5	3		T65	7		T120	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	5		T65	10		T120	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T77	14		T153	1		T172	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T59	12		T62	7		T172	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T67	2		T153	20		T241	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T59	11		T77	13		T226	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T67	14		T114	8		T230	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T49	1		T114	17		T120	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T1	2		T49	7		T118	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T47	2		T48	11		T51	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T52	3		T168	8		T242	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T228	2		T117	6		T243	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T56	4		T182	12		T172	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T228	11		T165	9		T34	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T1	7		T57	16		T225	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T3	14		T8	24		T133	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T5	12		T56	4		T53	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	1		T13	1		T52	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T164	2		T225	9		T226	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	4		T65	8		T172	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	6		T65	11		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	1		T77	15		T153	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T62	3		T181	1		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T67	3		T153	12		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	1		T59	12		T49	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	1		T67	15		T49	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T7	1		T177	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T177	1		T179	1		T227	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T47	5		T48	14		T228	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	3		T158	1		T56	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T3	16		T4	2		T6	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T176	1		T182	13		T172	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T158	1		T176	1		T229	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T1	8		T5	13		T57	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T117	2		T121	1		T180	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T160	1		T179	1		T230	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T62	15		T205	1		T196	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T157	1		T56	5		T231	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16318	1			T9	12		T10	20		T12	169
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T225	10		T226	2		T113	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T5	14		T65	5		T172	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T65	6		T244	14		T120	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	14		T77	15		T153	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T181	8		T159	12		T172	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T153	11		T245	7		T246	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	10		T49	5		T77	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	6		T67	14		T49	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	11		T177	6		T159	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T177	9		T179	9		T227	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T47	2		T247	10		T106	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	12		T56	7		T173	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1173	1			T6	41		T11	11		T66	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T172	16		T50	1		T52	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T229	14		T165	7		T166	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	11		T5	14		T57	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T180	9		T248	4		T197	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T160	10		T179	10		T230	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T205	10		T196	15		T44	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T56	7		T231	9		T53	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T249	3		T250	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T45	13		T224	1		T236	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T223	14		T237	1		T238	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T157	1		T164	2		T225	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T5	4		T7	1		T65	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	6		T65	11		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T77	15		T153	2		T239	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T59	13		T62	9		T181	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T67	3		T153	22		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	1		T59	12		T49	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T67	15		T114	9		T230	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	1		T177	1		T49	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	3		T7	1		T49	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T47	5		T48	14		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T177	1		T173	1		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T159	1		T228	3		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T158	1		T56	5		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T158	2		T228	12		T165	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T1	8		T57	17		T225	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T3	16		T4	2		T6	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T5	13		T157	1		T56	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16305	1			T9	12		T10	20		T12	169
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T45	11		T236	9		T240	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T223	13		T238	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T225	10		T226	2		T113	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T5	14		T7	14		T65	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T65	6		T120	3		T246	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T77	15		T172	17		T251	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T181	8		T159	12		T172	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T153	21		T241	9		T168	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	10		T49	5		T77	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T67	14		T230	9		T234	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	11		T177	6		T120	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	12		T7	6		T49	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T47	2		T159	4		T51	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T177	9		T173	15		T168	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T159	13		T113	8		T243	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T56	7		T172	16		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T165	7		T166	5		T180	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	11		T57	18		T225	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T6	41		T11	11		T66	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	451	1			T5	14		T56	7		T160	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

auto[0]

4168

1

T1

23

T2

10

T5

28

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25424

1

T1

34

T2

11

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21531

1

T1

15

T3

16

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

3893

1

T1

19

T2

11

T5

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19397

1

T1

19

T5

45

T9

12

auto[1]

6027

1

T1

15

T2

11

T3

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21406

1

T1

25

T2

11

T3

2

auto[1]

4018

1

T1

9

T3

14

T5

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T252	1		-	-		-	-
values[0]	47	1			T253	15		T254	10		T240	21
values[1]	575	1			T7	7		T65	17		T157	1
values[2]	2905	1			T3	16		T4	2		T6	44
values[3]	458	1			T57	35		T62	6		T176	1
values[4]	816	1			T1	19		T7	15		T12	6
values[5]	819	1			T1	15		T157	1		T158	1
values[6]	631	1			T62	3		T49	17		T225	11
values[7]	811	1			T2	11		T5	45		T67	29
values[8]	840	1			T56	12		T164	1		T181	9
values[9]	1216	1			T59	12		T176	1		T48	14
minimum	16305	1			T9	12		T10	20		T12	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	694	1			T7	7		T65	30		T157	1
values[1]	2906	1			T3	16		T4	2		T6	44
values[2]	686	1			T12	6		T57	35		T62	6
values[3]	732	1			T1	19		T7	15		T47	7
values[4]	785	1			T1	15		T157	1		T158	1
values[5]	696	1			T5	45		T62	3		T49	17
values[6]	656	1			T2	11		T56	12		T164	1
values[7]	964	1			T177	10		T49	6		T159	5
values[8]	835	1			T59	12		T176	1		T48	14
values[9]	144	1			T164	1		T228	12		T113	11
minimum	16326	1			T9	12		T10	20		T12	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

4168

1

T1

23

T2

10

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	7		T157	1		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T65	13		T178	1		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1512	1			T3	2		T4	2		T6	44
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T158	1		T49	1		T153	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	1		T62	1		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T57	19		T164	1		T50	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T47	5		T166	11		T231	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T1	12		T7	15		T159	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T1	13		T157	1		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T158	1		T77	16		T255	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	15		T225	17		T153	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	15		T62	1		T49	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T56	8		T205	11		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	11		T164	1		T67	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T177	10		T49	6		T159	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T51	18		T244	15		T120	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T48	3		T226	3		T239	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T59	1		T176	1		T181	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T164	1		T228	1		T113	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T248	5		T234	14		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16170	1			T9	12		T10	20		T12	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T127	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T59	12		T67	2		T30	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T65	17		T257	9		T258	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T3	14		T8	24		T133	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T49	1		T153	11		T120	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T12	5		T62	5		T114	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T57	16		T50	2		T168	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T47	2		T259	9		T168	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T1	7		T234	15		T260	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	2		T226	8		T153	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T77	14		T172	14		T197	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	12		T225	13		T153	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	3		T62	2		T49	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T56	4		T196	1		T235	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T67	14		T172	17		T243	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T229	12		T172	14		T114	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T51	6		T244	14		T120	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T48	11		T226	3		T117	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T59	11		T241	8		T227	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T228	11		T113	2		T114	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T234	11		T256	2		T240	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T47	1		T77	13		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T127	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T252	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T261	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T253	1		T254	10		T240	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	7		T157	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T65	7		T178	1		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T3	2		T4	2		T6	44
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T65	6		T158	1		T49	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T62	1		T176	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T57	19		T164	1		T50	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	1		T47	5		T166	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T1	12		T7	15		T179	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T1	13		T157	1		T225	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T158	1		T159	13		T255	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T225	6		T153	12		T165	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T62	1		T49	10		T77	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	15		T162	1		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T2	11		T5	15		T67	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T56	8		T177	10		T49	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T164	1		T181	9		T244	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T48	3		T164	1		T226	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T59	1		T176	1		T255	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16164	1			T9	12		T10	20		T12	169
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T253	14		T240	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T59	12		T67	2		T77	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T65	10		T257	9		T258	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T3	14		T8	24		T133	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T65	7		T49	1		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T62	5		T114	6		T262	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T57	16		T50	2		T120	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	5		T47	2		T120	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	7		T168	7		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	2		T225	8		T226	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T172	14		T14	2		T263	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T225	5		T153	10		T165	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T62	2		T49	7		T77	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T5	12		T264	3		T35	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T5	3		T67	14		T172	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T56	4		T229	12		T114	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T244	14		T120	14		T54	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T48	11		T226	3		T228	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T59	11		T51	6		T241	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	1		T13	1		T52	1