Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25424

1

T1

34

T2

11

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22112

1

T1

19

T2

11

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3312

1

T1

15

T7

27

T157

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19458

1

T1

19

T5

18

T7

15

auto[1]

5966

1

T1

15

T2

11

T3

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21406

1

T1

25

T2

11

T3

2

auto[1]

4018

1

T1

9

T3

14

T5

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	271	1			T158	1		T255	1		T153	23
values[0]	80	1			T12	6		T278	26		T300	1
values[1]	755	1			T5	27		T176	1		T229	27
values[2]	615	1			T164	1		T49	17		T160	11
values[3]	707	1			T158	1		T56	12		T62	15
values[4]	674	1			T157	2		T62	6		T48	14
values[5]	2732	1			T3	16		T4	2		T6	44
values[6]	699	1			T1	19		T65	13		T159	5
values[7]	600	1			T176	1		T164	1		T177	7
values[8]	689	1			T5	18		T7	7		T65	17
values[9]	1297	1			T1	15		T2	11		T7	12
minimum	16305	1			T9	12		T10	20		T12	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	654	1			T50	5		T52	4		T114	7
values[1]	695	1			T158	1		T164	1		T49	17
values[2]	733	1			T56	12		T62	15		T48	14
values[3]	2711	1			T3	16		T4	2		T6	44
values[4]	606	1			T7	15		T65	13		T181	9
values[5]	643	1			T1	19		T177	7		T49	2
values[6]	689	1			T5	18		T59	12		T176	1
values[7]	663	1			T7	7		T65	17		T158	1
values[8]	1290	1			T1	15		T2	11		T7	12
values[9]	106	1			T255	1		T117	7		T223	27
minimum	16634	1			T5	27		T9	12		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

4168

1

T1

23

T2

10

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T50	3		T114	1		T121	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T52	1		T168	12		T170	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T158	1		T164	1		T49	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T160	11		T161	2		T54	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T56	8		T62	1		T48	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T67	15		T114	1		T167	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1489	1			T3	2		T4	2		T6	44
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T157	1		T62	1		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T65	6		T181	9		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	15		T225	11		T255	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	12		T177	7		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T159	5		T51	18		T196	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	15		T176	1		T77	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T59	1		T164	1		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	7		T65	7		T57	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T158	1		T62	1		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	404	1			T2	11		T158	1		T56	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T1	13		T7	12		T47	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T255	1		T223	14		T330	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T117	1		T105	1		T331	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16310	1			T5	15		T9	12		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T231	10		T262	1		T185	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T50	2		T114	6		T259	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T52	3		T168	8		T284	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T49	7		T120	3		T241	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T54	1		T230	8		T260	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T56	4		T62	14		T48	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T67	14		T114	8		T243	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T3	14		T8	24		T133	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T62	5		T233	11		T35	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T65	7		T117	6		T257	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T225	8		T160	2		T114	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	7		T49	1		T153	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T51	6		T196	17		T256	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	3		T77	13		T182	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T59	11		T52	3		T54	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T65	10		T57	16		T225	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T62	2		T67	2		T244	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T56	4		T226	3		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T1	2		T47	2		T59	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T223	13		T294	15		T332	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T117	6		T306	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	12		T12	5		T47	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T262	6		T185	11		T15	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T158	1		T255	1		T153	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T179	10		T117	1		T227	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T12	1		T278	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T300	1		T301	1		T318	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T5	15		T176	1		T229	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T231	10		T168	12		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T164	1		T49	10		T50	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T160	11		T161	1		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T158	1		T56	8		T62	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T67	15		T161	1		T114	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T157	1		T48	3		T172	35
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T157	1		T62	1		T225	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1474	1			T3	2		T4	2		T6	44
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	15		T162	1		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	12		T65	6		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T159	5		T255	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T176	1		T177	7		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T164	1		T52	4		T54	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T5	15		T7	7		T65	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T59	1		T62	1		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	378	1			T2	11		T56	8		T225	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T1	13		T7	12		T158	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16164	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T153	11		T223	13		T315	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T117	6		T227	12		T333	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T12	5		T278	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T318	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	12		T229	12		T50	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T168	8		T262	6		T185	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T49	7		T120	3		T271	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T52	3		T54	1		T230	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T56	4		T62	14		T120	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T67	14		T114	8		T243	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T48	11		T172	31		T113	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T62	5		T225	8		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	979	1			T3	14		T8	24		T133	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T114	11		T262	9		T35	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	7		T65	7		T153	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T160	2		T51	6		T227	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T49	1		T77	13		T172	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T52	3		T54	15		T227	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T5	3		T65	10		T57	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T59	11		T62	2		T244	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T56	4		T225	5		T226	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T1	2		T47	2		T59	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	1		T13	1		T52	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T50	4		T114	7		T121	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T52	4		T168	9		T170	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T158	1		T164	1		T49	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T160	1		T161	2		T54	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T56	5		T62	15		T48	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T67	15		T114	9		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T3	16		T4	2		T6	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T157	1		T62	6		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T65	8		T181	1		T117	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	1		T225	9		T255	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	8		T177	1		T49	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T159	1		T51	13		T196	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	4		T176	1		T77	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T59	12		T164	1		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	1		T65	11		T57	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T158	1		T62	3		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T2	1		T158	1		T56	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T1	3		T7	1		T47	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T255	1		T223	14		T330	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T117	7		T105	1		T331	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16400	1			T5	13		T9	12		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T231	1		T262	7		T185	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T50	1		T271	15		T234	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T168	11		T284	1		T246	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T49	7		T120	3		T241	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T160	10		T54	1		T230	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T56	7		T172	16		T120	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T67	14		T167	16		T180	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1159	1			T6	41		T11	11		T66	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T233	10		T41	12		T190	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T65	5		T181	8		T282	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	14		T225	10		T167	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T1	11		T177	6		T172	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T159	4		T51	11		T196	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	14		T77	5		T165	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T205	10		T52	1		T248	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	6		T65	6		T57	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T177	9		T159	13		T173	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T2	10		T56	7		T226	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T1	12		T7	11		T47	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T223	13		T332	11		T307	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	14		T229	14		T166	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T231	9		T185	4		T15	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T158	1		T255	1		T153	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T179	1		T117	7		T227	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T12	6		T278	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T300	1		T301	1		T318	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T5	13		T176	1		T229	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T231	1		T168	9		T170	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T164	1		T49	10		T50	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T160	1		T161	1		T52	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T158	1		T56	5		T62	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T67	15		T161	1		T114	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T157	1		T48	14		T172	33
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T157	1		T62	6		T225	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T3	16		T4	2		T6	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	1		T162	1		T114	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	8		T65	8		T153	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T159	1		T255	1		T160	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T176	1		T177	1		T49	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T164	1		T52	6		T54	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	4		T7	1		T65	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T59	12		T62	3		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T2	1		T56	5		T225	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T1	3		T7	1		T158	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16305	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T153	11		T223	13		T310	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T179	9		T227	12		T245	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T278	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T318	11		T305	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T5	14		T229	14		T50	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T231	9		T168	11		T185	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T49	7		T120	3		T271	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T160	10		T54	1		T230	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T56	7		T120	13		T241	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T67	14		T167	16		T243	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T172	33		T113	8		T120	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T225	10		T180	10		T233	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1137	1			T6	41		T11	11		T66	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T7	14		T167	1		T190	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T1	11		T65	5		T106	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T159	4		T51	11		T248	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T177	6		T77	5		T172	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T52	1		T168	3		T184	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	14		T7	6		T65	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T205	10		T166	10		T244	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T2	10		T56	7		T225	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T1	12		T7	11		T47	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

auto[0]

4168

1

T1

23

T2

10

T5

28