Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25424

1

T1

34

T2

11

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21986

1

T1

19

T3

16

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

3438

1

T1

15

T2

11

T5

45

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19421

1

T1

15

T5

27

T7

34

auto[1]

6003

1

T1

19

T2

11

T3

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21406

1

T1

25

T2

11

T3

2

auto[1]

4018

1

T1

9

T3

14

T5

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	265	1			T7	12		T65	17		T177	17
values[0]	51	1			T227	25		T264	4		T275	22
values[1]	776	1			T5	27		T12	6		T65	13
values[2]	799	1			T1	19		T5	18		T157	1
values[3]	671	1			T7	15		T158	1		T48	14
values[4]	842	1			T7	7		T67	29		T159	5
values[5]	530	1			T157	1		T158	1		T62	15
values[6]	686	1			T158	1		T59	13		T181	9
values[7]	618	1			T2	11		T56	12		T62	6
values[8]	2981	1			T3	16		T4	2		T6	44
values[9]	900	1			T1	15		T47	7		T176	1
minimum	16305	1			T9	12		T10	20		T12	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	827	1			T1	19		T157	1		T56	12
values[1]	733	1			T5	18		T7	15		T59	12
values[2]	652	1			T158	1		T48	14		T49	6
values[3]	822	1			T7	7		T164	1		T67	29
values[4]	555	1			T157	1		T158	2		T62	15
values[5]	759	1			T2	11		T59	13		T181	9
values[6]	2729	1			T3	16		T4	2		T6	44
values[7]	763	1			T1	15		T57	35		T164	1
values[8]	894	1			T7	12		T65	17		T47	7
values[9]	153	1			T177	17		T114	7		T34	9
minimum	16537	1			T5	27		T9	12		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

4168

1

T1

23

T2

10

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	12		T157	1		T56	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T255	1		T30	1		T205	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T59	1		T159	13		T51	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	15		T7	15		T62	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T158	1		T77	16		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T48	3		T49	6		T255	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T7	7		T159	5		T160	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T164	1		T67	15		T229	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T157	1		T158	2		T62	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T176	1		T223	14		T262	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T181	9		T153	12		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T2	11		T59	1		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1545	1			T3	2		T4	2		T6	44
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T165	8		T166	11		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T57	19		T225	6		T153	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	13		T164	1		T67	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T7	12		T47	5		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T65	7		T176	1		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T177	7		T114	1		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T177	10		T41	5		T322	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16211	1			T9	12		T10	20		T12	170
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T5	15		T65	6		T77	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	7		T56	4		T117	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T30	12		T196	17		T256	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T59	11		T51	6		T52	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	3		T62	2		T225	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T77	14		T182	12		T234	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T48	11		T114	8		T120	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T50	2		T292	11		T168	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T67	14		T229	12		T172	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T62	14		T226	8		T259	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T223	13		T262	9		T190	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T153	11		T120	14		T54	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T59	12		T153	1		T227	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T3	14		T8	24		T133	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T165	9		T117	6		T118	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T57	16		T225	5		T153	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T1	2		T67	2		T113	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T47	2		T160	2		T228	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T65	10		T49	1		T114	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T114	6		T34	8		T130	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T322	13		T289	18		T323	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	5		T47	1		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T5	12		T65	7		T77	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T7	12		T177	7		T239	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T65	7		T177	10		T49	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T227	13		T275	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T264	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	1		T164	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T5	15		T65	6		T77	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	12		T157	1		T56	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	15		T62	1		T225	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T158	1		T77	16		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	15		T48	3		T49	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T7	7		T159	5		T160	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T67	15		T229	15		T114	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T157	1		T158	1		T62	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T176	1		T164	1		T172	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T158	1		T181	9		T153	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T59	1		T153	1		T53	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T56	8		T62	1		T49	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	11		T179	10		T165	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T3	2		T4	2		T6	44
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T164	1		T67	1		T231	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T47	5		T225	6		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T1	13		T176	1		T178	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16164	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T172	14		T114	6		T106	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T65	10		T49	1		T196	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T227	12		T275	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T264	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T12	5		T241	8		T53	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T5	12		T65	7		T77	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	7		T56	4		T59	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	3		T62	2		T225	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T77	14		T182	12		T52	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T48	11		T120	3		T285	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T50	2		T292	11		T168	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T67	14		T229	12		T114	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T62	14		T226	8		T197	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T172	14		T243	11		T223	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T153	11		T120	14		T259	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T59	12		T153	1		T260	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T56	4		T62	5		T49	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T165	9		T117	6		T118	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1103	1			T3	14		T8	24		T133	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T67	2		T113	2		T282	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T47	2		T225	5		T160	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	2		T114	11		T230	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	1		T13	1		T52	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	8		T157	1		T56	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T255	1		T30	13		T205	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T59	12		T159	1		T51	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	4		T7	1		T62	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T158	1		T77	15		T182	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T48	14		T49	1		T255	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	1		T159	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T164	1		T67	15		T229	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T157	1		T158	2		T62	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T176	1		T223	14		T262	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T181	1		T153	12		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	1		T59	13		T153	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T3	16		T4	2		T6	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T165	10		T166	1		T117	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T57	17		T225	6		T153	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	3		T164	1		T67	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T7	1		T47	5		T160	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T65	11		T176	1		T49	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T177	1		T114	7		T34	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T177	1		T41	1		T322	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16373	1			T9	12		T10	20		T12	175
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T5	13		T65	8		T77	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	11		T56	7		T53	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T205	10		T259	3		T196	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T159	12		T51	11		T230	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	14		T7	14		T225	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T77	15		T234	13		T197	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T49	5		T173	15		T120	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	6		T159	4		T160	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T67	14		T229	14		T172	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T166	5		T248	14		T271	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T223	13		T190	11		T267	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T181	8		T153	11		T120	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	10		T179	9		T53	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T6	41		T11	11		T66	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T165	7		T166	10		T118	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T57	18		T225	5		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	12		T231	9		T113	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	11		T47	2		T172	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T65	6		T179	10		T167	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T177	6		T334	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T177	9		T41	4		T325	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T241	9		T227	12		T311	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T5	14		T65	5		T77	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T7	1		T177	1		T239	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T65	11		T177	1		T49	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T227	13		T275	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T264	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	6		T164	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T5	13		T65	8		T77	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T1	8		T157	1		T56	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	4		T62	3		T225	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T158	1		T77	15		T182	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	1		T48	14		T49	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	1		T159	1		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T67	15		T229	13		T114	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T157	1		T158	1		T62	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T176	1		T164	1		T172	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T158	1		T181	1		T153	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T59	13		T153	2		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T56	5		T62	6		T49	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	1		T179	1		T165	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1442	1			T3	16		T4	2		T6	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T164	1		T67	3		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T47	5		T225	6		T160	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T1	3		T176	1		T178	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16305	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T7	11		T177	6		T172	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T65	6		T177	9		T325	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T227	12		T275	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T241	9		T53	3		T180	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	14		T65	5		T77	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	11		T56	7		T159	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	14		T225	10		T166	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T77	15		T168	3		T234	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	14		T49	5		T173	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	6		T159	4		T160	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T67	14		T229	14		T230	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T166	5		T184	2		T197	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T172	13		T180	8		T243	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T181	8		T153	11		T120	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T53	1		T260	9		T106	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T56	7		T49	7		T159	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	10		T179	9		T165	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T6	41		T11	11		T66	27
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T231	9		T113	8		T180	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T47	2		T225	5		T172	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T1	12		T179	10		T167	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

auto[0]

4168

1

T1

23

T2

10

T5

28