Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25424

1

T1

34

T2

11

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21815

1

T1

15

T2

11

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3609

1

T1

19

T5

18

T7

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19747

1

T1

34

T2

11

T5

27

auto[1]

5677

1

T3

16

T4

2

T5

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21406

1

T1

25

T2

11

T3

2

auto[1]

4018

1

T1

9

T3

14

T5

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	360	1			T1	19		T160	11		T231	10
values[0]	56	1			T173	16		T230	17		T34	15
values[1]	702	1			T5	18		T65	13		T56	24
values[2]	713	1			T7	7		T62	15		T255	1
values[3]	797	1			T65	17		T158	1		T62	3
values[4]	2913	1			T3	16		T4	2		T6	44
values[5]	604	1			T1	15		T5	27		T7	15
values[6]	813	1			T157	1		T62	6		T48	14
values[7]	499	1			T2	11		T157	1		T59	13
values[8]	810	1			T164	1		T67	29		T225	11
values[9]	852	1			T7	12		T57	35		T164	1
minimum	16305	1			T9	12		T10	20		T12	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	783	1			T5	18		T65	13		T56	12
values[1]	710	1			T7	7		T65	17		T158	1
values[2]	766	1			T12	6		T47	7		T62	3
values[3]	2849	1			T3	16		T4	2		T6	44
values[4]	677	1			T1	15		T5	27		T62	6
values[5]	778	1			T157	1		T59	13		T48	14
values[6]	562	1			T2	11		T157	1		T176	1
values[7]	802	1			T164	1		T67	29		T225	11
values[8]	873	1			T1	19		T7	12		T57	35
values[9]	152	1			T160	11		T172	28		T114	9
minimum	16472	1			T9	12		T10	20		T12	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

4168

1

T1

23

T2

10

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T65	6		T56	8		T164	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	15		T59	1		T181	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	7		T65	7		T62	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T158	1		T255	1		T120	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T177	7		T228	1		T50	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T12	1		T47	5		T62	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T3	2		T4	2		T6	44
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	15		T176	1		T49	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	13		T5	15		T62	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T179	11		T166	11		T248	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T67	1		T229	15		T172	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T157	1		T59	1		T48	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T2	11		T157	1		T176	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T160	1		T182	1		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T164	1		T225	6		T159	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T67	15		T228	1		T50	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T7	12		T57	19		T285	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T1	12		T164	1		T49	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T160	11		T36	8		T253	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T172	14		T114	1		T54	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16200	1			T9	12		T10	20		T12	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T56	8		T225	11		T173	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T65	7		T56	4		T77	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	3		T59	11		T230	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T65	10		T62	14		T153	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T120	4		T241	8		T196	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T228	2		T165	9		T117	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	5		T47	2		T62	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T3	14		T8	24		T133	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T49	7		T52	3		T114	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	2		T5	12		T62	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T243	11		T190	5		T197	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T67	2		T229	12		T172	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T59	12		T48	11		T244	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T51	6		T120	3		T196	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T160	2		T182	12		T114	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T225	5		T153	1		T117	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T67	14		T228	11		T50	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T57	16		T285	9		T230	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	7		T226	3		T153	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T253	14		T314	2		T335	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T172	14		T114	8		T54	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T47	1		T13	1		T52	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T56	4		T225	8		T264	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T160	11		T167	17		T230	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T1	12		T231	10		T114	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T34	1		T327	1		T309	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T173	16		T230	11		T123	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T65	6		T56	8		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	15		T56	8		T59	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	7		T62	1		T153	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T255	1		T120	12		T241	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T65	7		T50	3		T165	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T158	1		T62	1		T113	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T3	2		T4	2		T6	44
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	1		T47	5		T49	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	13		T5	15		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	15		T176	1		T179	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T62	1		T67	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T157	1		T48	3		T244	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T2	11		T157	1		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T59	1		T160	1		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T164	1		T225	6		T159	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T67	15		T228	1		T50	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T7	12		T57	19		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T164	1		T49	6		T226	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16164	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T230	13		T262	9		T35	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T1	7		T114	8		T223	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T34	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T230	6		T123	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T65	7		T56	4		T77	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	3		T56	4		T59	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T62	14		T153	11		T171	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T120	4		T241	8		T230	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T65	10		T165	9		T168	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T62	2		T113	2		T259	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T3	14		T8	24		T133	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	5		T47	2		T49	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	2		T5	12		T77	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T197	2		T246	3		T336	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T62	5		T67	2		T229	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T48	11		T244	14		T243	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T51	6		T54	15		T196	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T59	12		T160	2		T182	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T225	5		T117	1		T120	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T67	14		T228	11		T50	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T57	16		T153	1		T285	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T226	3		T153	9		T172	31
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	1		T13	1		T52	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T65	8		T56	5		T164	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	4		T59	12		T181	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	1		T65	11		T62	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T158	1		T255	1		T120	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T177	1		T228	3		T50	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	6		T47	5		T62	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T3	16		T4	2		T6	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	1		T176	1		T49	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	3		T5	13		T62	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T179	1		T166	1		T248	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T67	3		T229	13		T172	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T157	1		T59	13		T48	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T2	1		T157	1		T176	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T160	3		T182	13		T114	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T164	1		T225	6		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T67	15		T228	12		T50	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T7	1		T57	17		T285	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	8		T164	1		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T160	1		T36	1		T253	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T172	15		T114	9		T54	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16356	1			T9	12		T10	20		T12	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T56	5		T225	9		T173	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T65	5		T56	7		T77	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	14		T181	8		T159	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	6		T65	6		T153	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T120	11		T241	9		T196	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T177	6		T165	7		T168	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T47	2		T113	16		T227	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1179	1			T6	41		T11	11		T66	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	14		T49	7		T179	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	12		T5	14		T77	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T179	10		T166	10		T248	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T229	14		T172	17		T167	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T244	14		T180	8		T233	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T2	10		T51	11		T120	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T167	1		T259	3		T234	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T225	5		T159	12		T168	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T67	14		T50	1		T120	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T7	11		T57	18		T285	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	11		T49	5		T226	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T160	10		T36	7		T316	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T172	13		T54	1		T223	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T14	3		T324	1		T337	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T56	7		T225	10		T173	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T160	1		T167	1		T230	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T1	8		T231	1		T114	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T34	15		T327	1		T309	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T173	1		T230	7		T123	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T65	8		T56	5		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	4		T56	5		T59	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	1		T62	15		T153	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T255	1		T120	5		T241	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T65	11		T50	3		T165	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T158	1		T62	3		T113	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T3	16		T4	2		T6	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	6		T47	5		T49	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	3		T5	13		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T7	1		T176	1		T179	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T62	6		T67	3		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T157	1		T48	14		T244	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T2	1		T157	1		T176	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T59	13		T160	3		T182	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T164	1		T225	6		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T67	15		T228	12		T50	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	1		T57	17		T153	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T164	1		T49	1		T226	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16305	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T160	10		T167	16		T230	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T1	11		T231	9		T223	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T173	15		T230	10		T123	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T65	5		T56	7		T77	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	14		T56	7		T181	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	6		T153	11		T171	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T120	11		T241	9		T230	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T65	6		T165	7		T168	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T113	16		T227	12		T234	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T6	41		T11	11		T66	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T47	2		T49	7		T179	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	12		T5	14		T77	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	14		T179	10		T166	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T229	14		T172	17		T167	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T244	14		T180	8		T243	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T2	10		T51	11		T248	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T167	1		T64	1		T199	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T225	5		T159	12		T120	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T67	14		T50	1		T120	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	11		T57	18		T285	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T49	5		T226	2		T153	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

auto[0]

4168

1

T1

23

T2

10

T5

28