Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25424

1

T1

34

T2

11

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21862

1

T2

11

T3

16

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

3562

1

T1

34

T5

27

T7

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19303

1

T1

19

T2

11

T5

18

auto[1]

6121

1

T1

15

T3

16

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21406

1

T1

25

T2

11

T3

2

auto[1]

4018

1

T1

9

T3

14

T5

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	201	1			T157	1		T62	15		T231	10
values[0]	119	1			T65	13		T223	27		T45	24
values[1]	506	1			T5	18		T7	15		T157	1
values[2]	719	1			T12	6		T65	17		T164	1
values[3]	703	1			T59	13		T62	9		T67	3
values[4]	685	1			T2	11		T59	12		T67	29
values[5]	694	1			T1	15		T7	19		T177	17
values[6]	736	1			T47	7		T48	14		T159	5
values[7]	675	1			T158	1		T56	12		T176	1
values[8]	867	1			T1	19		T5	27		T158	2
values[9]	3214	1			T3	16		T4	2		T6	44
minimum	16305	1			T9	12		T10	20		T12	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	573	1			T5	18		T7	15		T164	1
values[1]	729	1			T12	6		T65	17		T157	1
values[2]	608	1			T62	3		T67	3		T181	9
values[3]	759	1			T2	11		T7	7		T59	12
values[4]	771	1			T1	15		T7	12		T177	17
values[5]	671	1			T158	1		T47	7		T56	12
values[6]	2837	1			T3	16		T4	2		T6	44
values[7]	869	1			T1	19		T5	27		T158	1
values[8]	883	1			T56	12		T160	11		T179	11
values[9]	179	1			T157	1		T62	15		T205	11
minimum	16545	1			T9	12		T10	20		T12	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

4168

1

T1

23

T2

10

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	15		T164	1		T113	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T7	15		T172	18		T262	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	1		T65	7		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T77	16		T153	12		T239	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T62	1		T181	9		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T67	1		T161	1		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	11		T59	1		T49	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	7		T67	15		T49	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T7	12		T177	7		T159	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	13		T177	10		T179	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T158	1		T47	5		T48	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T56	8		T182	1		T173	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1506	1			T3	2		T4	2		T6	44
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T176	1		T172	17		T50	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T158	1		T176	1		T229	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T1	12		T5	15		T57	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T179	11		T117	1		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T56	8		T160	11		T180	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T62	1		T205	11		T196	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T157	1		T231	10		T53	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16234	1			T9	12		T10	20		T12	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T65	6		T225	11		T290	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	3		T113	2		T230	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T172	14		T262	6		T34	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	5		T65	10		T59	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T77	14		T153	10		T120	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T62	2		T226	8		T153	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T67	2		T232	10		T282	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T59	11		T49	1		T77	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T67	14		T49	7		T114	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T51	6		T114	6		T120	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	2		T227	12		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T47	2		T48	11		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T56	4		T182	12		T52	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	944	1			T3	14		T8	24		T133	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T172	17		T50	2		T52	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T229	12		T165	9		T54	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T1	7		T5	12		T57	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T117	1		T230	6		T196	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T56	4		T168	7		T242	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T62	14		T196	16		T44	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T53	1		T235	18		T18	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T47	1		T226	3		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T65	7		T225	8		T338	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T62	1		T248	5		T235	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T157	1		T231	10		T37	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T223	14		T45	12		T224	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T65	6		T250	12		T238	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	15		T157	1		T164	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T7	15		T225	11		T262	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	1		T65	7		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T77	16		T153	1		T239	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T59	1		T62	2		T181	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T67	1		T153	11		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	11		T59	1		T49	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T67	15		T114	1		T54	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	12		T177	7		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	13		T7	7		T177	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T47	5		T48	3		T159	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T173	16		T162	1		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T158	1		T159	14		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T56	8		T176	1		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T158	2		T165	8		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T1	12		T5	15		T57	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1621	1			T3	2		T4	2		T6	44
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T56	8		T225	6		T160	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16164	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T62	14		T235	10		T199	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T235	18		T18	3		T339	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T223	13		T45	12		T240	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T65	7		T238	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	3		T226	3		T113	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T225	8		T262	6		T256	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	5		T65	10		T30	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T77	14		T153	1		T172	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T59	12		T62	7		T172	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T67	2		T153	9		T232	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T59	11		T77	13		T226	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T67	14		T114	8		T54	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T49	1		T114	17		T120	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	2		T49	7		T227	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T47	2		T48	11		T51	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T52	3		T118	1		T168	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T228	2		T117	6		T243	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T56	4		T182	12		T172	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T165	9		T34	6		T35	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T1	7		T5	12		T57	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T3	14		T8	24		T133	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T56	4		T225	5		T53	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	1		T13	1		T52	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	4		T164	1		T113	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	1		T172	15		T262	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T12	6		T65	11		T157	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T77	15		T153	12		T239	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T62	3		T181	1		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T67	3		T161	1		T232	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T2	1		T59	12		T49	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	1		T67	15		T49	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	1		T177	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	3		T177	1		T179	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T158	1		T47	5		T48	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T56	5		T182	13		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T3	16		T4	2		T6	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T176	1		T172	18		T50	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T158	1		T176	1		T229	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T1	8		T5	13		T57	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T179	1		T117	2		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T56	5		T160	1		T180	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T62	15		T205	1		T196	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T157	1		T231	1		T53	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16393	1			T9	12		T10	20		T12	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T65	8		T225	9		T290	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	14		T113	8		T230	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T7	14		T172	17		T190	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T65	6		T120	3		T267	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T77	15		T153	10		T120	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T181	8		T159	12		T153	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T246	2		T310	10		T199	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	10		T49	5		T77	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	6		T67	14		T49	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	11		T177	6		T159	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	12		T177	9		T179	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T47	2		T106	9		T340	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T56	7		T173	15		T118	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1182	1			T6	41		T11	11		T66	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T172	16		T50	1		T52	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T229	14		T165	7		T166	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	11		T5	14		T57	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T179	10		T180	9		T230	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T56	7		T160	10		T180	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T205	10		T196	15		T44	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T231	9		T53	3		T235	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T226	2		T223	13		T234	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T65	5		T225	10		T290	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T62	15		T248	1		T235	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T157	1		T231	1		T37	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T223	14		T45	13		T224	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T65	8		T250	1		T238	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	4		T157	1		T164	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T7	1		T225	9		T262	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	6		T65	11		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T77	15		T153	2		T239	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T59	13		T62	9		T181	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T67	3		T153	10		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T2	1		T59	12		T49	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T67	15		T114	9		T54	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	1		T177	1		T49	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	3		T7	1		T177	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T47	5		T48	14		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T173	1		T162	1		T52	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T158	1		T159	1		T228	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T56	5		T176	1		T182	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T158	2		T165	10		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T1	8		T5	13		T57	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T3	16		T4	2		T6	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T56	5		T225	6		T160	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16305	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T248	4		T235	9		T199	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T231	9		T235	16		T334	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T223	13		T45	11		T236	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T65	5		T250	11		T238	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	14		T226	2		T113	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T7	14		T225	10		T290	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T65	6		T120	3		T267	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T77	15		T172	17		T120	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T181	8		T159	12		T172	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T153	10		T168	11		T284	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	10		T49	5		T77	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T67	14		T230	9		T191	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	11		T177	6		T166	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	12		T7	6		T177	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T47	2		T159	4		T51	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T173	15		T118	5		T168	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T159	13		T113	8		T243	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T56	7		T172	16		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T165	7		T166	5		T180	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	11		T5	14		T57	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T6	41		T11	11		T66	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T56	7		T225	5		T160	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

auto[0]

4168

1

T1

23

T2

10

T5

28