Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25424

1

T1

34

T2

11

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21475

1

T1

15

T3

16

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

3949

1

T1

19

T2

11

T5

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19374

1

T1

19

T5

45

T9

12

auto[1]

6050

1

T1

15

T2

11

T3

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21406

1

T1

25

T2

11

T3

2

auto[1]

4018

1

T1

9

T3

14

T5

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	203	1			T48	14		T164	1		T239	1
values[0]	48	1			T341	3		T254	10		T342	1
values[1]	547	1			T7	7		T65	17		T157	1
values[2]	2880	1			T3	16		T4	2		T6	44
values[3]	559	1			T12	6		T57	35		T62	6
values[4]	770	1			T1	19		T7	15		T47	7
values[5]	848	1			T1	15		T157	1		T158	1
values[6]	582	1			T62	3		T49	17		T225	11
values[7]	882	1			T2	11		T5	45		T67	29
values[8]	809	1			T56	12		T164	1		T181	9
values[9]	991	1			T59	12		T176	1		T226	6
minimum	16305	1			T9	12		T10	20		T12	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	549	1			T65	30		T59	13		T67	3
values[1]	2846	1			T3	16		T4	2		T6	44
values[2]	734	1			T12	6		T47	7		T57	35
values[3]	689	1			T1	19		T7	15		T159	13
values[4]	817	1			T1	15		T157	1		T158	1
values[5]	653	1			T5	45		T62	3		T49	17
values[6]	688	1			T2	11		T56	12		T164	1
values[7]	962	1			T181	9		T177	10		T49	6
values[8]	881	1			T59	12		T176	1		T48	14
values[9]	108	1			T164	1		T228	12		T113	11
minimum	16497	1			T7	7		T9	12		T10	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

4168

1

T1

23

T2

10

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T59	1		T67	1		T177	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T65	13		T178	1		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1494	1			T3	2		T4	2		T6	44
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T158	1		T56	8		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	1		T47	5		T62	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T57	19		T50	3		T167	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T166	11		T231	10		T120	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T1	12		T7	15		T159	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	13		T157	1		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T158	1		T77	16		T255	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	15		T225	17		T153	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	15		T62	1		T49	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T56	8		T205	11		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T2	11		T164	1		T67	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T177	10		T49	6		T159	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T181	9		T51	18		T244	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T48	3		T226	3		T239	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T59	1		T176	1		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T164	1		T228	1		T113	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T248	5		T234	14		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16212	1			T7	7		T9	12		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T315	1		T86	3		T254	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T59	12		T67	2		T30	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T65	17		T257	9		T258	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T3	14		T8	24		T133	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T56	4		T49	1		T153	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T12	5		T47	2		T62	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T57	16		T50	2		T292	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T120	4		T168	8		T64	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	7		T234	15		T260	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	2		T226	8		T153	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T77	14		T172	14		T197	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	12		T225	13		T153	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	3		T62	2		T49	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T56	4		T196	1		T235	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T67	14		T172	17		T243	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T229	12		T172	14		T114	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T51	6		T244	14		T120	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T48	11		T226	3		T117	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T59	11		T241	8		T227	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T228	11		T113	2		T114	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T234	11		T256	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T47	1		T77	13		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T315	11		T86	2		T343	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T48	3		T164	1		T239	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T248	5		T227	1		T35	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T341	2		T261	1		T344	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T254	10		T342	1		T240	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T7	7		T157	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T65	7		T178	1		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T3	2		T4	2		T6	44
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T65	6		T158	1		T56	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T12	1		T62	1		T176	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T57	19		T50	3		T166	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T47	5		T166	11		T231	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T1	12		T7	15		T159	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T1	13		T157	1		T225	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T158	1		T255	1		T172	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T225	6		T153	12		T165	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T62	1		T49	10		T77	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	15		T162	1		T167	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T2	11		T5	15		T67	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T56	8		T177	10		T49	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T164	1		T181	9		T244	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T226	3		T172	14		T50	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T59	1		T176	1		T255	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16164	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T48	11		T228	11		T113	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T227	1		T35	6		T235	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T341	1		T344	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T240	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T59	12		T67	2		T77	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T65	10		T257	9		T258	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T3	14		T8	24		T133	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T65	7		T56	4		T49	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T12	5		T62	5		T114	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T57	16		T50	2		T120	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T47	2		T120	4		T168	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	7		T168	7		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	2		T225	8		T226	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T172	14		T263	10		T186	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T225	5		T153	10		T165	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T62	2		T49	7		T77	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T5	12		T196	1		T264	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T5	3		T67	14		T172	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T56	4		T229	12		T114	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T244	14		T120	14		T54	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T226	3		T172	14		T114	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T59	11		T51	6		T241	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	1		T13	1		T52	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T59	13		T67	3		T177	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T65	19		T178	1		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T3	16		T4	2		T6	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T158	1		T56	5		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	6		T47	5		T62	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T57	17		T50	4		T167	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T166	1		T231	1		T120	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T1	8		T7	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	3		T157	1		T226	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T158	1		T77	15		T255	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	13		T225	15		T153	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	4		T62	3		T49	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T56	5		T205	1		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T2	1		T164	1		T67	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T177	1		T49	1		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T181	1		T51	13		T244	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T48	14		T226	4		T239	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T59	12		T176	1		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T164	1		T228	12		T113	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T248	1		T234	12		T256	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16337	1			T7	1		T9	12		T10	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T315	12		T86	4		T254	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T177	6		T53	3		T199	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T65	11		T41	12		T235	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1162	1			T6	41		T7	11		T11	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T56	7		T153	11		T160	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T47	2		T53	1		T167	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T57	18		T50	1		T167	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T166	10		T231	9		T120	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	11		T7	14		T159	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	12		T52	1		T113	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T77	15		T172	17		T197	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	14		T225	15		T153	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	14		T49	7		T159	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T56	7		T205	10		T167	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	10		T67	14		T172	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T177	9		T49	5		T159	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T181	8		T51	11		T244	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T226	2		T166	10		T54	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T241	9		T64	1		T190	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T113	8		T302	1		T265	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T248	4		T234	13		T345	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T7	6		T77	5		T179	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T86	1		T254	9		T240	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T48	14		T164	1		T239	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T248	1		T227	2		T35	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T341	2		T261	1		T344	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T254	1		T342	1		T240	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	1		T157	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T65	11		T178	1		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T3	16		T4	2		T6	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T65	8		T158	1		T56	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T12	6		T62	6		T176	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T57	17		T50	4		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T47	5		T166	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T1	8		T7	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	3		T157	1		T225	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T158	1		T255	1		T172	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T225	6		T153	12		T165	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T62	3		T49	10		T77	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	13		T162	1		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T2	1		T5	4		T67	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T56	5		T177	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T164	1		T181	1		T244	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T226	4		T172	15		T50	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T59	12		T176	1		T255	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16305	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T113	8		T346	10		T18	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T248	4		T235	9		T290	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T341	1		T344	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T254	9		T240	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T7	6		T177	6		T77	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T65	6		T41	12		T235	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T6	41		T7	11		T11	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T65	5		T56	7		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T53	1		T247	10		T191	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T57	18		T50	1		T166	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T47	2		T166	10		T231	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	11		T7	14		T159	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	12		T225	10		T113	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T172	17		T263	13		T186	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T225	5		T153	10		T165	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T49	7		T77	15		T180	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	14		T167	1		T184	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T2	10		T5	14		T67	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T56	7		T177	9		T49	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T181	8		T244	14		T120	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T226	2		T172	13		T166	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T51	11		T241	9		T64	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

auto[0]

4168

1

T1

23

T2

10

T5

28