Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25424

1

T1

34

T2

11

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19712

1

T1

34

T2

11

T5

18

auto[ADC_CTRL_FILTER_COND_OUT]

5712

1

T3

16

T4

2

T5

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19686

1

T1

15

T7

12

T9

12

auto[1]

5738

1

T1

19

T2

11

T3

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21406

1

T1

25

T2

11

T3

2

auto[1]

4018

1

T1

9

T3

14

T5

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	243	1			T121	1		T54	17		T242	15
values[0]	38	1			T65	13		T289	25		-	-
values[1]	653	1			T7	15		T12	6		T47	7
values[2]	904	1			T1	19		T7	12		T67	3
values[3]	674	1			T5	45		T176	1		T177	7
values[4]	631	1			T1	15		T157	1		T62	3
values[5]	801	1			T65	17		T158	1		T56	12
values[6]	588	1			T178	1		T30	13		T179	10
values[7]	625	1			T56	12		T62	21		T48	14
values[8]	642	1			T7	7		T158	1		T59	13
values[9]	3320	1			T2	11		T3	16		T4	2
minimum	16305	1			T9	12		T10	20		T12	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	635	1			T7	27		T47	7		T177	10
values[1]	3034	1			T1	19		T3	16		T4	2
values[2]	657	1			T1	15		T5	45		T177	7
values[3]	668	1			T157	1		T56	12		T57	35
values[4]	838	1			T65	17		T158	1		T59	12
values[5]	649	1			T62	15		T178	1		T30	13
values[6]	559	1			T7	7		T56	12		T59	13
values[7]	687	1			T158	1		T164	2		T49	19
values[8]	1014	1			T2	11		T157	1		T158	1
values[9]	132	1			T225	19		T161	1		T232	11
minimum	16551	1			T9	12		T10	20		T12	175

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

4168

1

T1

23

T2

10

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	12		T47	5		T49	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	15		T177	10		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T1	12		T176	1		T67	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1565	1			T3	2		T4	2		T6	44
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	13		T5	15		T205	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	15		T177	7		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T157	1		T56	8		T57	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T62	1		T229	15		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T65	7		T158	1		T255	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T59	1		T181	9		T77	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T178	1		T30	1		T179	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T62	1		T114	1		T117	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	7		T62	1		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T56	8		T59	1		T48	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T158	1		T164	2		T49	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T49	1		T226	1		T244	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T2	11		T159	5		T226	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T157	1		T158	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T161	1		T242	1		T343	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T225	11		T232	1		T190	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16232	1			T9	12		T10	20		T12	170
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T65	6		T67	15		T50	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T47	2		T225	5		T172	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T117	1		T34	6		T197	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	7		T67	2		T153	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1023	1			T3	14		T8	24		T133	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T1	2		T5	3		T53	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	12		T153	1		T114	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T56	4		T57	16		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T62	2		T229	12		T43	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T65	10		T228	2		T172	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T59	11		T77	13		T52	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T30	12		T259	9		T227	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T62	14		T114	6		T117	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T62	5		T223	13		T264	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T56	4		T59	12		T48	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T49	7		T256	12		T282	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T49	1		T226	8		T244	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T226	3		T165	9		T120	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T160	2		T172	14		T120	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T242	14		T343	8		T347	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T225	8		T232	10		T190	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	5		T47	1		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T65	7		T67	14		T50	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T54	2		T242	1		T35	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T121	1		T34	1		T190	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T289	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T65	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	1		T47	5		T49	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	15		T67	15		T177	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T1	12		T7	12		T67	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T77	16		T159	14		T52	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	15		T176	1		T153	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	15		T177	7		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	13		T157	1		T153	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T62	1		T229	15		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T65	7		T158	1		T56	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T59	1		T181	9		T77	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T178	1		T30	1		T179	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T162	1		T121	1		T260	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T62	1		T164	1		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T56	8		T62	1		T48	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	7		T158	1		T164	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T59	1		T117	1		T167	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T2	11		T49	10		T159	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1736	1			T3	2		T4	2		T6	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16164	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T54	15		T242	14		T35	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T34	8		T190	5		T321	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T289	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T65	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T12	5		T47	2		T225	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T67	14		T50	2		T117	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	7		T67	2		T51	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T77	14		T52	3		T227	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	3		T153	9		T53	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	12		T228	11		T114	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	2		T153	11		T182	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T62	2		T229	12		T153	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T65	10		T56	4		T57	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T59	11		T77	13		T52	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T30	12		T114	8		T259	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T235	10		T202	12		T297	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T62	5		T223	13		T282	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T56	4		T62	14		T48	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T264	3		T106	10		T282	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T59	12		T117	6		T259	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T49	7		T226	3		T165	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1174	1			T3	14		T8	24		T133	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	1		T13	1		T52	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	1		T47	5		T49	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	1		T177	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T1	8		T176	1		T67	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1358	1			T3	16		T4	2		T6	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	3		T5	4		T205	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	13		T177	1		T153	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T157	1		T56	5		T57	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T62	3		T229	13		T43	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T65	11		T158	1		T255	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T59	12		T181	1		T77	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T178	1		T30	13		T179	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T62	15		T114	7		T117	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T62	6		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T56	5		T59	13		T48	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T158	1		T164	2		T49	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T49	2		T226	9		T244	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T2	1		T159	1		T226	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T157	1		T158	1		T160	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T161	1		T242	15		T343	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T225	9		T232	11		T190	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16359	1			T9	12		T10	20		T12	175
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T65	8		T67	15		T50	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	11		T47	2		T49	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	14		T177	9		T180	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	11		T153	10		T51	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1230	1			T6	41		T11	11		T66	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	12		T5	14		T205	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	14		T177	6		T180	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T56	7		T57	18		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T229	14		T247	10		T199	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T65	6		T172	13		T173	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T181	8		T77	5		T160	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T179	9		T184	11		T260	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T235	9		T202	10		T291	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T7	6		T223	13		T106	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T56	7		T54	1		T230	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T49	7		T167	11		T248	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T244	14		T167	16		T248	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	10		T159	4		T226	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T172	17		T166	25		T120	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T347	13		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T225	10		T190	2		T348	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T159	12		T349	5		T272	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T65	5		T67	14		T50	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T54	17		T242	15		T35	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T121	1		T34	9		T190	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T289	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T65	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	6		T47	5		T49	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	1		T67	15		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T1	8		T7	1		T67	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T77	15		T159	1		T52	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	4		T176	1		T153	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	13		T177	1		T228	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	3		T157	1		T153	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T62	3		T229	13		T153	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T65	11		T158	1		T56	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T59	12		T181	1		T77	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T178	1		T30	13		T179	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T162	1		T121	1		T260	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T62	6		T164	1		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T56	5		T62	15		T48	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	1		T158	1		T164	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T59	13		T117	7		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T2	1		T49	10		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1540	1			T3	16		T4	2		T6	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16305	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T235	16		T290	3		T350	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T190	2		T341	1		T317	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T289	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T65	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T47	2		T49	5		T225	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	14		T67	14		T177	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T1	11		T7	11		T51	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T77	15		T159	13		T180	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	14		T153	10		T205	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	14		T177	6		T243	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	12		T153	11		T113	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T229	14		T180	8		T199	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T65	6		T56	7		T57	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T181	8		T77	5		T160	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T179	9		T173	15		T227	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T235	9		T202	10		T297	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T223	13		T282	11		T199	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T56	7		T54	1		T230	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	6		T167	11		T248	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T167	16		T248	14		T168	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	10		T49	7		T159	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1370	1			T6	41		T11	11		T66	27

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

auto[0]

4168

1

T1

23

T2

10

T5

28