Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	1		T157	1		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T65	19		T178	1		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T3	16		T4	2		T6	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T158	1		T49	2		T153	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	6		T62	6		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T57	17		T164	1		T50	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T47	5		T166	1		T231	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T1	8		T7	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	3		T157	1		T226	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T158	1		T77	15		T255	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	13		T225	15		T153	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	4		T62	3		T49	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T56	5		T205	1		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	1		T164	1		T67	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T177	1		T49	1		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T51	13		T244	15		T120	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T48	14		T226	4		T239	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T59	12		T176	1		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T164	1		T228	12		T113	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T248	1		T234	12		T256	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16319	1			T9	12		T10	20		T12	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T127	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T7	6		T177	6		T179	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T65	11		T41	12		T235	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1173	1			T6	41		T7	11		T11	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T153	11		T160	10		T166	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T53	1		T247	10		T191	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T57	18		T50	1		T167	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T47	2		T166	10		T231	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	11		T7	14		T159	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	12		T52	1		T113	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T77	15		T172	17		T197	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	14		T225	15		T153	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T5	14		T49	7		T159	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T56	7		T205	10		T167	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	10		T67	14		T172	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T177	9		T49	5		T159	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T51	11		T244	14		T120	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T226	2		T166	10		T54	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T181	8		T241	9		T64	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T113	8		T251	12		T265	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T248	4		T234	13		T266	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T77	5		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T252	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T261	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T253	15		T254	1		T240	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T7	1		T157	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T65	11		T178	1		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T3	16		T4	2		T6	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T65	8		T158	1		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T62	6		T176	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T57	17		T164	1		T50	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	6		T47	5		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	8		T7	1		T179	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	3		T157	1		T225	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T158	1		T159	1		T255	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T225	6		T153	12		T165	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T62	3		T49	10		T77	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	13		T162	1		T52	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T2	1		T5	4		T67	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T56	5		T177	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T164	1		T181	1		T244	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	387	1			T48	14		T164	1		T226	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T59	12		T176	1		T255	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16305	1			T9	12		T10	20		T12	169
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T254	9		T240	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T7	6		T177	6		T77	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T65	6		T41	12		T235	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T6	41		T7	11		T11	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T65	5		T153	11		T160	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T53	1		T247	10		T267	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T57	18		T50	1		T166	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T47	2		T166	10		T231	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T1	11		T7	14		T179	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	12		T225	10		T113	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T159	12		T172	17		T14	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T225	5		T153	10		T165	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T49	7		T77	15		T180	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	14		T167	1		T184	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	10		T5	14		T67	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T56	7		T177	9		T49	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T181	8		T244	14		T120	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T226	2		T172	13		T166	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T51	11		T241	9		T248	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

auto[0]

4168

1

T1

23

T2

10

T5

28