Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25424

1

T1

34

T2

11

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21715

1

T1

15

T2

11

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3709

1

T1

19

T5

27

T7

34

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19024

1

T2

11

T9

12

T10

20

auto[1]

6400

1

T1

34

T3

16

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21406

1

T1

25

T2

11

T3

2

auto[1]

4018

1

T1

9

T3

14

T5

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	402	1			T12	7		T68	1		T47	5
values[0]	57	1			T52	7		T254	4		T281	1
values[1]	809	1			T12	6		T158	1		T62	15
values[2]	2945	1			T2	11		T3	16		T4	2
values[3]	664	1			T1	15		T65	13		T47	7
values[4]	674	1			T1	19		T157	1		T77	19
values[5]	665	1			T176	1		T164	1		T67	3
values[6]	590	1			T7	15		T158	1		T62	9
values[7]	674	1			T59	13		T164	1		T159	13
values[8]	727	1			T7	12		T157	1		T56	12
values[9]	1305	1			T7	7		T65	17		T158	1
minimum	15912	1			T9	12		T10	20		T12	162

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	987	1			T5	27		T12	6		T158	1
values[1]	3021	1			T1	15		T2	11		T3	16
values[2]	584	1			T65	13		T157	1		T47	7
values[3]	739	1			T1	19		T77	49		T159	5
values[4]	655	1			T7	15		T62	6		T176	1
values[5]	745	1			T158	1		T59	13		T62	3
values[6]	566	1			T164	1		T67	29		T255	1
values[7]	752	1			T7	12		T157	1		T56	12
values[8]	861	1			T7	7		T65	17		T158	1
values[9]	199	1			T164	1		T229	27		T205	11
minimum	16315	1			T9	12		T10	20		T12	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

4168

1

T1

23

T2

10

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	1		T62	1		T49	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T5	15		T158	1		T52	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1612	1			T1	13		T2	11		T3	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T178	1		T153	12		T251	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T65	6		T57	19		T180	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T157	1		T47	5		T49	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T77	22		T228	1		T166	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	12		T159	5		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T176	1		T164	1		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T7	15		T62	1		T67	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T158	1		T62	1		T159	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T59	1		T181	9		T255	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T255	1		T161	1		T231	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T164	1		T67	15		T166	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T157	1		T56	8		T230	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T7	12		T48	3		T159	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T158	1		T56	8		T177	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	7		T65	7		T59	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T205	11		T180	9		T282	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T164	1		T229	15		T117	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16164	1			T9	12		T10	20		T12	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T283	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	5		T62	14		T49	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T5	12		T52	3		T54	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T1	2		T3	14		T5	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T153	11		T256	10		T284	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T65	7		T57	16		T271	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T47	2		T172	14		T114	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T77	27		T228	2		T285	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T1	7		T153	1		T172	31
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T228	11		T118	1		T232	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T62	5		T67	2		T117	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T62	2		T50	2		T120	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T59	12		T165	9		T234	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T53	1		T14	2		T258	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T67	14		T117	6		T223	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T56	4		T230	8		T196	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T48	11		T52	3		T114	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T56	4		T225	5		T182	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T65	10		T59	11		T49	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T282	1		T286	11		T193	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T229	12		T117	6		T198	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	1		T13	1		T52	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	393	1			T12	7		T68	1		T47	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T257	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T281	1		T287	1		T288	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T52	4		T254	4		T289	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	1		T62	1		T49	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T158	1		T54	2		T259	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T2	11		T3	2		T4	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T5	15		T178	1		T153	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	13		T65	6		T57	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T47	5		T49	6		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T77	6		T228	1		T166	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	12		T157	1		T159	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T176	1		T164	1		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T67	1		T153	1		T160	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T158	1		T62	1		T50	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	15		T62	1		T181	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T159	13		T255	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T59	1		T164	1		T268	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T157	1		T56	8		T53	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T7	12		T48	3		T67	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T158	1		T56	8		T177	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T7	7		T65	7		T59	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15771	1			T9	12		T10	20		T12	162
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T257	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T52	3		T289	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	5		T62	14		T49	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T54	15		T259	9		T227	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T3	14		T5	3		T8	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	12		T153	11		T256	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T1	2		T65	7		T57	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T47	2		T114	6		T196	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T77	13		T228	2		T271	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	7		T172	14		T244	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T228	11		T118	1		T285	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T67	2		T153	1		T172	31
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T62	2		T50	2		T197	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T62	5		T165	9		T117	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T120	3		T241	8		T14	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T59	12		T223	12		T35	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T56	4		T53	1		T196	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T48	11		T67	14		T52	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T56	4		T225	5		T182	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T65	10		T59	11		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	1		T13	1		T52	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T12	6		T62	15		T49	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T5	13		T158	1		T52	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T1	3		T2	1		T3	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T178	1		T153	12		T251	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T65	8		T57	17		T180	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T157	1		T47	5		T49	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T77	29		T228	3		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	8		T159	1		T153	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T176	1		T164	1		T228	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	1		T62	6		T67	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T158	1		T62	3		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T59	13		T181	1		T255	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T255	1		T161	1		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T164	1		T67	15		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T157	1		T56	5		T230	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	1		T48	14		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T158	1		T56	5		T177	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T7	1		T65	11		T59	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T205	1		T180	1		T282	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T164	1		T229	13		T117	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16305	1			T9	12		T10	20		T12	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T283	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T49	7		T226	2		T173	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T5	14		T52	1		T167	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T1	12		T2	10		T5	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T153	11		T251	12		T290	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T65	5		T57	18		T180	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T47	2		T49	5		T172	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T77	20		T166	5		T285	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	11		T159	4		T172	33
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T118	5		T167	12		T39	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T7	14		T160	10		T230	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T159	12		T50	1		T166	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T181	8		T165	7		T234	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T231	9		T53	3		T14	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T67	14		T166	10		T184	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T56	7		T230	9		T248	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	11		T159	13		T179	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T56	7		T177	15		T225	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	6		T65	6		T225	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T205	10		T180	8		T193	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T229	14		T36	17		T291	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T283	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	393	1			T12	7		T68	1		T47	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T257	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T281	1		T287	1		T288	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T52	6		T254	1		T289	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	6		T62	15		T49	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T158	1		T54	17		T259	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T2	1		T3	16		T4	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	13		T178	1		T153	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T1	3		T65	8		T57	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T47	5		T49	1		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T77	14		T228	3		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	8		T157	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T176	1		T164	1		T228	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T67	3		T153	2		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T158	1		T62	3		T50	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	1		T62	6		T181	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T159	1		T255	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T59	13		T164	1		T268	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T157	1		T56	5		T53	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	1		T48	14		T67	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T158	1		T56	5		T177	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	415	1			T7	1		T65	11		T59	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15912	1			T9	12		T10	20		T12	162
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T288	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T52	1		T254	3		T289	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T49	7		T226	2		T173	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T292	10		T64	1		T251	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T2	10		T5	14		T6	41
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	14		T153	11		T167	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	12		T65	5		T57	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T47	2		T49	5		T234	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T77	5		T166	5		T180	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	11		T159	4		T172	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T118	5		T285	9		T167	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T160	10		T172	33		T227	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T50	1		T166	10		T53	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T7	14		T181	8		T165	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T159	12		T231	9		T120	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T223	7		T197	10		T185	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T56	7		T53	3		T248	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T7	11		T67	14		T179	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T56	7		T177	15		T225	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T7	6		T65	6		T225	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

auto[0]

4168

1

T1

23

T2

10

T5

28