Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25424

1

T1

34

T2

11

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19699

1

T1

34

T2

11

T5

18

auto[ADC_CTRL_FILTER_COND_OUT]

5725

1

T3

16

T4

2

T5

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19692

1

T1

15

T7

12

T9

12

auto[1]

5732

1

T1

19

T2

11

T3

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21406

1

T1

25

T2

11

T3

2

auto[1]

4018

1

T1

9

T3

14

T5

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	36	1			T225	19		T293	1		T294	16
values[0]	79	1			T65	13		T47	7		T197	31
values[1]	663	1			T7	15		T12	6		T67	29
values[2]	873	1			T1	19		T7	12		T67	3
values[3]	641	1			T5	27		T176	1		T177	7
values[4]	625	1			T1	15		T5	18		T157	1
values[5]	841	1			T65	17		T158	1		T57	35
values[6]	604	1			T178	1		T30	13		T179	10
values[7]	549	1			T56	12		T62	15		T48	14
values[8]	712	1			T7	7		T158	1		T59	13
values[9]	3496	1			T2	11		T3	16		T4	2
minimum	16305	1			T9	12		T10	20		T12	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	920	1			T7	27		T65	13		T47	7
values[1]	3000	1			T1	19		T3	16		T4	2
values[2]	658	1			T1	15		T5	45		T62	3
values[3]	616	1			T157	1		T56	12		T57	35
values[4]	801	1			T65	17		T158	1		T59	12
values[5]	708	1			T56	12		T62	15		T164	1
values[6]	563	1			T7	7		T59	13		T62	6
values[7]	669	1			T158	1		T48	14		T164	2
values[8]	933	1			T2	11		T157	1		T158	1
values[9]	229	1			T225	19		T160	3		T239	1
minimum	16327	1			T9	12		T10	20		T12	175

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

4168

1

T1

23

T2

10

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T7	12		T47	5		T49	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T7	15		T65	6		T67	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	12		T176	1		T67	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1575	1			T3	2		T4	2		T6	44
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	13		T5	15		T205	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	15		T62	1		T177	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T157	1		T56	8		T57	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T229	15		T43	1		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T65	7		T158	1		T255	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T59	1		T181	9		T77	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T164	1		T178	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T56	8		T62	1		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	7		T62	1		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T59	1		T161	1		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T158	1		T164	2		T255	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T48	3		T49	1		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T2	11		T49	10		T159	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T157	1		T158	1		T172	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T161	1		T168	4		T242	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T225	11		T160	1		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16166	1			T9	12		T10	20		T12	170
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T295	1		T266	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T47	2		T225	5		T172	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T65	7		T67	14		T50	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	7		T67	2		T153	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1033	1			T3	14		T8	24		T133	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	2		T5	3		T53	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T5	12		T62	2		T153	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T56	4		T57	16		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T229	12		T43	4		T262	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T65	10		T228	2		T172	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T59	11		T77	13		T52	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T30	12		T259	9		T227	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T56	4		T62	14		T235	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T62	5		T223	13		T264	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T59	12		T114	6		T117	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T256	12		T282	1		T245	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T48	11		T49	1		T226	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T49	7		T226	3		T165	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T172	14		T120	4		T223	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T168	7		T242	14		T256	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T225	8		T160	2		T232	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	5		T47	1		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T295	3		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T225	11		T293	1		T294	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T47	5		T289	14		T296	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T65	6		T197	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	1		T49	6		T225	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	15		T67	15		T50	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	12		T7	12		T67	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T177	10		T77	16		T159	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T176	1		T153	11		T205	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	15		T177	7		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T1	13		T5	15		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T62	1		T229	15		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T65	7		T158	1		T57	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T59	1		T181	9		T77	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T178	1		T30	1		T179	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T162	1		T121	1		T260	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T164	1		T170	1		T282	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T56	8		T62	1		T48	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	7		T158	1		T62	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T59	1		T166	11		T117	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T2	11		T159	5		T226	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1739	1			T3	2		T4	2		T6	44
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16164	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T225	8		T294	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T47	2		T289	11		T296	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T65	7		T197	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T12	5		T225	5		T172	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T67	14		T50	2		T117	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	7		T67	2		T51	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T77	14		T52	3		T227	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T153	9		T53	1		T34	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	12		T228	11		T114	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	2		T5	3		T56	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T62	2		T229	12		T153	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T65	10		T57	16		T113	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T59	11		T77	13		T52	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T30	12		T172	14		T114	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T235	10		T202	12		T297	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T282	10		T199	5		T298	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T56	4		T62	14		T48	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T62	5		T49	7		T223	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T59	12		T117	6		T259	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T226	3		T165	9		T120	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1210	1			T3	14		T8	24		T133	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	1		T13	1		T52	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T7	1		T47	5		T49	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T7	1		T65	8		T67	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	8		T176	1		T67	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1369	1			T3	16		T4	2		T6	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	3		T5	4		T205	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	13		T62	3		T177	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T157	1		T56	5		T57	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T229	13		T43	5		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T65	11		T158	1		T255	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T59	12		T181	1		T77	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T164	1		T178	1		T30	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T56	5		T62	15		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	1		T62	6		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T59	13		T161	1		T114	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T158	1		T164	2		T255	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T48	14		T49	2		T226	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T2	1		T49	10		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T157	1		T158	1		T172	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T161	1		T168	8		T242	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T225	9		T160	3		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16312	1			T9	12		T10	20		T12	175
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T295	4		T266	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	11		T47	2		T49	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T7	14		T65	5		T67	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	11		T153	10		T51	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1239	1			T6	41		T11	11		T66	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	12		T5	14		T205	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	14		T177	6		T180	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T56	7		T57	18		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T229	14		T247	10		T278	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T65	6		T172	13		T173	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T181	8		T77	5		T160	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T179	9		T184	11		T260	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T56	7		T235	9		T202	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T7	6		T223	13		T106	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T167	16		T54	1		T230	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T167	11		T248	4		T245	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T244	14		T248	14		T168	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	10		T49	7		T159	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T172	17		T166	25		T120	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T168	3		T299	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T225	10		T190	2		T299	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T266	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T225	9		T293	1		T294	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T47	5		T289	12		T296	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T65	8		T197	17		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	6		T49	1		T225	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	1		T67	15		T50	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T1	8		T7	1		T67	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T177	1		T77	15		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T176	1		T153	10		T205	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	13		T177	1		T228	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	3		T5	4		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T62	3		T229	13		T153	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T65	11		T158	1		T57	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T59	12		T181	1		T77	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T178	1		T30	13		T179	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T162	1		T121	1		T260	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T164	1		T170	1		T282	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T56	5		T62	15		T48	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	1		T158	1		T62	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T59	13		T166	1		T117	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T2	1		T159	1		T226	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1582	1			T3	16		T4	2		T6	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16305	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T225	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T47	2		T289	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T65	5		T197	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T49	5		T225	5		T159	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	14		T67	14		T50	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	11		T7	11		T51	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T177	9		T77	15		T159	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T153	10		T205	10		T231	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	14		T177	6		T180	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	12		T5	14		T56	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T229	14		T118	5		T199	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T65	6		T57	18		T113	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T181	8		T77	5		T160	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T179	9		T172	13		T173	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T235	9		T202	10		T297	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T282	11		T199	4		T298	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T56	7		T54	1		T230	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	6		T49	7		T167	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T166	10		T167	16		T248	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	10		T159	4		T226	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1367	1			T6	41		T11	11		T66	27

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

auto[0]

4168

1

T1

23

T2

10

T5

28