Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25424

1

T1

34

T2

11

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22355

1

T1

34

T2

11

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3069

1

T7

27

T157

2

T158

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19567

1

T1

19

T5

18

T7

15

auto[1]

5857

1

T1

15

T2

11

T3

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21406

1

T1

25

T2

11

T3

2

auto[1]

4018

1

T1

9

T3

14

T5

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	36	1			T254	10		T261	26		-	-
values[0]	50	1			T43	5		T300	1		T301	1
values[1]	822	1			T5	27		T12	6		T176	1
values[2]	550	1			T164	1		T49	17		T160	11
values[3]	757	1			T158	1		T56	12		T62	15
values[4]	626	1			T157	2		T48	14		T225	19
values[5]	2811	1			T3	16		T4	2		T6	44
values[6]	643	1			T1	19		T65	13		T77	19
values[7]	573	1			T7	7		T176	1		T177	7
values[8]	741	1			T5	18		T65	17		T57	35
values[9]	1510	1			T1	15		T2	11		T7	12
minimum	16305	1			T9	12		T10	20		T12	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	973	1			T5	27		T12	6		T176	1
values[1]	653	1			T158	1		T62	15		T164	1
values[2]	758	1			T56	12		T48	14		T67	29
values[3]	2755	1			T3	16		T4	2		T6	44
values[4]	535	1			T7	15		T65	13		T225	19
values[5]	670	1			T1	19		T181	9		T177	7
values[6]	627	1			T5	18		T59	12		T176	1
values[7]	766	1			T7	7		T65	17		T158	1
values[8]	1192	1			T1	15		T2	11		T7	12
values[9]	155	1			T59	13		T49	6		T117	7
minimum	16340	1			T9	12		T10	20		T12	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

4168

1

T1

23

T2

10

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T5	15		T12	1		T176	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T50	3		T52	1		T168	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T158	1		T164	1		T49	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T62	1		T160	11		T161	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T56	8		T48	3		T172	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T67	15		T114	1		T120	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1533	1			T3	2		T4	2		T6	44
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T157	2		T62	1		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T65	6		T117	1		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	15		T225	11		T255	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T1	12		T181	9		T177	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T159	5		T172	14		T196	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	15		T176	1		T77	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T59	1		T164	1		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	7		T65	7		T225	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T158	1		T57	19		T62	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	447	1			T1	13		T2	11		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T7	12		T47	5		T159	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T49	6		T223	14		T302	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T59	1		T117	1		T197	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16184	1			T9	12		T10	20		T12	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T303	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T5	12		T12	5		T229	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T50	2		T52	3		T168	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T49	7		T241	8		T242	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T62	14		T120	3		T54	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T56	4		T48	11		T172	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T67	14		T114	8		T120	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T3	14		T8	24		T133	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T62	5		T113	2		T233	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T65	7		T117	6		T257	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T225	8		T160	2		T114	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	7		T49	1		T30	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T172	14		T196	17		T256	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	3		T77	13		T153	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T59	11		T52	3		T54	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T65	10		T225	5		T77	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T57	16		T62	2		T67	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T1	2		T56	4		T226	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T47	2		T226	8		T153	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T223	13		T302	3		T294	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T59	12		T117	6		T197	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T47	1		T13	1		T52	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T254	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T261	18		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T43	1		T304	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T300	1		T301	1		T305	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T5	15		T12	1		T176	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T50	3		T120	4		T168	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T164	1		T49	10		T271	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T160	11		T161	1		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T158	1		T56	8		T50	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T62	1		T67	15		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T48	3		T172	35		T248	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T157	2		T225	11		T113	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1486	1			T3	2		T4	2		T6	44
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	15		T62	1		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	12		T65	6		T77	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T159	5		T255	1		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	7		T176	1		T177	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T172	14		T52	4		T54	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	15		T65	7		T77	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T57	19		T59	1		T62	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	521	1			T1	13		T2	11		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T7	12		T158	1		T47	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16164	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T261	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T43	4		T304	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	12		T12	5		T229	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T50	2		T120	3		T168	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T49	7		T271	13		T242	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T52	3		T54	1		T230	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T56	4		T120	14		T241	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T62	14		T67	14		T114	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T48	11		T172	31		T263	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T225	8		T113	2		T120	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T3	14		T8	24		T133	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T62	5		T114	11		T262	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	7		T65	7		T77	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T160	2		T227	1		T196	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T49	1		T165	9		T51	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T172	14		T52	3		T54	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	3		T65	10		T77	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T57	16		T59	11		T62	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T1	2		T56	4		T225	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T47	2		T59	12		T67	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	1		T13	1		T52	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T5	13		T12	6		T176	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T50	4		T52	4		T168	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T158	1		T164	1		T49	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T62	15		T160	1		T161	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T56	5		T48	14		T172	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T67	15		T114	9		T120	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T3	16		T4	2		T6	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T157	2		T62	6		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T65	8		T117	7		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	1		T225	9		T255	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T1	8		T181	1		T177	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T159	1		T172	15		T196	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	4		T176	1		T77	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T59	12		T164	1		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T7	1		T65	11		T225	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T158	1		T57	17		T62	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T1	3		T2	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	1		T47	5		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T49	1		T223	14		T302	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T59	13		T117	7		T197	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16322	1			T9	12		T10	20		T12	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T303	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T5	14		T229	14		T166	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T50	1		T168	11		T185	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T49	7		T241	9		T260	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T160	10		T120	3		T54	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T56	7		T172	16		T120	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T67	14		T120	11		T167	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T6	41		T11	11		T66	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T113	8		T53	1		T233	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T65	5		T282	11		T306	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T7	14		T225	10		T167	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	11		T181	8		T177	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T159	4		T172	13		T196	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	14		T77	5		T165	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T205	10		T52	1		T248	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	6		T65	6		T225	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T57	18		T177	9		T159	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	374	1			T1	12		T2	10		T56	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	11		T47	2		T159	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T49	5		T223	13		T307	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T197	14		T45	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T308	17		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T254	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T261	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T43	5		T304	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T300	1		T301	1		T305	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T5	13		T12	6		T176	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T50	4		T120	4		T168	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T164	1		T49	10		T271	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T160	1		T161	1		T52	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T158	1		T56	5		T50	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T62	15		T67	15		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T48	14		T172	33		T248	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T157	2		T225	9		T113	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T3	16		T4	2		T6	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	1		T62	6		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	8		T65	8		T77	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T159	1		T255	1		T160	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	1		T176	1		T177	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T172	15		T52	6		T54	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	4		T65	11		T77	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T57	17		T59	12		T62	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	450	1			T1	3		T2	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T7	1		T158	1		T47	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16305	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T254	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T261	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T304	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T305	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	14		T229	14		T166	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T50	1		T120	3		T168	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T49	7		T271	15		T234	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T160	10		T167	16		T54	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T56	7		T120	13		T241	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T67	14		T243	9		T235	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T172	33		T248	4		T41	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T225	10		T113	8		T120	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1158	1			T6	41		T11	11		T66	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	14		T167	1		T41	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T1	11		T65	5		T77	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T159	4		T248	14		T196	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	6		T177	6		T165	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T172	13		T52	1		T184	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	14		T65	6		T77	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T57	18		T205	10		T166	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	431	1			T1	12		T2	10		T56	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T7	11		T47	2		T177	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

auto[0]

4168

1

T1

23

T2

10

T5

28