Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25424

1

T1

34

T2

11

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21911

1

T1

15

T3

16

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

3513

1

T1

19

T2

11

T5

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19105

1

T9

12

T10

20

T12

162

auto[1]

6319

1

T1

34

T2

11

T3

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21406

1

T1

25

T2

11

T3

2

auto[1]

4018

1

T1

9

T3

14

T5

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	749	1			T12	7		T68	1		T47	5
values[0]	46	1			T52	7		T281	1		T287	1
values[1]	799	1			T12	6		T158	1		T62	15
values[2]	3004	1			T2	11		T3	16		T4	2
values[3]	603	1			T1	15		T5	18		T65	13
values[4]	742	1			T1	19		T157	1		T77	19
values[5]	638	1			T62	6		T176	1		T164	1
values[6]	565	1			T7	15		T158	1		T62	3
values[7]	693	1			T59	13		T164	1		T159	13
values[8]	793	1			T7	12		T157	1		T56	12
values[9]	880	1			T7	7		T65	17		T158	1
minimum	15912	1			T9	12		T10	20		T12	162

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	834	1			T5	27		T12	6		T158	1
values[1]	2958	1			T1	15		T2	11		T3	16
values[2]	595	1			T65	13		T157	1		T47	7
values[3]	730	1			T1	19		T176	1		T77	49
values[4]	623	1			T7	15		T158	1		T62	6
values[5]	694	1			T59	13		T62	3		T181	9
values[6]	644	1			T164	1		T67	29		T255	1
values[7]	715	1			T7	12		T157	1		T56	12
values[8]	969	1			T7	7		T65	17		T158	1
values[9]	131	1			T164	1		T205	11		T117	7
minimum	16531	1			T9	12		T10	20		T12	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

4168

1

T1

23

T2

10

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T62	1		T49	10		T226	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T5	15		T12	1		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1609	1			T1	13		T3	2		T4	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	11		T178	1		T153	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T57	19		T180	10		T271	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T65	6		T157	1		T47	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T176	1		T77	6		T159	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	12		T77	16		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T158	1		T164	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T7	15		T62	1		T67	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T62	1		T50	3		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T59	1		T181	9		T159	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T166	11		T120	4		T223	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T164	1		T67	15		T255	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T157	1		T56	8		T48	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	12		T49	1		T159	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T65	7		T158	1		T59	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T7	7		T56	8		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T164	1		T282	1		T286	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T205	11		T117	1		T257	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16226	1			T9	12		T10	20		T12	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T52	4		T54	2		T64	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T62	14		T49	7		T226	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	12		T12	5		T259	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T1	2		T3	14		T5	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T153	11		T233	11		T284	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T57	16		T271	13		T168	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T65	7		T47	2		T172	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T77	13		T243	11		T234	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	7		T77	14		T228	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T153	1		T228	11		T117	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T62	5		T67	2		T230	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T62	2		T50	2		T241	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T59	12		T165	9		T234	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T120	3		T223	12		T258	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T67	14		T35	6		T197	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T56	4		T48	11		T230	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T49	1		T52	3		T114	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T65	10		T59	11		T225	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T56	4		T225	8		T153	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T282	1		T286	11		T291	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T117	6		T257	8		T198	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T47	1		T13	1		T52	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T52	3		T54	15		T64	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	502	1			T12	7		T68	1		T47	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T117	1		T120	14		T257	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T281	1		T287	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T52	4		T289	14		T309	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T62	1		T49	10		T226	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	1		T158	1		T54	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T3	2		T4	2		T6	44
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T2	11		T5	15		T153	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	13		T5	15		T57	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T65	6		T47	5		T49	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T77	6		T159	5		T180	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T1	12		T157	1		T239	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T176	1		T164	1		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T62	1		T67	1		T160	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T158	1		T62	1		T50	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	15		T181	9		T255	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T231	10		T120	4		T223	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T59	1		T164	1		T159	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T157	1		T56	8		T48	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T7	12		T67	15		T159	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T65	7		T158	1		T177	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	7		T56	8		T176	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15771	1			T9	12		T10	20		T12	162
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T59	11		T256	12		T263	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T117	6		T120	14		T257	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T52	3		T289	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T62	14		T49	7		T226	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	5		T54	15		T259	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T3	14		T8	24		T133	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	12		T153	11		T233	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	2		T5	3		T57	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T65	7		T47	2		T77	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T77	13		T271	13		T234	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	7		T228	2		T172	45
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T153	1		T228	11		T118	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T62	5		T67	2		T285	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T62	2		T50	2		T117	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T165	9		T230	13		T234	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T120	3		T223	12		T14	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T59	12		T35	6		T197	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T56	4		T48	11		T64	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T67	14		T52	3		T114	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T65	10		T225	5		T229	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T56	4		T49	1		T225	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	1		T13	1		T52	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T62	15		T49	10		T226	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	13		T12	6		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1439	1			T1	3		T3	16		T4	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	1		T178	1		T153	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T57	17		T180	1		T271	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T65	8		T157	1		T47	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T176	1		T77	14		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	8		T77	15		T239	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T158	1		T164	1		T153	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	1		T62	6		T67	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T62	3		T50	4		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T59	13		T181	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T166	1		T120	4		T223	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T164	1		T67	15		T255	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T157	1		T56	5		T48	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	1		T49	2		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T65	11		T158	1		T59	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T7	1		T56	5		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T164	1		T282	2		T286	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T205	1		T117	7		T257	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16365	1			T9	12		T10	20		T12	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T52	6		T54	17		T64	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T49	7		T226	2		T173	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	14		T292	10		T235	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T1	12		T5	14		T6	41
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T2	10		T153	11		T233	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T57	18		T180	9		T271	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T65	5		T47	2		T49	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T77	5		T159	4		T243	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	11		T77	15		T172	33
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T118	5		T167	12		T39	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	14		T160	10		T230	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T50	1		T166	10		T241	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T181	8		T159	12		T165	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T166	10		T120	3		T223	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T67	14		T113	8		T197	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T56	7		T231	9		T230	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	11		T159	13		T179	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T65	6		T177	15		T225	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	6		T56	7		T225	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T291	16		T193	19		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T205	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T310	6		T86	16		T188	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T52	1		T64	1		T310	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	517	1			T12	7		T68	1		T47	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T117	7		T120	15		T257	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T281	1		T287	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T52	6		T289	12		T309	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T62	15		T49	10		T226	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	6		T158	1		T54	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T3	16		T4	2		T6	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	1		T5	13		T153	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	3		T5	4		T57	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T65	8		T47	5		T49	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T77	14		T159	1		T180	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	8		T157	1		T239	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T176	1		T164	1		T153	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T62	6		T67	3		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T158	1		T62	3		T50	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	1		T181	1		T255	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T231	1		T120	4		T223	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T59	13		T164	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T157	1		T56	5		T48	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	1		T67	15		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T65	11		T158	1		T177	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T7	1		T56	5		T176	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15912	1			T9	12		T10	20		T12	162
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T177	6		T263	13		T291	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T120	13		T311	11		T312	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T52	1		T289	13		T288	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T49	7		T226	2		T173	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T292	10		T64	1		T191	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T6	41		T11	11		T66	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	10		T5	14		T153	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	12		T5	14		T57	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T65	5		T47	2		T49	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T77	5		T159	4		T180	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	11		T172	46		T166	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T118	5		T167	12		T243	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T160	10		T285	9		T227	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T50	1		T166	10		T241	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T7	14		T181	8		T165	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T231	9		T120	3		T223	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T159	12		T197	10		T185	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T56	7		T166	10		T248	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T7	11		T67	14		T159	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T65	6		T177	9		T225	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	6		T56	7		T225	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

auto[0]

4168

1

T1

23

T2

10

T5

28