Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25424

1

T1

34

T2

11

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21853

1

T1

34

T3

16

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

3571

1

T2

11

T5

27

T7

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19592

1

T1

15

T2

11

T5

27

auto[1]

5832

1

T1

19

T3

16

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21406

1

T1

25

T2

11

T3

2

auto[1]

4018

1

T1

9

T3

14

T5

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	346	1			T65	17		T49	2		T255	1
values[0]	54	1			T159	13		T271	29		T247	11
values[1]	656	1			T158	1		T48	14		T181	9
values[2]	453	1			T7	15		T56	12		T67	3
values[3]	828	1			T157	1		T158	1		T176	1
values[4]	806	1			T1	34		T2	11		T5	18
values[5]	2795	1			T3	16		T4	2		T6	44
values[6]	708	1			T7	12		T59	13		T67	29
values[7]	608	1			T57	35		T176	1		T225	11
values[8]	778	1			T7	7		T157	1		T56	12
values[9]	1087	1			T5	27		T12	6		T47	7
minimum	16305	1			T9	12		T10	20		T12	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	631	1			T48	14		T67	3		T177	17
values[1]	569	1			T7	15		T157	1		T158	1
values[2]	828	1			T1	19		T56	12		T59	12
values[3]	2901	1			T1	15		T2	11		T3	16
values[4]	666	1			T65	13		T158	1		T49	6
values[5]	748	1			T7	12		T57	35		T59	13
values[6]	722	1			T62	15		T225	11		T172	32
values[7]	566	1			T7	7		T157	1		T56	12
values[8]	1189	1			T5	27		T12	6		T65	17
values[9]	133	1			T255	1		T242	11		T35	7
minimum	16471	1			T9	12		T10	20		T12	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

4168

1

T1

23

T2

10

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T48	3		T67	1		T177	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T77	6		T153	12		T160	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T7	15		T158	1		T244	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T157	1		T225	11		T51	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T1	12		T56	8		T59	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T176	1		T205	11		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1542	1			T1	13		T3	2		T4	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	11		T77	16		T255	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T65	6		T49	6		T165	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T158	1		T182	1		T239	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	12		T176	1		T67	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T57	19		T59	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T225	6		T172	18		T120	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T62	1		T117	1		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T157	1		T56	8		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	7		T164	1		T159	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T12	1		T65	7		T159	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T5	15		T47	5		T62	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T242	1		T272	1		T250	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T255	1		T35	1		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16254	1			T9	12		T10	20		T12	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T158	1		T168	12		T203	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T48	11		T67	2		T226	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T77	13		T153	11		T114	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T244	14		T106	12		T313	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T225	8		T51	6		T230	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	7		T56	4		T59	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T227	1		T196	1		T262	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T1	2		T3	14		T5	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T77	14		T50	2		T259	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T65	7		T165	9		T54	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T182	12		T228	2		T113	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T67	14		T160	2		T168	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T57	16		T59	12		T172	31
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T225	5		T172	14		T120	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T62	14		T117	1		T54	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T56	4		T153	1		T234	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T226	8		T120	4		T278	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T12	5		T65	10		T52	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T5	12		T47	2		T62	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T242	10		T250	4		T274	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T35	6		T256	12		T253	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T47	1		T229	12		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T168	14		T314	2		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T65	7		T230	11		T227	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T49	1		T255	1		T179	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T159	13		T271	16		T247	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T277	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T48	3		T181	9		T177	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T158	1		T77	6		T153	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	15		T56	8		T67	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T51	18		T161	1		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T158	1		T49	10		T166	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T157	1		T176	1		T225	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	25		T5	15		T59	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	11		T255	1		T50	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1519	1			T3	2		T4	2		T6	44
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T158	1		T77	16		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	12		T67	15		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T59	1		T178	1		T239	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T176	1		T225	6		T120	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T57	19		T173	16		T117	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T157	1		T56	8		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	7		T62	1		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	1		T159	14		T52	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T5	15		T47	5		T62	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16164	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T65	10		T230	6		T227	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T49	1		T35	15		T315	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T271	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T48	11		T229	12		T226	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T77	13		T153	11		T243	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T56	4		T67	2		T106	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T51	6		T114	8		T246	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T49	7		T244	14		T232	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T225	8		T230	13		T227	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	9		T5	3		T59	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T50	2		T259	9		T196	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T3	14		T8	24		T133	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T77	14		T182	12		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T67	14		T160	2		T54	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T59	12		T172	31		T53	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T225	5		T120	3		T168	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T57	16		T117	1		T54	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T56	4		T153	1		T172	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T62	14		T226	8		T234	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	5		T52	6		T114	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T5	12		T47	2		T62	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	1		T13	1		T52	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	14		T67	3		T177	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T77	14		T153	12		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	1		T158	1		T244	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T157	1		T225	9		T51	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	8		T56	5		T59	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T176	1		T205	1		T52	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T1	3		T3	16		T4	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	1		T77	15		T255	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T65	8		T49	1		T165	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T158	1		T182	13		T239	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	1		T176	1		T67	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T57	17		T59	13		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T225	6		T172	15		T120	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T62	15		T117	2		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T157	1		T56	5		T153	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	1		T164	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T12	6		T65	11		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T5	13		T47	5		T62	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T242	11		T272	1		T250	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T255	1		T35	7		T256	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16360	1			T9	12		T10	20		T12	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T158	1		T168	15		T203	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T177	15		T226	2		T231	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T77	5		T153	11		T160	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	14		T244	14		T251	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T225	10		T51	11		T167	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	11		T56	7		T49	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T205	10		T180	8		T190	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T1	12		T5	14		T6	41
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	10		T77	15		T50	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T65	5		T49	5		T165	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T113	8		T120	13		T241	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T7	11		T67	14		T53	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T57	18		T172	29		T173	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T225	5		T172	17		T120	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T227	12		T64	1		T234	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T56	7		T166	10		T113	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T7	6		T159	4		T120	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T65	6		T159	13		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T5	14		T47	2		T179	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T250	15		T274	13		T316	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T283	9		T317	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T181	8		T159	12		T229	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T168	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T65	11		T230	7		T227	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T49	2		T255	1		T179	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T159	1		T271	14		T247	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T277	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T48	14		T181	1		T177	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T158	1		T77	14		T153	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	1		T56	5		T67	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T51	13		T161	1		T114	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T158	1		T49	10		T166	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T157	1		T176	1		T225	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	11		T5	4		T59	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	1		T255	1		T50	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T3	16		T4	2		T6	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T158	1		T77	15		T182	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T7	1		T67	15		T160	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T59	13		T178	1		T239	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T176	1		T225	6		T120	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T57	17		T173	1		T117	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T157	1		T56	5		T153	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	1		T62	15		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T12	6		T159	1		T52	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	382	1			T5	13		T47	5		T62	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16305	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T65	6		T230	10		T292	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T179	9		T318	13		T272	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T159	12		T271	15		T247	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T181	8		T177	6		T229	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T77	5		T153	11		T160	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	14		T56	7		T177	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T51	11		T167	1		T290	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T49	7		T166	15		T244	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T225	10		T205	10		T180	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	23		T5	14		T180	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	10		T50	1		T191	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1186	1			T6	41		T11	11		T65	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T77	15		T113	8		T120	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T7	11		T67	14		T53	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T172	29		T53	3		T167	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T225	5		T120	3		T168	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T57	18		T173	15		T227	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T56	7		T172	17		T166	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	6		T234	13		T263	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T159	13		T52	1		T248	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T5	14		T47	2		T159	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

auto[0]

4168

1

T1

23

T2

10

T5

28