Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25424

1

T1

34

T2

11

T3

16

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22027

1

T1

19

T3

16

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

3397

1

T1

15

T2

11

T5

45

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19551

1

T1

15

T5

27

T7

34

auto[1]

5873

1

T1

19

T2

11

T3

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21406

1

T1

25

T2

11

T3

2

auto[1]

4018

1

T1

9

T3

14

T5

15

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	45	1			T114	12		T36	8		T319	16
values[0]	65	1			T161	1		T227	25		T264	4
values[1]	737	1			T5	27		T12	6		T65	13
values[2]	811	1			T1	19		T5	18		T157	1
values[3]	694	1			T7	15		T158	1		T48	14
values[4]	780	1			T67	29		T159	5		T229	27
values[5]	603	1			T7	7		T157	1		T158	1
values[6]	698	1			T158	1		T181	9		T153	25
values[7]	580	1			T2	11		T56	12		T59	13
values[8]	2971	1			T3	16		T4	2		T6	44
values[9]	1135	1			T1	15		T7	12		T65	17
minimum	16305	1			T9	12		T10	20		T12	169

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1060	1			T1	19		T5	27		T12	6
values[1]	688	1			T5	18		T7	15		T59	12
values[2]	657	1			T158	1		T48	14		T49	6
values[3]	850	1			T7	7		T164	1		T67	29
values[4]	447	1			T157	1		T158	2		T62	15
values[5]	845	1			T2	11		T59	13		T181	9
values[6]	2760	1			T3	16		T4	2		T6	44
values[7]	740	1			T1	15		T57	35		T164	1
values[8]	887	1			T7	12		T65	17		T47	7
values[9]	160	1			T177	17		T114	7		T34	9
minimum	16330	1			T9	12		T10	20		T12	169

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

4168

1

T1

23

T2

10

T5

28

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T1	12		T12	1		T157	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T5	15		T65	6		T77	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T59	1		T159	13		T51	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	15		T7	15		T62	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T158	1		T77	16		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T48	3		T49	6		T255	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T7	7		T159	5		T50	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T164	1		T67	15		T229	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T157	1		T158	2		T62	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T176	1		T226	1		T53	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T181	9		T153	12		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T2	11		T59	1		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1594	1			T3	2		T4	2		T6	44
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T166	11		T117	1		T118	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T57	19		T225	6		T153	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	13		T164	1		T67	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T7	12		T176	1		T160	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T65	7		T47	5		T49	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T114	1		T34	1		T301	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T177	17		T41	5		T313	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16176	1			T9	12		T10	20		T12	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T320	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	7		T12	5		T56	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T5	12		T65	7		T77	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T59	11		T51	6		T52	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	3		T62	2		T225	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T77	14		T182	12		T114	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T48	11		T120	3		T285	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T50	2		T292	11		T168	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T67	14		T229	12		T172	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T62	14		T259	9		T271	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T226	8		T190	15		T321	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T153	11		T120	14		T54	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T59	12		T153	1		T227	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T3	14		T8	24		T133	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T117	6		T118	1		T282	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T57	16		T225	5		T153	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T1	2		T67	2		T165	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T160	2		T172	14		T52	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T65	10		T47	2		T49	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T114	6		T34	8		T130	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T313	15		T322	13		T289	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T47	1		T13	1		T52	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T320	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T319	16		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T114	1		T36	8		T323	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T227	13		T315	1		T275	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T161	1		T264	1		T324	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	1		T164	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	15		T65	6		T77	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	12		T157	1		T56	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	15		T62	1		T225	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T158	1		T77	16		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	15		T48	3		T49	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T159	5		T50	3		T114	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T67	15		T229	15		T160	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	7		T157	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T176	1		T164	1		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T158	1		T181	9		T153	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T153	1		T53	2		T260	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T56	8		T62	1		T49	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	11		T59	1		T179	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1597	1			T3	2		T4	2		T6	44
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T164	1		T67	1		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T7	12		T176	1		T225	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T1	13		T65	7		T47	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16164	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T114	11		T323	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T227	12		T315	8		T275	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T264	3		T324	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T12	5		T241	8		T53	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	12		T65	7		T77	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	7		T56	4		T59	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	3		T62	2		T225	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T77	14		T182	12		T52	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T48	11		T120	3		T285	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T50	2		T114	8		T292	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T67	14		T229	12		T230	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T62	14		T197	2		T201	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T226	8		T172	14		T243	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T153	11		T120	14		T259	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T153	1		T260	14		T262	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T56	4		T62	5		T49	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T59	12		T165	9		T117	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1090	1			T3	14		T8	24		T133	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T67	2		T113	2		T282	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T225	5		T153	9		T160	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	2		T65	10		T47	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	1		T13	1		T52	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T1	8		T12	6		T157	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T5	13		T65	8		T77	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T59	12		T159	1		T51	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	4		T7	1		T62	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T158	1		T77	15		T182	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T48	14		T49	1		T255	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	1		T159	1		T50	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T164	1		T67	15		T229	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T157	1		T158	2		T62	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T176	1		T226	9		T53	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T181	1		T153	12		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T2	1		T59	13		T153	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T3	16		T4	2		T6	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T166	1		T117	7		T118	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T57	17		T225	6		T153	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	3		T164	1		T67	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T7	1		T176	1		T160	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T65	11		T47	5		T49	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T114	7		T34	9		T301	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T177	2		T41	1		T313	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16316	1			T9	12		T10	20		T12	169
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T320	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	11		T56	7		T241	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	14		T65	5		T77	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T159	12		T51	11		T168	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	14		T7	14		T225	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T77	15		T234	13		T197	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T49	5		T173	15		T120	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	6		T159	4		T50	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T67	14		T229	14		T160	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T166	5		T248	14		T271	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T53	1		T190	11		T267	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T181	8		T153	11		T120	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	10		T179	9		T223	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T6	41		T11	11		T66	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T166	10		T118	5		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T57	18		T225	5		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T1	12		T165	7		T231	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	11		T172	17		T52	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T65	6		T47	2		T179	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T325	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T177	15		T41	4		T266	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T275	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T319	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T114	12		T36	1		T323	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T227	13		T315	9		T275	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T161	1		T264	4		T324	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	6		T164	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T5	13		T65	8		T77	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T1	8		T157	1		T56	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	4		T62	3		T225	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T158	1		T77	15		T182	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	1		T48	14		T49	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T159	1		T50	4		T114	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T67	15		T229	13		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	1		T157	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T176	1		T164	1		T226	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T158	1		T181	1		T153	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T153	2		T53	1		T260	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T56	5		T62	6		T49	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	1		T59	13		T179	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1427	1			T3	16		T4	2		T6	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T164	1		T67	3		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	366	1			T7	1		T176	1		T225	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T1	3		T65	11		T47	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16305	1			T9	12		T10	20		T12	169
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T319	15		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T36	7		T323	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T227	12		T275	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T324	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T241	9		T53	3		T180	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	14		T65	5		T77	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	11		T56	7		T159	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T5	14		T225	10		T166	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T77	15		T168	3		T234	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	14		T49	5		T173	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T159	4		T50	1		T292	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T67	14		T229	14		T160	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	6		T166	5		T184	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T172	13		T180	8		T243	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T181	8		T153	11		T120	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T53	1		T260	9		T106	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T56	7		T49	7		T159	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	10		T179	9		T165	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T6	41		T11	11		T66	27
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T166	10		T231	9		T113	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T7	11		T225	5		T153	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T1	12		T65	6		T47	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21256

1

T1

11

T2

1

T3

16

auto[1]

auto[0]

4168

1

T1

23

T2

10

T5

28