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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.79 99.07 96.67 100.00 100.00 98.83 98.33 91.61


Total test records in report: 920
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T795 /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.959927839 Jul 22 06:05:27 PM PDT 24 Jul 22 06:18:34 PM PDT 24 332222086208 ps
T796 /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1895898378 Jul 22 06:07:09 PM PDT 24 Jul 22 06:07:37 PM PDT 24 41432549806 ps
T797 /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1834987408 Jul 22 06:05:39 PM PDT 24 Jul 22 06:18:21 PM PDT 24 332212949300 ps
T798 /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1658041666 Jul 22 06:07:58 PM PDT 24 Jul 22 06:15:44 PM PDT 24 401655462228 ps
T799 /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.639305771 Jul 22 06:06:13 PM PDT 24 Jul 22 06:21:16 PM PDT 24 496344206786 ps
T74 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.4055063744 Jul 22 06:04:03 PM PDT 24 Jul 22 06:04:09 PM PDT 24 2771566353 ps
T81 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2054708950 Jul 22 06:04:13 PM PDT 24 Jul 22 06:04:16 PM PDT 24 458849999 ps
T111 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1205857396 Jul 22 06:04:57 PM PDT 24 Jul 22 06:04:59 PM PDT 24 539229035 ps
T82 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4197341306 Jul 22 06:05:17 PM PDT 24 Jul 22 06:05:21 PM PDT 24 531299542 ps
T75 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3797436868 Jul 22 06:04:10 PM PDT 24 Jul 22 06:04:16 PM PDT 24 2482223870 ps
T134 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1010604937 Jul 22 06:03:54 PM PDT 24 Jul 22 06:03:58 PM PDT 24 542702086 ps
T78 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2433903343 Jul 22 06:03:51 PM PDT 24 Jul 22 06:04:03 PM PDT 24 4487883372 ps
T800 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2968020407 Jul 22 06:04:14 PM PDT 24 Jul 22 06:04:17 PM PDT 24 348235285 ps
T76 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2216605160 Jul 22 06:04:48 PM PDT 24 Jul 22 06:04:52 PM PDT 24 4340644931 ps
T801 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1845656685 Jul 22 06:04:11 PM PDT 24 Jul 22 06:04:13 PM PDT 24 294210821 ps
T152 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.452451355 Jul 22 06:03:58 PM PDT 24 Jul 22 06:04:01 PM PDT 24 789597485 ps
T146 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.194973708 Jul 22 06:03:51 PM PDT 24 Jul 22 06:03:56 PM PDT 24 4938951968 ps
T802 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.397397239 Jul 22 06:04:13 PM PDT 24 Jul 22 06:04:15 PM PDT 24 520818075 ps
T135 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1335280866 Jul 22 06:03:50 PM PDT 24 Jul 22 06:04:20 PM PDT 24 52210501454 ps
T803 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2889763469 Jul 22 06:03:51 PM PDT 24 Jul 22 06:03:53 PM PDT 24 400881848 ps
T804 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.890999389 Jul 22 06:04:09 PM PDT 24 Jul 22 06:04:10 PM PDT 24 420460392 ps
T90 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3823396825 Jul 22 06:04:03 PM PDT 24 Jul 22 06:04:06 PM PDT 24 556013512 ps
T79 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2565921151 Jul 22 06:04:57 PM PDT 24 Jul 22 06:05:07 PM PDT 24 4507118023 ps
T96 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1153722832 Jul 22 06:03:52 PM PDT 24 Jul 22 06:03:55 PM PDT 24 502416218 ps
T147 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2482391211 Jul 22 06:03:53 PM PDT 24 Jul 22 06:03:58 PM PDT 24 4608708060 ps
T87 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.165298031 Jul 22 06:04:11 PM PDT 24 Jul 22 06:04:15 PM PDT 24 574672603 ps
T805 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1703637532 Jul 22 06:04:01 PM PDT 24 Jul 22 06:04:03 PM PDT 24 404572258 ps
T148 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.137636146 Jul 22 06:04:53 PM PDT 24 Jul 22 06:04:58 PM PDT 24 2037822547 ps
T112 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.595091168 Jul 22 06:04:12 PM PDT 24 Jul 22 06:04:14 PM PDT 24 426773526 ps
T80 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1154849030 Jul 22 06:04:06 PM PDT 24 Jul 22 06:04:18 PM PDT 24 4154581492 ps
T806 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.273226592 Jul 22 06:04:01 PM PDT 24 Jul 22 06:04:03 PM PDT 24 461832051 ps
T807 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3771057799 Jul 22 06:07:41 PM PDT 24 Jul 22 06:07:44 PM PDT 24 408454092 ps
T122 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1422001735 Jul 22 06:04:07 PM PDT 24 Jul 22 06:04:09 PM PDT 24 505483819 ps
T149 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1719973190 Jul 22 06:04:22 PM PDT 24 Jul 22 06:04:25 PM PDT 24 362247147 ps
T88 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2355559517 Jul 22 06:04:56 PM PDT 24 Jul 22 06:05:00 PM PDT 24 555594866 ps
T808 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2367980436 Jul 22 06:04:06 PM PDT 24 Jul 22 06:04:08 PM PDT 24 344147031 ps
T89 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1791499713 Jul 22 06:04:15 PM PDT 24 Jul 22 06:04:19 PM PDT 24 410542874 ps
T809 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1642865998 Jul 22 06:04:13 PM PDT 24 Jul 22 06:04:15 PM PDT 24 348068471 ps
T94 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.997498407 Jul 22 06:03:53 PM PDT 24 Jul 22 06:03:56 PM PDT 24 504107512 ps
T150 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.13169150 Jul 22 06:03:53 PM PDT 24 Jul 22 06:04:04 PM PDT 24 2431948387 ps
T810 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1368099291 Jul 22 06:03:59 PM PDT 24 Jul 22 06:04:01 PM PDT 24 391237122 ps
T811 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.220945160 Jul 22 06:04:17 PM PDT 24 Jul 22 06:04:19 PM PDT 24 377583597 ps
T812 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3453219357 Jul 22 06:03:58 PM PDT 24 Jul 22 06:04:02 PM PDT 24 716696269 ps
T813 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2706209960 Jul 22 06:04:14 PM PDT 24 Jul 22 06:04:18 PM PDT 24 295649648 ps
T136 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3958806000 Jul 22 06:04:13 PM PDT 24 Jul 22 06:04:15 PM PDT 24 459915410 ps
T93 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1747266415 Jul 22 06:05:17 PM PDT 24 Jul 22 06:05:21 PM PDT 24 548598870 ps
T151 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1157000673 Jul 22 06:04:03 PM PDT 24 Jul 22 06:04:05 PM PDT 24 606240207 ps
T137 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1333724181 Jul 22 06:03:53 PM PDT 24 Jul 22 06:03:55 PM PDT 24 490320386 ps
T95 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3504490049 Jul 22 06:04:02 PM PDT 24 Jul 22 06:04:07 PM PDT 24 497924513 ps
T138 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.803406527 Jul 22 06:04:13 PM PDT 24 Jul 22 06:04:16 PM PDT 24 511364973 ps
T814 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2959825639 Jul 22 06:04:15 PM PDT 24 Jul 22 06:04:19 PM PDT 24 425408328 ps
T815 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.24205941 Jul 22 06:04:12 PM PDT 24 Jul 22 06:04:14 PM PDT 24 414009576 ps
T816 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1762940625 Jul 22 06:03:58 PM PDT 24 Jul 22 06:04:01 PM PDT 24 484461636 ps
T817 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2816132209 Jul 22 06:04:28 PM PDT 24 Jul 22 06:04:30 PM PDT 24 523436395 ps
T818 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2383687526 Jul 22 06:04:04 PM PDT 24 Jul 22 06:04:08 PM PDT 24 4536626182 ps
T819 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3686454662 Jul 22 06:04:02 PM PDT 24 Jul 22 06:04:05 PM PDT 24 1969102635 ps
T820 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1367998517 Jul 22 06:04:14 PM PDT 24 Jul 22 06:04:20 PM PDT 24 4878898612 ps
T821 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.4083652159 Jul 22 06:05:00 PM PDT 24 Jul 22 06:05:01 PM PDT 24 303125121 ps
T822 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2360766437 Jul 22 06:04:42 PM PDT 24 Jul 22 06:04:44 PM PDT 24 502571063 ps
T823 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.661611508 Jul 22 06:04:06 PM PDT 24 Jul 22 06:04:08 PM PDT 24 359711434 ps
T824 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2791464923 Jul 22 06:04:04 PM PDT 24 Jul 22 06:04:08 PM PDT 24 572456913 ps
T139 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.941039947 Jul 22 06:05:34 PM PDT 24 Jul 22 06:05:36 PM PDT 24 495297827 ps
T825 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.187373281 Jul 22 06:04:13 PM PDT 24 Jul 22 06:04:18 PM PDT 24 3928317623 ps
T826 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1483820142 Jul 22 06:04:13 PM PDT 24 Jul 22 06:04:16 PM PDT 24 478967161 ps
T827 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.831918179 Jul 22 06:04:09 PM PDT 24 Jul 22 06:04:11 PM PDT 24 542384045 ps
T828 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.29276370 Jul 22 06:04:06 PM PDT 24 Jul 22 06:04:09 PM PDT 24 328529290 ps
T829 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2563746337 Jul 22 06:03:52 PM PDT 24 Jul 22 06:03:55 PM PDT 24 349526820 ps
T830 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2375451021 Jul 22 06:03:53 PM PDT 24 Jul 22 06:04:00 PM PDT 24 1299205340 ps
T831 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1915812602 Jul 22 06:05:00 PM PDT 24 Jul 22 06:05:04 PM PDT 24 5494799692 ps
T832 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2257975628 Jul 22 06:04:03 PM PDT 24 Jul 22 06:04:05 PM PDT 24 507583065 ps
T833 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1338516686 Jul 22 06:03:55 PM PDT 24 Jul 22 06:06:05 PM PDT 24 52512565981 ps
T834 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3269103202 Jul 22 06:04:02 PM PDT 24 Jul 22 06:04:10 PM PDT 24 8432451407 ps
T835 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2644188316 Jul 22 06:05:17 PM PDT 24 Jul 22 06:05:29 PM PDT 24 4496249270 ps
T836 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3554282843 Jul 22 06:04:09 PM PDT 24 Jul 22 06:04:19 PM PDT 24 2412418457 ps
T207 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3200037597 Jul 22 06:04:13 PM PDT 24 Jul 22 06:04:22 PM PDT 24 8236599415 ps
T837 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3215782809 Jul 22 06:04:42 PM PDT 24 Jul 22 06:04:46 PM PDT 24 667553865 ps
T838 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.257525132 Jul 22 06:04:12 PM PDT 24 Jul 22 06:04:14 PM PDT 24 625137174 ps
T839 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1363543816 Jul 22 06:04:11 PM PDT 24 Jul 22 06:04:23 PM PDT 24 4117533718 ps
T208 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3720021488 Jul 22 06:04:02 PM PDT 24 Jul 22 06:04:06 PM PDT 24 4959324500 ps
T840 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2220408622 Jul 22 06:04:16 PM PDT 24 Jul 22 06:04:21 PM PDT 24 4557443814 ps
T140 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3771808425 Jul 22 06:03:54 PM PDT 24 Jul 22 06:03:56 PM PDT 24 403102237 ps
T841 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3283654266 Jul 22 06:04:05 PM PDT 24 Jul 22 06:04:06 PM PDT 24 333560752 ps
T842 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1145287165 Jul 22 06:04:10 PM PDT 24 Jul 22 06:04:12 PM PDT 24 4746622770 ps
T141 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1244122357 Jul 22 06:04:10 PM PDT 24 Jul 22 06:04:15 PM PDT 24 1139382257 ps
T843 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.582099233 Jul 22 06:04:14 PM PDT 24 Jul 22 06:04:18 PM PDT 24 421266217 ps
T844 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2935118123 Jul 22 06:04:13 PM PDT 24 Jul 22 06:04:16 PM PDT 24 400832514 ps
T209 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.789722520 Jul 22 06:03:56 PM PDT 24 Jul 22 06:04:07 PM PDT 24 4217343833 ps
T845 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2218684915 Jul 22 06:04:02 PM PDT 24 Jul 22 06:04:04 PM PDT 24 399516215 ps
T846 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.923079800 Jul 22 06:04:15 PM PDT 24 Jul 22 06:04:19 PM PDT 24 529240859 ps
T142 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2334638986 Jul 22 06:04:03 PM PDT 24 Jul 22 06:04:05 PM PDT 24 305305137 ps
T847 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4157040875 Jul 22 06:04:02 PM PDT 24 Jul 22 06:04:06 PM PDT 24 2134706565 ps
T143 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2964099961 Jul 22 06:03:54 PM PDT 24 Jul 22 06:03:58 PM PDT 24 612579336 ps
T848 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2792986206 Jul 22 06:04:02 PM PDT 24 Jul 22 06:04:05 PM PDT 24 654753981 ps
T849 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.764638404 Jul 22 06:04:56 PM PDT 24 Jul 22 06:04:58 PM PDT 24 400966401 ps
T850 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2197548636 Jul 22 06:04:12 PM PDT 24 Jul 22 06:04:21 PM PDT 24 8425748413 ps
T210 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1200139962 Jul 22 06:04:04 PM PDT 24 Jul 22 06:04:08 PM PDT 24 4507534195 ps
T851 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3612287857 Jul 22 06:05:00 PM PDT 24 Jul 22 06:05:02 PM PDT 24 495860446 ps
T852 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3622629878 Jul 22 06:04:17 PM PDT 24 Jul 22 06:04:20 PM PDT 24 384719546 ps
T853 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2897636267 Jul 22 06:04:00 PM PDT 24 Jul 22 06:04:06 PM PDT 24 2717298634 ps
T854 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3151006136 Jul 22 06:03:55 PM PDT 24 Jul 22 06:03:58 PM PDT 24 535573981 ps
T855 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3866734002 Jul 22 06:03:50 PM PDT 24 Jul 22 06:03:55 PM PDT 24 478381197 ps
T856 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2750253677 Jul 22 06:04:37 PM PDT 24 Jul 22 06:04:39 PM PDT 24 523629386 ps
T857 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3663987932 Jul 22 06:04:06 PM PDT 24 Jul 22 06:04:14 PM PDT 24 4253080074 ps
T858 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2882913255 Jul 22 06:04:15 PM PDT 24 Jul 22 06:04:18 PM PDT 24 361880674 ps
T144 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1080926533 Jul 22 06:04:02 PM PDT 24 Jul 22 06:04:04 PM PDT 24 364364749 ps
T859 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1543344831 Jul 22 06:04:59 PM PDT 24 Jul 22 06:05:05 PM PDT 24 438509420 ps
T860 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.394598952 Jul 22 06:04:16 PM PDT 24 Jul 22 06:04:18 PM PDT 24 404288042 ps
T861 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2691802539 Jul 22 06:05:32 PM PDT 24 Jul 22 06:05:34 PM PDT 24 356280486 ps
T862 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2211588500 Jul 22 06:03:54 PM PDT 24 Jul 22 06:03:58 PM PDT 24 716014010 ps
T863 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2666206730 Jul 22 06:04:10 PM PDT 24 Jul 22 06:04:12 PM PDT 24 382545347 ps
T145 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1265419841 Jul 22 06:03:57 PM PDT 24 Jul 22 06:03:59 PM PDT 24 483689700 ps
T864 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3515919197 Jul 22 06:04:04 PM PDT 24 Jul 22 06:04:08 PM PDT 24 538843061 ps
T865 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.276172958 Jul 22 06:04:12 PM PDT 24 Jul 22 06:04:13 PM PDT 24 398728993 ps
T866 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3422075944 Jul 22 06:04:10 PM PDT 24 Jul 22 06:04:12 PM PDT 24 501022795 ps
T867 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.677321879 Jul 22 06:04:10 PM PDT 24 Jul 22 06:04:14 PM PDT 24 2439747722 ps
T868 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.320542264 Jul 22 06:05:32 PM PDT 24 Jul 22 06:05:34 PM PDT 24 304759208 ps
T869 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3865057107 Jul 22 06:04:22 PM PDT 24 Jul 22 06:04:24 PM PDT 24 386829061 ps
T870 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2620851113 Jul 22 06:04:34 PM PDT 24 Jul 22 06:04:36 PM PDT 24 308286536 ps
T871 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3674786426 Jul 22 06:04:15 PM PDT 24 Jul 22 06:04:21 PM PDT 24 509349632 ps
T872 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.94195724 Jul 22 06:03:51 PM PDT 24 Jul 22 06:03:56 PM PDT 24 4300684481 ps
T873 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.295180370 Jul 22 06:05:17 PM PDT 24 Jul 22 06:05:59 PM PDT 24 19070774011 ps
T874 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.430487872 Jul 22 06:03:59 PM PDT 24 Jul 22 06:04:04 PM PDT 24 4580120992 ps
T97 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.556237591 Jul 22 06:04:09 PM PDT 24 Jul 22 06:04:17 PM PDT 24 8223825023 ps
T875 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1772533225 Jul 22 06:04:06 PM PDT 24 Jul 22 06:04:08 PM PDT 24 511464399 ps
T876 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2752861977 Jul 22 06:04:14 PM PDT 24 Jul 22 06:04:17 PM PDT 24 501555938 ps
T877 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4120175985 Jul 22 06:04:05 PM PDT 24 Jul 22 06:04:07 PM PDT 24 466894012 ps
T878 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2310126618 Jul 22 06:04:14 PM PDT 24 Jul 22 06:04:18 PM PDT 24 427571083 ps
T879 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2321735082 Jul 22 06:03:56 PM PDT 24 Jul 22 06:03:58 PM PDT 24 2608890880 ps
T880 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1986064992 Jul 22 06:03:55 PM PDT 24 Jul 22 06:04:12 PM PDT 24 37539243102 ps
T881 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3651112203 Jul 22 06:03:53 PM PDT 24 Jul 22 06:04:48 PM PDT 24 27201795793 ps
T882 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.632758545 Jul 22 06:04:01 PM PDT 24 Jul 22 06:04:03 PM PDT 24 326415544 ps
T883 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1001083839 Jul 22 06:04:16 PM PDT 24 Jul 22 06:04:24 PM PDT 24 4198917870 ps
T884 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3295258829 Jul 22 06:04:14 PM PDT 24 Jul 22 06:04:17 PM PDT 24 298797209 ps
T885 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.865204840 Jul 22 06:04:22 PM PDT 24 Jul 22 06:04:24 PM PDT 24 298142678 ps
T886 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3519853612 Jul 22 06:03:57 PM PDT 24 Jul 22 06:04:00 PM PDT 24 626612579 ps
T887 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2214957940 Jul 22 06:03:56 PM PDT 24 Jul 22 06:03:58 PM PDT 24 1243309814 ps
T888 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1269080012 Jul 22 06:04:01 PM PDT 24 Jul 22 06:04:04 PM PDT 24 351829764 ps
T889 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1222157673 Jul 22 06:04:02 PM PDT 24 Jul 22 06:04:04 PM PDT 24 488168476 ps
T890 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1258224059 Jul 22 06:04:06 PM PDT 24 Jul 22 06:04:12 PM PDT 24 4344562972 ps
T891 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1583317787 Jul 22 06:04:04 PM PDT 24 Jul 22 06:04:06 PM PDT 24 450338028 ps
T98 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2846975109 Jul 22 06:04:01 PM PDT 24 Jul 22 06:04:11 PM PDT 24 8105462149 ps
T892 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.675473698 Jul 22 06:05:34 PM PDT 24 Jul 22 06:05:36 PM PDT 24 396613039 ps
T893 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.539742476 Jul 22 06:04:10 PM PDT 24 Jul 22 06:04:12 PM PDT 24 539298697 ps
T894 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3703011082 Jul 22 06:04:15 PM PDT 24 Jul 22 06:04:18 PM PDT 24 586954501 ps
T895 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3850460611 Jul 22 06:03:54 PM PDT 24 Jul 22 06:03:57 PM PDT 24 897470079 ps
T896 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4065131912 Jul 22 06:04:13 PM PDT 24 Jul 22 06:04:16 PM PDT 24 1352448107 ps
T897 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.982819581 Jul 22 06:07:41 PM PDT 24 Jul 22 06:07:44 PM PDT 24 433787691 ps
T898 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3012148037 Jul 22 06:04:10 PM PDT 24 Jul 22 06:04:13 PM PDT 24 522948602 ps
T899 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.894808230 Jul 22 06:03:59 PM PDT 24 Jul 22 06:04:01 PM PDT 24 899442381 ps
T900 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2956841740 Jul 22 06:04:11 PM PDT 24 Jul 22 06:04:25 PM PDT 24 4195373687 ps
T901 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3028283871 Jul 22 06:04:13 PM PDT 24 Jul 22 06:04:34 PM PDT 24 8727425972 ps
T902 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.982508173 Jul 22 06:04:08 PM PDT 24 Jul 22 06:04:11 PM PDT 24 515872782 ps
T903 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4213958348 Jul 22 06:04:15 PM PDT 24 Jul 22 06:04:19 PM PDT 24 479105736 ps
T904 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4023685416 Jul 22 06:04:14 PM PDT 24 Jul 22 06:04:17 PM PDT 24 433807443 ps
T905 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1510984220 Jul 22 06:04:12 PM PDT 24 Jul 22 06:04:14 PM PDT 24 454474582 ps
T906 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2499984296 Jul 22 06:04:38 PM PDT 24 Jul 22 06:04:39 PM PDT 24 495044238 ps
T907 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2943432393 Jul 22 06:04:05 PM PDT 24 Jul 22 06:04:07 PM PDT 24 395173951 ps
T908 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2110338092 Jul 22 06:04:10 PM PDT 24 Jul 22 06:04:19 PM PDT 24 4939715770 ps
T909 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1765179977 Jul 22 06:04:16 PM PDT 24 Jul 22 06:04:19 PM PDT 24 347599326 ps
T910 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2578168788 Jul 22 06:04:12 PM PDT 24 Jul 22 06:04:14 PM PDT 24 404482377 ps
T911 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2835448642 Jul 22 06:04:01 PM PDT 24 Jul 22 06:04:04 PM PDT 24 5374678281 ps
T912 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1453057355 Jul 22 06:04:04 PM PDT 24 Jul 22 06:04:07 PM PDT 24 1075110303 ps
T913 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3292419692 Jul 22 06:04:05 PM PDT 24 Jul 22 06:04:07 PM PDT 24 353082470 ps
T914 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1087219889 Jul 22 06:04:14 PM PDT 24 Jul 22 06:04:17 PM PDT 24 518887711 ps
T915 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2798700618 Jul 22 06:04:10 PM PDT 24 Jul 22 06:04:12 PM PDT 24 1241395099 ps
T916 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.167100692 Jul 22 06:04:28 PM PDT 24 Jul 22 06:04:30 PM PDT 24 376797257 ps
T917 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2214354572 Jul 22 06:03:59 PM PDT 24 Jul 22 06:04:01 PM PDT 24 350441792 ps
T918 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.96102260 Jul 22 06:04:03 PM PDT 24 Jul 22 06:04:06 PM PDT 24 578282018 ps
T919 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.412442940 Jul 22 06:04:03 PM PDT 24 Jul 22 06:04:05 PM PDT 24 478403887 ps
T920 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4181383253 Jul 22 06:04:01 PM PDT 24 Jul 22 06:04:03 PM PDT 24 1271184343 ps

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.529288759
Short name T7
Test name
Test status
Simulation time 546122084361 ps
CPU time 637.69 seconds
Started Jul 22 06:04:22 PM PDT 24
Finished Jul 22 06:15:00 PM PDT 24
Peak memory 201216 kb
Host smart-4f373809-1a75-4813-8570-67079c5d7de3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529288759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.529288759
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2282748148
Short name T47
Test name
Test status
Simulation time 100732133082 ps
CPU time 380.87 seconds
Started Jul 22 06:04:39 PM PDT 24
Finished Jul 22 06:11:01 PM PDT 24
Peak memory 217420 kb
Host smart-893b7207-5ccc-47c7-a338-b8d7e4cc91b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282748148 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2282748148
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.110120413
Short name T1
Test name
Test status
Simulation time 332128918177 ps
CPU time 389.56 seconds
Started Jul 22 06:05:55 PM PDT 24
Finished Jul 22 06:12:25 PM PDT 24
Peak memory 201224 kb
Host smart-fd47713b-fef0-4256-ba6a-7b6da52739a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110120413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.110120413
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3244959721
Short name T172
Test name
Test status
Simulation time 515345582745 ps
CPU time 225.11 seconds
Started Jul 22 06:06:35 PM PDT 24
Finished Jul 22 06:10:20 PM PDT 24
Peak memory 201176 kb
Host smart-fa662ebc-c533-452b-9e43-51e93f9eee67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244959721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3244959721
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.194494605
Short name T49
Test name
Test status
Simulation time 332957254678 ps
CPU time 708.14 seconds
Started Jul 22 06:04:48 PM PDT 24
Finished Jul 22 06:16:37 PM PDT 24
Peak memory 211008 kb
Host smart-87a59201-8e09-4379-b6ce-b8ec357d8db3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194494605 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.194494605
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3416509811
Short name T16
Test name
Test status
Simulation time 45609337693 ps
CPU time 86.98 seconds
Started Jul 22 06:07:13 PM PDT 24
Finished Jul 22 06:08:40 PM PDT 24
Peak memory 209968 kb
Host smart-c2a02965-b228-473c-a481-9ffe5f788baf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416509811 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3416509811
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1961016739
Short name T168
Test name
Test status
Simulation time 503199345008 ps
CPU time 526.74 seconds
Started Jul 22 06:08:47 PM PDT 24
Finished Jul 22 06:17:35 PM PDT 24
Peak memory 201228 kb
Host smart-84ef7b71-2af5-4cc0-a14a-e8fa1aab0c8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961016739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1961016739
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3504501800
Short name T120
Test name
Test status
Simulation time 542555638171 ps
CPU time 1307.08 seconds
Started Jul 22 06:06:14 PM PDT 24
Finished Jul 22 06:28:01 PM PDT 24
Peak memory 201288 kb
Host smart-89cf7d77-7c1f-40c5-beb6-bf5cbf4cc145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504501800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3504501800
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2822496549
Short name T62
Test name
Test status
Simulation time 490872612667 ps
CPU time 134.81 seconds
Started Jul 22 06:04:49 PM PDT 24
Finished Jul 22 06:07:05 PM PDT 24
Peak memory 201504 kb
Host smart-736b5528-032c-40c0-9c0d-f705dd16f906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822496549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2822496549
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3308571488
Short name T230
Test name
Test status
Simulation time 526849503121 ps
CPU time 1158.88 seconds
Started Jul 22 06:05:42 PM PDT 24
Finished Jul 22 06:25:02 PM PDT 24
Peak memory 201184 kb
Host smart-29638f3d-6357-4a97-8029-4dd9b0dc99dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308571488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3308571488
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3823396825
Short name T90
Test name
Test status
Simulation time 556013512 ps
CPU time 2.73 seconds
Started Jul 22 06:04:03 PM PDT 24
Finished Jul 22 06:04:06 PM PDT 24
Peak memory 218108 kb
Host smart-08194f2a-687c-437d-88b7-7b4086c0ad01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823396825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3823396825
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3641939950
Short name T235
Test name
Test status
Simulation time 509265637632 ps
CPU time 585.56 seconds
Started Jul 22 06:06:04 PM PDT 24
Finished Jul 22 06:15:50 PM PDT 24
Peak memory 201228 kb
Host smart-829cea18-11d1-4fbf-af79-0f5ccf20ae4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641939950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3641939950
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1071579462
Short name T77
Test name
Test status
Simulation time 380033470204 ps
CPU time 447.62 seconds
Started Jul 22 06:06:12 PM PDT 24
Finished Jul 22 06:13:40 PM PDT 24
Peak memory 201188 kb
Host smart-79a19826-7b10-46b9-a7bb-83ebe489f298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071579462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1071579462
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.1391293757
Short name T227
Test name
Test status
Simulation time 499609779712 ps
CPU time 113.22 seconds
Started Jul 22 06:05:55 PM PDT 24
Finished Jul 22 06:07:49 PM PDT 24
Peak memory 201316 kb
Host smart-fcbf8b84-4713-4b86-8d2c-8723bd0b3916
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391293757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.1391293757
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.910447707
Short name T66
Test name
Test status
Simulation time 601017929986 ps
CPU time 161.82 seconds
Started Jul 22 06:04:54 PM PDT 24
Finished Jul 22 06:07:37 PM PDT 24
Peak memory 201180 kb
Host smart-242dfeca-6db6-4ed4-8b0d-46d4e7fccd0b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910447707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.910447707
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3319030370
Short name T26
Test name
Test status
Simulation time 365867015 ps
CPU time 1.36 seconds
Started Jul 22 06:07:42 PM PDT 24
Finished Jul 22 06:07:45 PM PDT 24
Peak memory 201036 kb
Host smart-81bb8b72-d826-4061-8a2f-97b7e522e3f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319030370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3319030370
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1039582849
Short name T153
Test name
Test status
Simulation time 515489306467 ps
CPU time 895.46 seconds
Started Jul 22 06:04:31 PM PDT 24
Finished Jul 22 06:19:27 PM PDT 24
Peak memory 201204 kb
Host smart-e686d98d-8170-4b9d-8754-112eb1914445
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039582849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1039582849
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1335280866
Short name T135
Test name
Test status
Simulation time 52210501454 ps
CPU time 28.83 seconds
Started Jul 22 06:03:50 PM PDT 24
Finished Jul 22 06:04:20 PM PDT 24
Peak memory 201708 kb
Host smart-550e3823-2d98-4aa8-8172-0da8091b191d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335280866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1335280866
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3790793210
Short name T166
Test name
Test status
Simulation time 573085528891 ps
CPU time 163.95 seconds
Started Jul 22 06:05:41 PM PDT 24
Finished Jul 22 06:08:26 PM PDT 24
Peak memory 201240 kb
Host smart-a9c246ec-3257-4c01-af98-25b85c5f3bb8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790793210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3790793210
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.392086756
Short name T83
Test name
Test status
Simulation time 4333817227 ps
CPU time 2.87 seconds
Started Jul 22 06:04:39 PM PDT 24
Finished Jul 22 06:04:43 PM PDT 24
Peak memory 216956 kb
Host smart-7c0df1d7-4522-4b8a-89f4-8d46c07951ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392086756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.392086756
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2307821367
Short name T114
Test name
Test status
Simulation time 493498974721 ps
CPU time 1143.01 seconds
Started Jul 22 06:08:28 PM PDT 24
Finished Jul 22 06:27:32 PM PDT 24
Peak memory 201204 kb
Host smart-e990310a-5ed1-4ab5-bacd-5a15b197b71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307821367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2307821367
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.375902750
Short name T65
Test name
Test status
Simulation time 321897823525 ps
CPU time 792.05 seconds
Started Jul 22 06:05:24 PM PDT 24
Finished Jul 22 06:18:36 PM PDT 24
Peak memory 201212 kb
Host smart-1bd25bb9-0698-4e6b-863d-a1cfe0b80dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375902750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.375902750
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.1959638185
Short name T106
Test name
Test status
Simulation time 502281618817 ps
CPU time 277.74 seconds
Started Jul 22 06:05:18 PM PDT 24
Finished Jul 22 06:09:57 PM PDT 24
Peak memory 201216 kb
Host smart-6b0fe69d-2b4d-4900-9a98-f72e27b52327
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959638185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.1959638185
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.4253322021
Short name T180
Test name
Test status
Simulation time 566672347741 ps
CPU time 1344.02 seconds
Started Jul 22 06:05:41 PM PDT 24
Finished Jul 22 06:28:07 PM PDT 24
Peak memory 201256 kb
Host smart-ec1393ba-1ad3-40ba-8625-5eff2a5fcdf2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253322021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.4253322021
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3451087547
Short name T35
Test name
Test status
Simulation time 487678915587 ps
CPU time 1157.5 seconds
Started Jul 22 06:04:50 PM PDT 24
Finished Jul 22 06:24:09 PM PDT 24
Peak memory 201300 kb
Host smart-6cc8ba29-623a-4d19-af7c-f543e85e3438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451087547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3451087547
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3644390760
Short name T289
Test name
Test status
Simulation time 355736153728 ps
CPU time 186.73 seconds
Started Jul 22 06:05:20 PM PDT 24
Finished Jul 22 06:08:28 PM PDT 24
Peak memory 201180 kb
Host smart-750662c2-dbde-4f2d-b9eb-d90be6025043
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644390760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3644390760
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.4287063765
Short name T240
Test name
Test status
Simulation time 521758295097 ps
CPU time 1276.28 seconds
Started Jul 22 06:06:50 PM PDT 24
Finished Jul 22 06:28:07 PM PDT 24
Peak memory 201448 kb
Host smart-2660de30-dd53-486c-86a9-09a084199d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287063765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.4287063765
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2860494775
Short name T190
Test name
Test status
Simulation time 360124974720 ps
CPU time 132.44 seconds
Started Jul 22 06:04:43 PM PDT 24
Finished Jul 22 06:06:56 PM PDT 24
Peak memory 201224 kb
Host smart-1e2a14a9-06ab-4652-b3dd-d14f6b954195
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860494775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2860494775
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3080096941
Short name T199
Test name
Test status
Simulation time 492270939395 ps
CPU time 92.04 seconds
Started Jul 22 06:05:29 PM PDT 24
Finished Jul 22 06:07:02 PM PDT 24
Peak memory 201196 kb
Host smart-e4c8a15d-b625-4367-86d0-06e687cbff89
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080096941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3080096941
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2006026198
Short name T117
Test name
Test status
Simulation time 496894833580 ps
CPU time 1185.64 seconds
Started Jul 22 06:07:24 PM PDT 24
Finished Jul 22 06:27:11 PM PDT 24
Peak memory 201212 kb
Host smart-746520bf-9da6-478c-b5ad-b1ca18e8e03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006026198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2006026198
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.376222107
Short name T231
Test name
Test status
Simulation time 180160447414 ps
CPU time 218.78 seconds
Started Jul 22 06:06:05 PM PDT 24
Finished Jul 22 06:09:44 PM PDT 24
Peak memory 201224 kb
Host smart-a3c95988-054e-4704-a3d1-67f4ae92bc60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376222107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.376222107
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3200037597
Short name T207
Test name
Test status
Simulation time 8236599415 ps
CPU time 7.05 seconds
Started Jul 22 06:04:13 PM PDT 24
Finished Jul 22 06:04:22 PM PDT 24
Peak memory 201784 kb
Host smart-8564adf6-2f05-4b4b-9edb-b3f9319e1272
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200037597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3200037597
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1414606298
Short name T34
Test name
Test status
Simulation time 505565149674 ps
CPU time 318.28 seconds
Started Jul 22 06:07:26 PM PDT 24
Finished Jul 22 06:12:44 PM PDT 24
Peak memory 201196 kb
Host smart-f8cba4fd-fcdf-41de-97cb-301d43fc0dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414606298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1414606298
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.4052251124
Short name T248
Test name
Test status
Simulation time 366248805491 ps
CPU time 844.54 seconds
Started Jul 22 06:08:52 PM PDT 24
Finished Jul 22 06:22:57 PM PDT 24
Peak memory 201236 kb
Host smart-2f764e9e-aacd-435b-856c-7e5be007bfef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052251124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.4052251124
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.803406527
Short name T138
Test name
Test status
Simulation time 511364973 ps
CPU time 1.06 seconds
Started Jul 22 06:04:13 PM PDT 24
Finished Jul 22 06:04:16 PM PDT 24
Peak memory 201508 kb
Host smart-7d0a85b0-f6d7-4eed-b7c2-cba54709345f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803406527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.803406527
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2750926720
Short name T291
Test name
Test status
Simulation time 348095464225 ps
CPU time 531.49 seconds
Started Jul 22 06:05:44 PM PDT 24
Finished Jul 22 06:14:36 PM PDT 24
Peak memory 201316 kb
Host smart-2d507c7c-35a9-430f-9d9f-6864d819a46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750926720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2750926720
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1115770130
Short name T17
Test name
Test status
Simulation time 359849795125 ps
CPU time 297.18 seconds
Started Jul 22 06:04:52 PM PDT 24
Finished Jul 22 06:09:51 PM PDT 24
Peak memory 209552 kb
Host smart-81e0a249-d0f5-4876-bd07-30b88de88981
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115770130 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1115770130
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.836566344
Short name T318
Test name
Test status
Simulation time 582179270786 ps
CPU time 320.21 seconds
Started Jul 22 06:04:48 PM PDT 24
Finished Jul 22 06:10:09 PM PDT 24
Peak memory 201208 kb
Host smart-96d9cc5a-7424-489b-b223-f33ea80c2c76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836566344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.836566344
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1117667238
Short name T242
Test name
Test status
Simulation time 493437890460 ps
CPU time 1166.39 seconds
Started Jul 22 06:05:20 PM PDT 24
Finished Jul 22 06:24:47 PM PDT 24
Peak memory 201176 kb
Host smart-13d81b11-cc53-45cf-9d77-6596c8506767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117667238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1117667238
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.502811860
Short name T223
Test name
Test status
Simulation time 340889187187 ps
CPU time 84.73 seconds
Started Jul 22 06:05:32 PM PDT 24
Finished Jul 22 06:06:58 PM PDT 24
Peak memory 201224 kb
Host smart-3fe6515b-a133-4d84-a5ce-e071952c9b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502811860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.502811860
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3509786978
Short name T264
Test name
Test status
Simulation time 171587840637 ps
CPU time 362.84 seconds
Started Jul 22 06:06:24 PM PDT 24
Finished Jul 22 06:12:27 PM PDT 24
Peak memory 201204 kb
Host smart-b98dd340-3147-4439-ab12-693f7c1795c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509786978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3509786978
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3658418321
Short name T270
Test name
Test status
Simulation time 925019940323 ps
CPU time 473.08 seconds
Started Jul 22 06:05:30 PM PDT 24
Finished Jul 22 06:13:23 PM PDT 24
Peak memory 209964 kb
Host smart-cc718105-277d-4930-88b9-dcb0230822e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658418321 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3658418321
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3153844672
Short name T304
Test name
Test status
Simulation time 506012678368 ps
CPU time 209.99 seconds
Started Jul 22 06:08:12 PM PDT 24
Finished Jul 22 06:11:42 PM PDT 24
Peak memory 201116 kb
Host smart-a3e0afb6-f0fa-4f3c-9a68-9feee0e8041d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153844672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3153844672
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2274970764
Short name T261
Test name
Test status
Simulation time 625470580062 ps
CPU time 1704.82 seconds
Started Jul 22 06:08:13 PM PDT 24
Finished Jul 22 06:36:39 PM PDT 24
Peak memory 201632 kb
Host smart-44d6146d-4ce4-4fe9-bdac-85e35a8a402d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274970764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2274970764
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.4209001522
Short name T36
Test name
Test status
Simulation time 552525639643 ps
CPU time 1231.84 seconds
Started Jul 22 06:04:47 PM PDT 24
Finished Jul 22 06:25:19 PM PDT 24
Peak memory 201168 kb
Host smart-b258164d-b1e0-4a83-a813-669daab63b87
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209001522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.4209001522
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3580182369
Short name T159
Test name
Test status
Simulation time 597941115658 ps
CPU time 694.74 seconds
Started Jul 22 06:05:37 PM PDT 24
Finished Jul 22 06:17:12 PM PDT 24
Peak memory 201232 kb
Host smart-85eb70e1-65e3-4ce3-9d6e-0dfa109a11ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580182369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3580182369
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2157055742
Short name T225
Test name
Test status
Simulation time 324197810405 ps
CPU time 723.17 seconds
Started Jul 22 06:07:13 PM PDT 24
Finished Jul 22 06:19:17 PM PDT 24
Peak memory 201208 kb
Host smart-4ea565ad-90c3-4a3f-84c6-d801dae12c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157055742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2157055742
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2987535422
Short name T214
Test name
Test status
Simulation time 68899974202 ps
CPU time 249.6 seconds
Started Jul 22 06:04:48 PM PDT 24
Finished Jul 22 06:08:59 PM PDT 24
Peak memory 201668 kb
Host smart-4b3fb331-ab5d-4e70-bde2-1e7800ceda7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987535422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2987535422
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3553068718
Short name T283
Test name
Test status
Simulation time 349356238232 ps
CPU time 416.45 seconds
Started Jul 22 06:05:07 PM PDT 24
Finished Jul 22 06:12:04 PM PDT 24
Peak memory 201264 kb
Host smart-dac38678-71f3-46b0-bb07-07143452a22d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553068718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3553068718
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.4244920104
Short name T278
Test name
Test status
Simulation time 182912644637 ps
CPU time 116.68 seconds
Started Jul 22 06:07:04 PM PDT 24
Finished Jul 22 06:09:01 PM PDT 24
Peak memory 201284 kb
Host smart-4b32b9d9-cdad-41ef-b69b-51b4dba838d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244920104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.4244920104
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.922437916
Short name T319
Test name
Test status
Simulation time 374528434184 ps
CPU time 212.04 seconds
Started Jul 22 06:04:50 PM PDT 24
Finished Jul 22 06:08:24 PM PDT 24
Peak memory 201236 kb
Host smart-472037f6-58a4-460a-a6e9-f939f9ac381b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922437916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.922437916
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2839297312
Short name T281
Test name
Test status
Simulation time 492734742762 ps
CPU time 318.38 seconds
Started Jul 22 06:04:22 PM PDT 24
Finished Jul 22 06:09:41 PM PDT 24
Peak memory 201224 kb
Host smart-8a670a4a-a746-44f1-87c8-d07c4ad40f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839297312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2839297312
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1196887580
Short name T189
Test name
Test status
Simulation time 489698609602 ps
CPU time 304.78 seconds
Started Jul 22 06:04:20 PM PDT 24
Finished Jul 22 06:09:26 PM PDT 24
Peak memory 201204 kb
Host smart-51bcf00a-c8e5-4a7c-932c-f3ebfc471034
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196887580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1196887580
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.152925016
Short name T197
Test name
Test status
Simulation time 521343121147 ps
CPU time 324.96 seconds
Started Jul 22 06:04:52 PM PDT 24
Finished Jul 22 06:10:18 PM PDT 24
Peak memory 201216 kb
Host smart-ce959daf-6073-460a-91ff-fcfa9cb0701a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152925016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.152925016
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3672716060
Short name T303
Test name
Test status
Simulation time 484796644229 ps
CPU time 592.92 seconds
Started Jul 22 06:07:22 PM PDT 24
Finished Jul 22 06:17:16 PM PDT 24
Peak memory 201196 kb
Host smart-66c736f8-7f5f-4832-978f-624ce825e08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672716060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3672716060
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3048046954
Short name T211
Test name
Test status
Simulation time 124126170839 ps
CPU time 412.38 seconds
Started Jul 22 06:08:32 PM PDT 24
Finished Jul 22 06:15:25 PM PDT 24
Peak memory 201684 kb
Host smart-b5dad502-7fa9-406e-a168-c44fcf12b5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048046954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3048046954
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3402407005
Short name T295
Test name
Test status
Simulation time 329285310872 ps
CPU time 206.21 seconds
Started Jul 22 06:04:49 PM PDT 24
Finished Jul 22 06:08:16 PM PDT 24
Peak memory 201204 kb
Host smart-a837bb66-47a6-41a0-98ee-e3bf72e7aba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402407005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3402407005
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.559129364
Short name T186
Test name
Test status
Simulation time 510419345006 ps
CPU time 304.96 seconds
Started Jul 22 06:06:09 PM PDT 24
Finished Jul 22 06:11:17 PM PDT 24
Peak memory 201124 kb
Host smart-51912aa8-ac7e-4e49-b37d-9f1c1a0afeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559129364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.559129364
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.636201536
Short name T53
Test name
Test status
Simulation time 208921865576 ps
CPU time 473.05 seconds
Started Jul 22 06:04:27 PM PDT 24
Finished Jul 22 06:12:21 PM PDT 24
Peak memory 210036 kb
Host smart-34098317-7606-4e6c-b34e-2dab877919b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636201536 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.636201536
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1950734944
Short name T320
Test name
Test status
Simulation time 492149120172 ps
CPU time 291.98 seconds
Started Jul 22 06:05:32 PM PDT 24
Finished Jul 22 06:10:25 PM PDT 24
Peak memory 201216 kb
Host smart-2e52d1dd-10cd-4316-916e-3b20eea52579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950734944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1950734944
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2680759708
Short name T274
Test name
Test status
Simulation time 721257193881 ps
CPU time 1346.22 seconds
Started Jul 22 06:05:37 PM PDT 24
Finished Jul 22 06:28:03 PM PDT 24
Peak memory 201220 kb
Host smart-f5a1da6c-7697-44ae-b209-9269958cc99d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680759708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2680759708
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3298623594
Short name T252
Test name
Test status
Simulation time 483093381039 ps
CPU time 803.81 seconds
Started Jul 22 06:05:42 PM PDT 24
Finished Jul 22 06:19:07 PM PDT 24
Peak memory 201272 kb
Host smart-5f60149a-b14a-4c37-a5c5-57e5853826e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298623594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3298623594
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1858252554
Short name T205
Test name
Test status
Simulation time 165303986634 ps
CPU time 87.84 seconds
Started Jul 22 06:08:12 PM PDT 24
Finished Jul 22 06:09:40 PM PDT 24
Peak memory 201208 kb
Host smart-d3b44b05-5ec3-402f-b925-f02965df2f24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858252554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1858252554
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1148279349
Short name T254
Test name
Test status
Simulation time 622971150432 ps
CPU time 1410.58 seconds
Started Jul 22 06:04:28 PM PDT 24
Finished Jul 22 06:27:59 PM PDT 24
Peak memory 201196 kb
Host smart-511d081b-4bea-4a07-b424-3472f6a25794
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148279349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1148279349
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.276863700
Short name T257
Test name
Test status
Simulation time 496319631349 ps
CPU time 1056.78 seconds
Started Jul 22 06:08:00 PM PDT 24
Finished Jul 22 06:25:37 PM PDT 24
Peak memory 201500 kb
Host smart-b240ba70-ca39-4783-b343-175f9ab0f170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276863700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.276863700
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.994757056
Short name T127
Test name
Test status
Simulation time 347361472427 ps
CPU time 140.72 seconds
Started Jul 22 06:04:49 PM PDT 24
Finished Jul 22 06:07:11 PM PDT 24
Peak memory 201220 kb
Host smart-9e7e5d51-b789-4e01-8525-7d8fa5d63ade
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994757056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.994757056
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2846975109
Short name T98
Test name
Test status
Simulation time 8105462149 ps
CPU time 9.04 seconds
Started Jul 22 06:04:01 PM PDT 24
Finished Jul 22 06:04:11 PM PDT 24
Peak memory 201664 kb
Host smart-bc1afb5e-fdaa-4581-a596-255936e0db0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846975109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2846975109
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1111594280
Short name T253
Test name
Test status
Simulation time 507203699690 ps
CPU time 321.66 seconds
Started Jul 22 06:04:56 PM PDT 24
Finished Jul 22 06:10:18 PM PDT 24
Peak memory 201280 kb
Host smart-54b2717c-f680-44a7-a5fe-0121cf915beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111594280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1111594280
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3538658047
Short name T308
Test name
Test status
Simulation time 593374245913 ps
CPU time 650.96 seconds
Started Jul 22 06:04:48 PM PDT 24
Finished Jul 22 06:15:40 PM PDT 24
Peak memory 201208 kb
Host smart-dceed672-9c36-44d7-a238-061bac8ead97
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538658047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3538658047
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3630167280
Short name T324
Test name
Test status
Simulation time 49915576954 ps
CPU time 100.99 seconds
Started Jul 22 06:04:56 PM PDT 24
Finished Jul 22 06:06:37 PM PDT 24
Peak memory 215632 kb
Host smart-1dbb3f6a-5a51-49b3-b296-9e756191741f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630167280 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3630167280
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2681354821
Short name T325
Test name
Test status
Simulation time 557238198057 ps
CPU time 1311.79 seconds
Started Jul 22 06:05:12 PM PDT 24
Finished Jul 22 06:27:04 PM PDT 24
Peak memory 201184 kb
Host smart-1c59d143-27da-4014-99b9-9a9dd7deacdc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681354821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2681354821
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3399272285
Short name T344
Test name
Test status
Simulation time 164163467684 ps
CPU time 370.22 seconds
Started Jul 22 06:07:06 PM PDT 24
Finished Jul 22 06:13:17 PM PDT 24
Peak memory 201200 kb
Host smart-9d5c6d77-a884-49eb-91d5-2e7649c39b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399272285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3399272285
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3517676217
Short name T277
Test name
Test status
Simulation time 500210051258 ps
CPU time 1208.81 seconds
Started Jul 22 06:07:40 PM PDT 24
Finished Jul 22 06:27:49 PM PDT 24
Peak memory 201276 kb
Host smart-562ca574-87c5-4451-a89d-fc2d4eccc2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517676217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3517676217
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1142325804
Short name T269
Test name
Test status
Simulation time 334884796028 ps
CPU time 763.92 seconds
Started Jul 22 06:06:54 PM PDT 24
Finished Jul 22 06:19:38 PM PDT 24
Peak memory 201216 kb
Host smart-aeb0f992-17d7-424f-98b8-c94282f392a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142325804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1142325804
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.927952539
Short name T213
Test name
Test status
Simulation time 109908369823 ps
CPU time 472.07 seconds
Started Jul 22 06:08:18 PM PDT 24
Finished Jul 22 06:16:10 PM PDT 24
Peak memory 201720 kb
Host smart-03e45af0-25b1-4815-a028-ea03069ea195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927952539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.927952539
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.30925146
Short name T271
Test name
Test status
Simulation time 209312461265 ps
CPU time 506.2 seconds
Started Jul 22 06:08:09 PM PDT 24
Finished Jul 22 06:16:36 PM PDT 24
Peak memory 201244 kb
Host smart-22015751-caca-4de6-bd94-58dcdd782c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30925146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.30925146
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2211588500
Short name T862
Test name
Test status
Simulation time 716014010 ps
CPU time 2.45 seconds
Started Jul 22 06:03:54 PM PDT 24
Finished Jul 22 06:03:58 PM PDT 24
Peak memory 210960 kb
Host smart-2d278866-a477-4df6-9b95-ab945f22658a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211588500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2211588500
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3301252788
Short name T250
Test name
Test status
Simulation time 497548754507 ps
CPU time 278.45 seconds
Started Jul 22 06:04:52 PM PDT 24
Finished Jul 22 06:09:31 PM PDT 24
Peak memory 201188 kb
Host smart-d1b34337-a117-465c-95ea-929db89ec016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301252788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3301252788
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3863453425
Short name T215
Test name
Test status
Simulation time 134843502014 ps
CPU time 556.51 seconds
Started Jul 22 06:04:49 PM PDT 24
Finished Jul 22 06:14:07 PM PDT 24
Peak memory 201640 kb
Host smart-a803d91e-f98d-4be0-a530-a2c323420fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863453425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3863453425
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.4108764777
Short name T86
Test name
Test status
Simulation time 405516395496 ps
CPU time 107.12 seconds
Started Jul 22 06:04:57 PM PDT 24
Finished Jul 22 06:06:45 PM PDT 24
Peak memory 209956 kb
Host smart-deacc8cc-f04d-4d2c-bece-3b5efd12c8e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108764777 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.4108764777
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2852616851
Short name T193
Test name
Test status
Simulation time 336143434793 ps
CPU time 201.46 seconds
Started Jul 22 06:04:52 PM PDT 24
Finished Jul 22 06:08:14 PM PDT 24
Peak memory 201212 kb
Host smart-9064316f-1bcb-42c1-bb8d-b48938090e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852616851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2852616851
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2638218507
Short name T700
Test name
Test status
Simulation time 469736358306 ps
CPU time 468.92 seconds
Started Jul 22 06:04:52 PM PDT 24
Finished Jul 22 06:12:42 PM PDT 24
Peak memory 209856 kb
Host smart-31904a0f-e1eb-4245-9a11-81d7bcbd8973
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638218507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2638218507
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1295818601
Short name T177
Test name
Test status
Simulation time 385294024001 ps
CPU time 416.24 seconds
Started Jul 22 06:04:57 PM PDT 24
Finished Jul 22 06:11:54 PM PDT 24
Peak memory 201208 kb
Host smart-d3469555-17b6-44eb-9e47-9e16f28b786a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295818601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1295818601
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1426606325
Short name T275
Test name
Test status
Simulation time 176196401712 ps
CPU time 205.89 seconds
Started Jul 22 06:05:01 PM PDT 24
Finished Jul 22 06:08:28 PM PDT 24
Peak memory 201284 kb
Host smart-4620dfa5-376b-45fb-a341-b15cff319c56
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426606325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1426606325
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1744070884
Short name T288
Test name
Test status
Simulation time 357929071861 ps
CPU time 122.14 seconds
Started Jul 22 06:05:08 PM PDT 24
Finished Jul 22 06:07:11 PM PDT 24
Peak memory 201236 kb
Host smart-a38a738b-847c-4bdd-be41-4d6ca9438ae0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744070884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1744070884
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.113363104
Short name T305
Test name
Test status
Simulation time 539569145751 ps
CPU time 255.68 seconds
Started Jul 22 06:07:06 PM PDT 24
Finished Jul 22 06:11:23 PM PDT 24
Peak memory 201220 kb
Host smart-8e1414e0-649e-4bd0-9ba6-29a4484cad60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113363104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.113363104
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1308089827
Short name T218
Test name
Test status
Simulation time 120577953877 ps
CPU time 525.54 seconds
Started Jul 22 06:05:24 PM PDT 24
Finished Jul 22 06:14:10 PM PDT 24
Peak memory 201648 kb
Host smart-51711ba7-eafe-4598-8af5-bd35c28820f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308089827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1308089827
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.855316493
Short name T212
Test name
Test status
Simulation time 323598964184 ps
CPU time 1281.26 seconds
Started Jul 22 06:06:32 PM PDT 24
Finished Jul 22 06:27:53 PM PDT 24
Peak memory 217956 kb
Host smart-6ba35022-99ba-4aac-be98-79b016db1577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855316493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
855316493
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.241559637
Short name T226
Test name
Test status
Simulation time 328082390873 ps
CPU time 792.11 seconds
Started Jul 22 06:07:32 PM PDT 24
Finished Jul 22 06:20:44 PM PDT 24
Peak memory 201208 kb
Host smart-fb005dde-b1ba-4c85-b459-9abc6e46fe68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241559637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.241559637
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.811039238
Short name T234
Test name
Test status
Simulation time 519428004875 ps
CPU time 1172.78 seconds
Started Jul 22 06:06:43 PM PDT 24
Finished Jul 22 06:26:16 PM PDT 24
Peak memory 201232 kb
Host smart-adb50188-f9c5-4142-8a58-9ce66c7f2ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811039238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.811039238
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.709374978
Short name T329
Test name
Test status
Simulation time 163545636212 ps
CPU time 184.52 seconds
Started Jul 22 06:07:22 PM PDT 24
Finished Jul 22 06:10:27 PM PDT 24
Peak memory 201272 kb
Host smart-135c65b2-a09f-4ec6-8442-90734b4e2a37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709374978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.709374978
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3545043888
Short name T347
Test name
Test status
Simulation time 327286038683 ps
CPU time 786.69 seconds
Started Jul 22 06:07:39 PM PDT 24
Finished Jul 22 06:20:47 PM PDT 24
Peak memory 201200 kb
Host smart-89bb68c4-c152-4421-9d12-9ec29eb1986c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545043888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3545043888
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.701456956
Short name T356
Test name
Test status
Simulation time 101238977168 ps
CPU time 365.9 seconds
Started Jul 22 06:07:53 PM PDT 24
Finished Jul 22 06:13:59 PM PDT 24
Peak memory 201644 kb
Host smart-20396518-b9b3-4465-b655-f6cb2f0f8122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701456956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.701456956
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.4124487087
Short name T217
Test name
Test status
Simulation time 90064311141 ps
CPU time 375.28 seconds
Started Jul 22 06:04:32 PM PDT 24
Finished Jul 22 06:10:48 PM PDT 24
Peak memory 201548 kb
Host smart-c727fa9d-d16a-4303-bffa-9e3ff0335439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124487087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.4124487087
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1767925672
Short name T266
Test name
Test status
Simulation time 563350091591 ps
CPU time 341.66 seconds
Started Jul 22 06:04:44 PM PDT 24
Finished Jul 22 06:10:26 PM PDT 24
Peak memory 201252 kb
Host smart-cc9b84a8-676e-4891-b259-749f14934a8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767925672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1767925672
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2964099961
Short name T143
Test name
Test status
Simulation time 612579336 ps
CPU time 2.4 seconds
Started Jul 22 06:03:54 PM PDT 24
Finished Jul 22 06:03:58 PM PDT 24
Peak memory 201616 kb
Host smart-af15ab46-f45e-43ef-8dfc-54ee7f16a197
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964099961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2964099961
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3651112203
Short name T881
Test name
Test status
Simulation time 27201795793 ps
CPU time 53.69 seconds
Started Jul 22 06:03:53 PM PDT 24
Finished Jul 22 06:04:48 PM PDT 24
Peak memory 201716 kb
Host smart-c7108017-27c8-41f7-b5ac-42ff7d17aabd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651112203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3651112203
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3850460611
Short name T895
Test name
Test status
Simulation time 897470079 ps
CPU time 1.73 seconds
Started Jul 22 06:03:54 PM PDT 24
Finished Jul 22 06:03:57 PM PDT 24
Peak memory 201440 kb
Host smart-e2f8cda9-2403-47ad-b353-6595739374af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850460611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3850460611
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1153722832
Short name T96
Test name
Test status
Simulation time 502416218 ps
CPU time 2 seconds
Started Jul 22 06:03:52 PM PDT 24
Finished Jul 22 06:03:55 PM PDT 24
Peak memory 201496 kb
Host smart-6dd894ba-1cef-4f8e-a8c0-b10a93b7dcb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153722832 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1153722832
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3771808425
Short name T140
Test name
Test status
Simulation time 403102237 ps
CPU time 1.25 seconds
Started Jul 22 06:03:54 PM PDT 24
Finished Jul 22 06:03:56 PM PDT 24
Peak memory 201416 kb
Host smart-47074f20-8341-4180-8388-4675909f305f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771808425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3771808425
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2889763469
Short name T803
Test name
Test status
Simulation time 400881848 ps
CPU time 0.82 seconds
Started Jul 22 06:03:51 PM PDT 24
Finished Jul 22 06:03:53 PM PDT 24
Peak memory 201420 kb
Host smart-a680bbdf-d335-4948-8ba4-11ce7e88bc19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889763469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2889763469
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2321735082
Short name T879
Test name
Test status
Simulation time 2608890880 ps
CPU time 1.91 seconds
Started Jul 22 06:03:56 PM PDT 24
Finished Jul 22 06:03:58 PM PDT 24
Peak memory 201520 kb
Host smart-19565e1f-c3e7-4f8d-8733-4473903a302f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321735082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2321735082
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2433903343
Short name T78
Test name
Test status
Simulation time 4487883372 ps
CPU time 11.06 seconds
Started Jul 22 06:03:51 PM PDT 24
Finished Jul 22 06:04:03 PM PDT 24
Peak memory 201744 kb
Host smart-8a54eecc-083c-4cf0-b850-0d45b91e3212
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433903343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2433903343
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.452451355
Short name T152
Test name
Test status
Simulation time 789597485 ps
CPU time 2.32 seconds
Started Jul 22 06:03:58 PM PDT 24
Finished Jul 22 06:04:01 PM PDT 24
Peak memory 201656 kb
Host smart-8ac412ae-7ef1-4a7b-b1b5-ccbe2fb95165
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452451355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.452451355
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2214957940
Short name T887
Test name
Test status
Simulation time 1243309814 ps
CPU time 1.39 seconds
Started Jul 22 06:03:56 PM PDT 24
Finished Jul 22 06:03:58 PM PDT 24
Peak memory 201440 kb
Host smart-69f5a974-0160-4f69-9f70-e859032eee1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214957940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2214957940
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.167100692
Short name T916
Test name
Test status
Simulation time 376797257 ps
CPU time 1.26 seconds
Started Jul 22 06:04:28 PM PDT 24
Finished Jul 22 06:04:30 PM PDT 24
Peak memory 201552 kb
Host smart-efa873de-428b-4044-b0e6-870d311b0e79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167100692 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.167100692
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1333724181
Short name T137
Test name
Test status
Simulation time 490320386 ps
CPU time 1.04 seconds
Started Jul 22 06:03:53 PM PDT 24
Finished Jul 22 06:03:55 PM PDT 24
Peak memory 201448 kb
Host smart-1e592116-152c-402f-9d9f-a9ce69c6c33e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333724181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1333724181
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1368099291
Short name T810
Test name
Test status
Simulation time 391237122 ps
CPU time 0.85 seconds
Started Jul 22 06:03:59 PM PDT 24
Finished Jul 22 06:04:01 PM PDT 24
Peak memory 201428 kb
Host smart-1d3bc6b6-89fc-443e-bc44-b08f82d4b0ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368099291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1368099291
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.194973708
Short name T146
Test name
Test status
Simulation time 4938951968 ps
CPU time 3.31 seconds
Started Jul 22 06:03:51 PM PDT 24
Finished Jul 22 06:03:56 PM PDT 24
Peak memory 201688 kb
Host smart-3c04812e-47ee-46cb-9912-461dd0bce7c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194973708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.194973708
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3866734002
Short name T855
Test name
Test status
Simulation time 478381197 ps
CPU time 3.38 seconds
Started Jul 22 06:03:50 PM PDT 24
Finished Jul 22 06:03:55 PM PDT 24
Peak memory 217636 kb
Host smart-8809a093-7510-4d5d-b7be-5a2e1ca60816
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866734002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3866734002
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.430487872
Short name T874
Test name
Test status
Simulation time 4580120992 ps
CPU time 4.31 seconds
Started Jul 22 06:03:59 PM PDT 24
Finished Jul 22 06:04:04 PM PDT 24
Peak memory 201792 kb
Host smart-c33561ff-680c-4edd-9dd2-1627fc77deee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430487872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.430487872
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1422001735
Short name T122
Test name
Test status
Simulation time 505483819 ps
CPU time 2.1 seconds
Started Jul 22 06:04:07 PM PDT 24
Finished Jul 22 06:04:09 PM PDT 24
Peak memory 201460 kb
Host smart-9057e756-7f90-4943-ab57-4c47cb797dc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422001735 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1422001735
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.941039947
Short name T139
Test name
Test status
Simulation time 495297827 ps
CPU time 1.07 seconds
Started Jul 22 06:05:34 PM PDT 24
Finished Jul 22 06:05:36 PM PDT 24
Peak memory 201360 kb
Host smart-d9bce99b-9fb0-447a-863d-abaf53d494c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941039947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.941039947
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.273226592
Short name T806
Test name
Test status
Simulation time 461832051 ps
CPU time 1.16 seconds
Started Jul 22 06:04:01 PM PDT 24
Finished Jul 22 06:04:03 PM PDT 24
Peak memory 201488 kb
Host smart-1c0409ca-5501-4aa9-ad77-bcba4f06cb51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273226592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.273226592
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2644188316
Short name T835
Test name
Test status
Simulation time 4496249270 ps
CPU time 10.91 seconds
Started Jul 22 06:05:17 PM PDT 24
Finished Jul 22 06:05:29 PM PDT 24
Peak memory 201816 kb
Host smart-e795a37c-91d0-4b4e-b3f3-602869f21441
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644188316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2644188316
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4157040875
Short name T847
Test name
Test status
Simulation time 2134706565 ps
CPU time 2.99 seconds
Started Jul 22 06:04:02 PM PDT 24
Finished Jul 22 06:04:06 PM PDT 24
Peak memory 210004 kb
Host smart-48bb1b9c-c518-42f0-be91-24bf22823a76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157040875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.4157040875
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3422075944
Short name T866
Test name
Test status
Simulation time 501022795 ps
CPU time 1.07 seconds
Started Jul 22 06:04:10 PM PDT 24
Finished Jul 22 06:04:12 PM PDT 24
Peak memory 201480 kb
Host smart-f2ef5e02-60ba-453d-8359-8e8dbcb54da5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422075944 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3422075944
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2943432393
Short name T907
Test name
Test status
Simulation time 395173951 ps
CPU time 1.63 seconds
Started Jul 22 06:04:05 PM PDT 24
Finished Jul 22 06:04:07 PM PDT 24
Peak memory 201436 kb
Host smart-1b124ff7-2ad3-41d4-96ca-c7565c3f201e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943432393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2943432393
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3292419692
Short name T913
Test name
Test status
Simulation time 353082470 ps
CPU time 1.62 seconds
Started Jul 22 06:04:05 PM PDT 24
Finished Jul 22 06:04:07 PM PDT 24
Peak memory 201436 kb
Host smart-219d60cd-9aa3-49c7-bef4-b0392851e97a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292419692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3292419692
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.4055063744
Short name T74
Test name
Test status
Simulation time 2771566353 ps
CPU time 5.82 seconds
Started Jul 22 06:04:03 PM PDT 24
Finished Jul 22 06:04:09 PM PDT 24
Peak memory 201548 kb
Host smart-5dc0ad98-aad1-4264-9c6f-f7a2ff169bbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055063744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.4055063744
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2355559517
Short name T88
Test name
Test status
Simulation time 555594866 ps
CPU time 2.76 seconds
Started Jul 22 06:04:56 PM PDT 24
Finished Jul 22 06:05:00 PM PDT 24
Peak memory 201748 kb
Host smart-4e8fe9af-0c90-4043-90c0-4737fd267bbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355559517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2355559517
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2835448642
Short name T911
Test name
Test status
Simulation time 5374678281 ps
CPU time 2.25 seconds
Started Jul 22 06:04:01 PM PDT 24
Finished Jul 22 06:04:04 PM PDT 24
Peak memory 201772 kb
Host smart-fef41192-3fe3-42ec-aef4-4a5a6acbcfd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835448642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2835448642
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.632758545
Short name T882
Test name
Test status
Simulation time 326415544 ps
CPU time 1.66 seconds
Started Jul 22 06:04:01 PM PDT 24
Finished Jul 22 06:04:03 PM PDT 24
Peak memory 201576 kb
Host smart-78ddf6f4-8a58-4ed0-bc23-2c3c6a148cc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632758545 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.632758545
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1772533225
Short name T875
Test name
Test status
Simulation time 511464399 ps
CPU time 1.09 seconds
Started Jul 22 06:04:06 PM PDT 24
Finished Jul 22 06:04:08 PM PDT 24
Peak memory 201392 kb
Host smart-a6e542be-e99f-4787-823f-029bb5122cdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772533225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1772533225
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2367980436
Short name T808
Test name
Test status
Simulation time 344147031 ps
CPU time 0.85 seconds
Started Jul 22 06:04:06 PM PDT 24
Finished Jul 22 06:04:08 PM PDT 24
Peak memory 201328 kb
Host smart-92ddbe8f-97a2-4a6a-b42f-6be8dc627baf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367980436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2367980436
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3554282843
Short name T836
Test name
Test status
Simulation time 2412418457 ps
CPU time 8.63 seconds
Started Jul 22 06:04:09 PM PDT 24
Finished Jul 22 06:04:19 PM PDT 24
Peak memory 201592 kb
Host smart-4f0e5213-ffd1-4913-b219-632fb1627947
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554282843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3554282843
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2791464923
Short name T824
Test name
Test status
Simulation time 572456913 ps
CPU time 2.96 seconds
Started Jul 22 06:04:04 PM PDT 24
Finished Jul 22 06:04:08 PM PDT 24
Peak memory 210012 kb
Host smart-7f25901b-ff53-4cfc-95b6-6bf0d968a8ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791464923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2791464923
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.556237591
Short name T97
Test name
Test status
Simulation time 8223825023 ps
CPU time 6.85 seconds
Started Jul 22 06:04:09 PM PDT 24
Finished Jul 22 06:04:17 PM PDT 24
Peak memory 201844 kb
Host smart-a6b7fdcd-f613-49cd-bfe2-6d22b20fcf4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556237591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.556237591
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2666206730
Short name T863
Test name
Test status
Simulation time 382545347 ps
CPU time 1.01 seconds
Started Jul 22 06:04:10 PM PDT 24
Finished Jul 22 06:04:12 PM PDT 24
Peak memory 201588 kb
Host smart-4bdc1de9-e618-46d6-afa8-a9f611d645c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666206730 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2666206730
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2334638986
Short name T142
Test name
Test status
Simulation time 305305137 ps
CPU time 1.37 seconds
Started Jul 22 06:04:03 PM PDT 24
Finished Jul 22 06:04:05 PM PDT 24
Peak memory 201424 kb
Host smart-aaaaec20-be24-478b-93f8-4155fee5a051
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334638986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2334638986
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.831918179
Short name T827
Test name
Test status
Simulation time 542384045 ps
CPU time 0.92 seconds
Started Jul 22 06:04:09 PM PDT 24
Finished Jul 22 06:04:11 PM PDT 24
Peak memory 201460 kb
Host smart-b402a265-8d64-4f82-a31b-f1c19ccb5f1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831918179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.831918179
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2110338092
Short name T908
Test name
Test status
Simulation time 4939715770 ps
CPU time 8.83 seconds
Started Jul 22 06:04:10 PM PDT 24
Finished Jul 22 06:04:19 PM PDT 24
Peak memory 201792 kb
Host smart-2919b280-c3f6-4dc4-bfa5-8dcdcb019b36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110338092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2110338092
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1747266415
Short name T93
Test name
Test status
Simulation time 548598870 ps
CPU time 2.88 seconds
Started Jul 22 06:05:17 PM PDT 24
Finished Jul 22 06:05:21 PM PDT 24
Peak memory 201740 kb
Host smart-d4bc0a13-61f7-4243-9646-f51669d86aae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747266415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1747266415
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1154849030
Short name T80
Test name
Test status
Simulation time 4154581492 ps
CPU time 11.48 seconds
Started Jul 22 06:04:06 PM PDT 24
Finished Jul 22 06:04:18 PM PDT 24
Peak memory 201836 kb
Host smart-2d7a7fbe-65b0-4159-9807-fcb5e5372626
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154849030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1154849030
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.595091168
Short name T112
Test name
Test status
Simulation time 426773526 ps
CPU time 1.9 seconds
Started Jul 22 06:04:12 PM PDT 24
Finished Jul 22 06:04:14 PM PDT 24
Peak memory 201644 kb
Host smart-d6a3ca52-10e9-4abe-b27b-96d00764b04c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595091168 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.595091168
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3012148037
Short name T898
Test name
Test status
Simulation time 522948602 ps
CPU time 1.93 seconds
Started Jul 22 06:04:10 PM PDT 24
Finished Jul 22 06:04:13 PM PDT 24
Peak memory 201436 kb
Host smart-c9e794f0-6ebc-4cf4-9053-d7303aad9985
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012148037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3012148037
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.890999389
Short name T804
Test name
Test status
Simulation time 420460392 ps
CPU time 1.44 seconds
Started Jul 22 06:04:09 PM PDT 24
Finished Jul 22 06:04:10 PM PDT 24
Peak memory 201376 kb
Host smart-0b10752f-fe11-43a9-bfca-3b0607ba9012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890999389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.890999389
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.677321879
Short name T867
Test name
Test status
Simulation time 2439747722 ps
CPU time 2.81 seconds
Started Jul 22 06:04:10 PM PDT 24
Finished Jul 22 06:04:14 PM PDT 24
Peak memory 201524 kb
Host smart-fdc9682e-b8a8-488f-b7d9-66749adf9be1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677321879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.677321879
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3515919197
Short name T864
Test name
Test status
Simulation time 538843061 ps
CPU time 3.16 seconds
Started Jul 22 06:04:04 PM PDT 24
Finished Jul 22 06:04:08 PM PDT 24
Peak memory 201820 kb
Host smart-9479cd49-f915-4b43-9d9b-89a19f7d649a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515919197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3515919197
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2383687526
Short name T818
Test name
Test status
Simulation time 4536626182 ps
CPU time 4.04 seconds
Started Jul 22 06:04:04 PM PDT 24
Finished Jul 22 06:04:08 PM PDT 24
Peak memory 201796 kb
Host smart-f6b3322c-3ea9-4a28-81ae-559ab4edbd95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383687526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2383687526
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1791499713
Short name T89
Test name
Test status
Simulation time 410542874 ps
CPU time 1.82 seconds
Started Jul 22 06:04:15 PM PDT 24
Finished Jul 22 06:04:19 PM PDT 24
Peak memory 201512 kb
Host smart-51b39adf-eb6a-47e1-b231-6acc1cbb9148
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791499713 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1791499713
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1510984220
Short name T905
Test name
Test status
Simulation time 454474582 ps
CPU time 1.3 seconds
Started Jul 22 06:04:12 PM PDT 24
Finished Jul 22 06:04:14 PM PDT 24
Peak memory 201436 kb
Host smart-9cc0576c-2c4b-4697-9f96-a3acc36bfeab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510984220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1510984220
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1543344831
Short name T859
Test name
Test status
Simulation time 438509420 ps
CPU time 0.91 seconds
Started Jul 22 06:04:59 PM PDT 24
Finished Jul 22 06:05:05 PM PDT 24
Peak memory 201396 kb
Host smart-f8dac9d3-a28e-42d9-b5b0-95835587c5a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543344831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1543344831
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1001083839
Short name T883
Test name
Test status
Simulation time 4198917870 ps
CPU time 6.12 seconds
Started Jul 22 06:04:16 PM PDT 24
Finished Jul 22 06:04:24 PM PDT 24
Peak memory 201792 kb
Host smart-065f1243-02ce-4501-a87b-1092f58eca0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001083839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1001083839
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3674786426
Short name T871
Test name
Test status
Simulation time 509349632 ps
CPU time 3.49 seconds
Started Jul 22 06:04:15 PM PDT 24
Finished Jul 22 06:04:21 PM PDT 24
Peak memory 201792 kb
Host smart-439778a8-8930-44b9-ad84-9a2568285479
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674786426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3674786426
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2220408622
Short name T840
Test name
Test status
Simulation time 4557443814 ps
CPU time 3.3 seconds
Started Jul 22 06:04:16 PM PDT 24
Finished Jul 22 06:04:21 PM PDT 24
Peak memory 201620 kb
Host smart-4097aeb1-6164-4419-bf07-a7f13748fb9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220408622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2220408622
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2054708950
Short name T81
Test name
Test status
Simulation time 458849999 ps
CPU time 1.1 seconds
Started Jul 22 06:04:13 PM PDT 24
Finished Jul 22 06:04:16 PM PDT 24
Peak memory 201656 kb
Host smart-67a5f699-481b-4b91-98d9-0b324020a481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054708950 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2054708950
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3958806000
Short name T136
Test name
Test status
Simulation time 459915410 ps
CPU time 1.59 seconds
Started Jul 22 06:04:13 PM PDT 24
Finished Jul 22 06:04:15 PM PDT 24
Peak memory 201372 kb
Host smart-de3ab224-c7ac-4c12-b10e-6b61116b713f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958806000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3958806000
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3771057799
Short name T807
Test name
Test status
Simulation time 408454092 ps
CPU time 1.44 seconds
Started Jul 22 06:07:41 PM PDT 24
Finished Jul 22 06:07:44 PM PDT 24
Peak memory 201436 kb
Host smart-c05449da-4b59-42ed-abf4-67ed2e53c114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771057799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3771057799
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.187373281
Short name T825
Test name
Test status
Simulation time 3928317623 ps
CPU time 3.32 seconds
Started Jul 22 06:04:13 PM PDT 24
Finished Jul 22 06:04:18 PM PDT 24
Peak memory 201720 kb
Host smart-783b1068-d6a4-4e21-89c8-2c4ecefb9b00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187373281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.187373281
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.257525132
Short name T838
Test name
Test status
Simulation time 625137174 ps
CPU time 1.67 seconds
Started Jul 22 06:04:12 PM PDT 24
Finished Jul 22 06:04:14 PM PDT 24
Peak memory 201764 kb
Host smart-1db4ca06-e4f5-4078-97b1-d6411fd3ef08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257525132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.257525132
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2197548636
Short name T850
Test name
Test status
Simulation time 8425748413 ps
CPU time 7.36 seconds
Started Jul 22 06:04:12 PM PDT 24
Finished Jul 22 06:04:21 PM PDT 24
Peak memory 201856 kb
Host smart-73b913d0-4568-4064-9091-9fe855871b58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197548636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2197548636
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2578168788
Short name T910
Test name
Test status
Simulation time 404482377 ps
CPU time 1.14 seconds
Started Jul 22 06:04:12 PM PDT 24
Finished Jul 22 06:04:14 PM PDT 24
Peak memory 201496 kb
Host smart-458a871d-0339-4b34-8cd5-7dd6320eb827
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578168788 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2578168788
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2620851113
Short name T870
Test name
Test status
Simulation time 308286536 ps
CPU time 1.35 seconds
Started Jul 22 06:04:34 PM PDT 24
Finished Jul 22 06:04:36 PM PDT 24
Peak memory 201392 kb
Host smart-c1c401bc-95c9-4f10-805b-93403f81f65c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620851113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2620851113
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.137636146
Short name T148
Test name
Test status
Simulation time 2037822547 ps
CPU time 3.83 seconds
Started Jul 22 06:04:53 PM PDT 24
Finished Jul 22 06:04:58 PM PDT 24
Peak memory 201520 kb
Host smart-7dacf0b8-ed8b-4635-850d-0c44eb43e96f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137636146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.137636146
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.165298031
Short name T87
Test name
Test status
Simulation time 574672603 ps
CPU time 3.39 seconds
Started Jul 22 06:04:11 PM PDT 24
Finished Jul 22 06:04:15 PM PDT 24
Peak memory 218068 kb
Host smart-ac77894b-62b2-4c26-8a91-33fecc39a9f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165298031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.165298031
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3622629878
Short name T852
Test name
Test status
Simulation time 384719546 ps
CPU time 1.72 seconds
Started Jul 22 06:04:17 PM PDT 24
Finished Jul 22 06:04:20 PM PDT 24
Peak memory 201556 kb
Host smart-59616683-c30c-4924-8b9a-6520237538a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622629878 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3622629878
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1719973190
Short name T149
Test name
Test status
Simulation time 362247147 ps
CPU time 1.69 seconds
Started Jul 22 06:04:22 PM PDT 24
Finished Jul 22 06:04:25 PM PDT 24
Peak memory 201404 kb
Host smart-48d2e9ea-2d89-44a8-9a71-4bfbe9a0d677
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719973190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1719973190
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2750253677
Short name T856
Test name
Test status
Simulation time 523629386 ps
CPU time 0.92 seconds
Started Jul 22 06:04:37 PM PDT 24
Finished Jul 22 06:04:39 PM PDT 24
Peak memory 201392 kb
Host smart-47bfcd6d-f470-4444-b34c-eebac2e3298f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750253677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2750253677
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1367998517
Short name T820
Test name
Test status
Simulation time 4878898612 ps
CPU time 3.58 seconds
Started Jul 22 06:04:14 PM PDT 24
Finished Jul 22 06:04:20 PM PDT 24
Peak memory 201756 kb
Host smart-b2ac598d-a2e2-4c9f-851b-a8b91e728798
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367998517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1367998517
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2798700618
Short name T915
Test name
Test status
Simulation time 1241395099 ps
CPU time 1.76 seconds
Started Jul 22 06:04:10 PM PDT 24
Finished Jul 22 06:04:12 PM PDT 24
Peak memory 201716 kb
Host smart-cf7e577f-71d2-484d-a06c-93599dd87960
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798700618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2798700618
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1363543816
Short name T839
Test name
Test status
Simulation time 4117533718 ps
CPU time 10.64 seconds
Started Jul 22 06:04:11 PM PDT 24
Finished Jul 22 06:04:23 PM PDT 24
Peak memory 202008 kb
Host smart-dcea1711-9205-4d11-91bf-097bf0969bd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363543816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1363543816
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.982508173
Short name T902
Test name
Test status
Simulation time 515872782 ps
CPU time 2.16 seconds
Started Jul 22 06:04:08 PM PDT 24
Finished Jul 22 06:04:11 PM PDT 24
Peak memory 201656 kb
Host smart-3ac796a3-9afc-472b-9838-2165920dc191
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982508173 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.982508173
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2310126618
Short name T878
Test name
Test status
Simulation time 427571083 ps
CPU time 1.07 seconds
Started Jul 22 06:04:14 PM PDT 24
Finished Jul 22 06:04:18 PM PDT 24
Peak memory 201428 kb
Host smart-25905751-7dcb-4024-964d-e7393e5f7b66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310126618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2310126618
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.764638404
Short name T849
Test name
Test status
Simulation time 400966401 ps
CPU time 0.9 seconds
Started Jul 22 06:04:56 PM PDT 24
Finished Jul 22 06:04:58 PM PDT 24
Peak memory 201436 kb
Host smart-dd74e354-1829-4867-b570-fa7de4d5bbd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764638404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.764638404
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1915812602
Short name T831
Test name
Test status
Simulation time 5494799692 ps
CPU time 3.96 seconds
Started Jul 22 06:05:00 PM PDT 24
Finished Jul 22 06:05:04 PM PDT 24
Peak memory 201788 kb
Host smart-885555e7-3393-4208-9e7b-333bebe3bfab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915812602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1915812602
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4065131912
Short name T896
Test name
Test status
Simulation time 1352448107 ps
CPU time 1.95 seconds
Started Jul 22 06:04:13 PM PDT 24
Finished Jul 22 06:04:16 PM PDT 24
Peak memory 209948 kb
Host smart-80f2633a-01a5-4143-bd91-9fea47536dba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065131912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.4065131912
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3028283871
Short name T901
Test name
Test status
Simulation time 8727425972 ps
CPU time 19.76 seconds
Started Jul 22 06:04:13 PM PDT 24
Finished Jul 22 06:04:34 PM PDT 24
Peak memory 201716 kb
Host smart-d29142db-7714-49c1-b39c-4b6961214247
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028283871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3028283871
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1010604937
Short name T134
Test name
Test status
Simulation time 542702086 ps
CPU time 2.98 seconds
Started Jul 22 06:03:54 PM PDT 24
Finished Jul 22 06:03:58 PM PDT 24
Peak memory 201640 kb
Host smart-99733d8d-b645-4710-ba1b-afb79d61c26b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010604937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1010604937
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1338516686
Short name T833
Test name
Test status
Simulation time 52512565981 ps
CPU time 129.06 seconds
Started Jul 22 06:03:55 PM PDT 24
Finished Jul 22 06:06:05 PM PDT 24
Peak memory 201736 kb
Host smart-5082eb86-034d-4cde-b5cd-c592d1ea3092
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338516686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1338516686
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3453219357
Short name T812
Test name
Test status
Simulation time 716696269 ps
CPU time 2.57 seconds
Started Jul 22 06:03:58 PM PDT 24
Finished Jul 22 06:04:02 PM PDT 24
Peak memory 201440 kb
Host smart-bb2129b5-3bb4-400a-abcc-bce662347579
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453219357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3453219357
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.997498407
Short name T94
Test name
Test status
Simulation time 504107512 ps
CPU time 1.56 seconds
Started Jul 22 06:03:53 PM PDT 24
Finished Jul 22 06:03:56 PM PDT 24
Peak memory 201400 kb
Host smart-9779b7ca-e899-49a5-9af4-2b26be557609
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997498407 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.997498407
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1265419841
Short name T145
Test name
Test status
Simulation time 483689700 ps
CPU time 1.17 seconds
Started Jul 22 06:03:57 PM PDT 24
Finished Jul 22 06:03:59 PM PDT 24
Peak memory 201424 kb
Host smart-7d8ebf12-1aae-4873-ac0e-42fd96f94917
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265419841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1265419841
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2563746337
Short name T829
Test name
Test status
Simulation time 349526820 ps
CPU time 0.78 seconds
Started Jul 22 06:03:52 PM PDT 24
Finished Jul 22 06:03:55 PM PDT 24
Peak memory 201392 kb
Host smart-ac2fe21d-d645-4794-9acc-9e1d95c65ba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563746337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2563746337
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2482391211
Short name T147
Test name
Test status
Simulation time 4608708060 ps
CPU time 3.66 seconds
Started Jul 22 06:03:53 PM PDT 24
Finished Jul 22 06:03:58 PM PDT 24
Peak memory 201808 kb
Host smart-bbd36d43-d040-4130-bdb7-fc725835c65f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482391211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2482391211
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3215782809
Short name T837
Test name
Test status
Simulation time 667553865 ps
CPU time 2.39 seconds
Started Jul 22 06:04:42 PM PDT 24
Finished Jul 22 06:04:46 PM PDT 24
Peak memory 201780 kb
Host smart-d3c683e0-e9d3-4bab-a89b-08ee8b029f05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215782809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3215782809
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.94195724
Short name T872
Test name
Test status
Simulation time 4300684481 ps
CPU time 3.78 seconds
Started Jul 22 06:03:51 PM PDT 24
Finished Jul 22 06:03:56 PM PDT 24
Peak memory 201880 kb
Host smart-5cd2aa0a-ced8-44a9-b373-eeb5a95341c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94195724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_intg
_err.94195724
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2499984296
Short name T906
Test name
Test status
Simulation time 495044238 ps
CPU time 0.85 seconds
Started Jul 22 06:04:38 PM PDT 24
Finished Jul 22 06:04:39 PM PDT 24
Peak memory 201392 kb
Host smart-31e0339e-b4dc-4b61-8c3a-ee601d9aebdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499984296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2499984296
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2752861977
Short name T876
Test name
Test status
Simulation time 501555938 ps
CPU time 1.33 seconds
Started Jul 22 06:04:14 PM PDT 24
Finished Jul 22 06:04:17 PM PDT 24
Peak memory 201380 kb
Host smart-5584f15f-ef8b-40ea-9608-4e610c594199
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752861977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2752861977
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.394598952
Short name T860
Test name
Test status
Simulation time 404288042 ps
CPU time 0.76 seconds
Started Jul 22 06:04:16 PM PDT 24
Finished Jul 22 06:04:18 PM PDT 24
Peak memory 201256 kb
Host smart-36e92433-0d3d-4b01-8316-00cdf623696e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394598952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.394598952
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2691802539
Short name T861
Test name
Test status
Simulation time 356280486 ps
CPU time 1.47 seconds
Started Jul 22 06:05:32 PM PDT 24
Finished Jul 22 06:05:34 PM PDT 24
Peak memory 201436 kb
Host smart-849a36ce-240a-44fe-86cd-c3d43562bb54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691802539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2691802539
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.539742476
Short name T893
Test name
Test status
Simulation time 539298697 ps
CPU time 1.23 seconds
Started Jul 22 06:04:10 PM PDT 24
Finished Jul 22 06:04:12 PM PDT 24
Peak memory 201484 kb
Host smart-3e7b0c10-58e4-49bf-8063-aa03041cdf4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539742476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.539742476
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2882913255
Short name T858
Test name
Test status
Simulation time 361880674 ps
CPU time 0.78 seconds
Started Jul 22 06:04:15 PM PDT 24
Finished Jul 22 06:04:18 PM PDT 24
Peak memory 201424 kb
Host smart-fc10c663-2792-4b7e-8c4b-72e9913e5f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882913255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2882913255
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.4023685416
Short name T904
Test name
Test status
Simulation time 433807443 ps
CPU time 1.11 seconds
Started Jul 22 06:04:14 PM PDT 24
Finished Jul 22 06:04:17 PM PDT 24
Peak memory 201460 kb
Host smart-f8625c18-f22f-45f3-a1a5-143add87dfac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023685416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.4023685416
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2959825639
Short name T814
Test name
Test status
Simulation time 425408328 ps
CPU time 1.55 seconds
Started Jul 22 06:04:15 PM PDT 24
Finished Jul 22 06:04:19 PM PDT 24
Peak memory 201428 kb
Host smart-fd190f81-0684-47c5-a5b2-f0b779114804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959825639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2959825639
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.582099233
Short name T843
Test name
Test status
Simulation time 421266217 ps
CPU time 1.64 seconds
Started Jul 22 06:04:14 PM PDT 24
Finished Jul 22 06:04:18 PM PDT 24
Peak memory 201436 kb
Host smart-ade1b566-cad3-46ff-a19b-7ab4f12503e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582099233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.582099233
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1845656685
Short name T801
Test name
Test status
Simulation time 294210821 ps
CPU time 1.36 seconds
Started Jul 22 06:04:11 PM PDT 24
Finished Jul 22 06:04:13 PM PDT 24
Peak memory 201416 kb
Host smart-0ec689bc-dbc5-42b2-86c8-0ae35a67038d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845656685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1845656685
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2375451021
Short name T830
Test name
Test status
Simulation time 1299205340 ps
CPU time 5.72 seconds
Started Jul 22 06:03:53 PM PDT 24
Finished Jul 22 06:04:00 PM PDT 24
Peak memory 201648 kb
Host smart-446794d7-63fe-4d39-852d-0218843cb968
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375451021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2375451021
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1986064992
Short name T880
Test name
Test status
Simulation time 37539243102 ps
CPU time 15.58 seconds
Started Jul 22 06:03:55 PM PDT 24
Finished Jul 22 06:04:12 PM PDT 24
Peak memory 201748 kb
Host smart-88f50ba1-8fd3-4f48-b4ad-a0b001bdda8c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986064992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1986064992
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.894808230
Short name T899
Test name
Test status
Simulation time 899442381 ps
CPU time 1.19 seconds
Started Jul 22 06:03:59 PM PDT 24
Finished Jul 22 06:04:01 PM PDT 24
Peak memory 201424 kb
Host smart-847d3639-31a4-4151-8803-91cf1aa791b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894808230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.894808230
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1762940625
Short name T816
Test name
Test status
Simulation time 484461636 ps
CPU time 1.94 seconds
Started Jul 22 06:03:58 PM PDT 24
Finished Jul 22 06:04:01 PM PDT 24
Peak memory 201580 kb
Host smart-d8f2197c-dd8d-43d0-bd53-a163b152ebb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762940625 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1762940625
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3151006136
Short name T854
Test name
Test status
Simulation time 535573981 ps
CPU time 1.38 seconds
Started Jul 22 06:03:55 PM PDT 24
Finished Jul 22 06:03:58 PM PDT 24
Peak memory 201464 kb
Host smart-6c6f6116-6392-473d-b7fd-a3940b1dba79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151006136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3151006136
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.320542264
Short name T868
Test name
Test status
Simulation time 304759208 ps
CPU time 0.9 seconds
Started Jul 22 06:05:32 PM PDT 24
Finished Jul 22 06:05:34 PM PDT 24
Peak memory 201368 kb
Host smart-7a5216a6-bb78-47d4-81df-d05da5cf20d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320542264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.320542264
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.13169150
Short name T150
Test name
Test status
Simulation time 2431948387 ps
CPU time 10.02 seconds
Started Jul 22 06:03:53 PM PDT 24
Finished Jul 22 06:04:04 PM PDT 24
Peak memory 201580 kb
Host smart-69779fe0-dd6f-4a40-b876-3fd2ca5cd763
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13169150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctr
l_same_csr_outstanding.13169150
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3519853612
Short name T886
Test name
Test status
Simulation time 626612579 ps
CPU time 2.26 seconds
Started Jul 22 06:03:57 PM PDT 24
Finished Jul 22 06:04:00 PM PDT 24
Peak memory 201764 kb
Host smart-4f6d0a16-e23a-4c39-b23f-63fe46c2ca51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519853612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3519853612
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.789722520
Short name T209
Test name
Test status
Simulation time 4217343833 ps
CPU time 10.58 seconds
Started Jul 22 06:03:56 PM PDT 24
Finished Jul 22 06:04:07 PM PDT 24
Peak memory 201712 kb
Host smart-f890d2dc-00f0-4cce-a677-871655994474
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789722520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.789722520
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2360766437
Short name T822
Test name
Test status
Simulation time 502571063 ps
CPU time 0.97 seconds
Started Jul 22 06:04:42 PM PDT 24
Finished Jul 22 06:04:44 PM PDT 24
Peak memory 201348 kb
Host smart-df1b5a86-93e8-4c9f-a675-5082e6708ada
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360766437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2360766437
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3295258829
Short name T884
Test name
Test status
Simulation time 298797209 ps
CPU time 0.85 seconds
Started Jul 22 06:04:14 PM PDT 24
Finished Jul 22 06:04:17 PM PDT 24
Peak memory 201428 kb
Host smart-ce6cdaf4-f75d-4674-abf0-4402d0ec8831
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295258829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3295258829
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1642865998
Short name T809
Test name
Test status
Simulation time 348068471 ps
CPU time 1.38 seconds
Started Jul 22 06:04:13 PM PDT 24
Finished Jul 22 06:04:15 PM PDT 24
Peak memory 201364 kb
Host smart-e64fba23-64a9-4d6e-b9fa-055d3b7a0956
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642865998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1642865998
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3703011082
Short name T894
Test name
Test status
Simulation time 586954501 ps
CPU time 0.73 seconds
Started Jul 22 06:04:15 PM PDT 24
Finished Jul 22 06:04:18 PM PDT 24
Peak memory 201328 kb
Host smart-ce11f388-ed87-461b-a78c-91712e1d0307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703011082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3703011082
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.220945160
Short name T811
Test name
Test status
Simulation time 377583597 ps
CPU time 1.16 seconds
Started Jul 22 06:04:17 PM PDT 24
Finished Jul 22 06:04:19 PM PDT 24
Peak memory 201408 kb
Host smart-2a5a3927-0bed-40c0-ab0a-739d4720780e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220945160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.220945160
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2968020407
Short name T800
Test name
Test status
Simulation time 348235285 ps
CPU time 0.87 seconds
Started Jul 22 06:04:14 PM PDT 24
Finished Jul 22 06:04:17 PM PDT 24
Peak memory 201440 kb
Host smart-447563ca-635c-42c0-b33f-9951b2b58f03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968020407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2968020407
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2706209960
Short name T813
Test name
Test status
Simulation time 295649648 ps
CPU time 1.31 seconds
Started Jul 22 06:04:14 PM PDT 24
Finished Jul 22 06:04:18 PM PDT 24
Peak memory 201428 kb
Host smart-39201257-1544-40a7-8ce4-1bd27a51a0db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706209960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2706209960
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1483820142
Short name T826
Test name
Test status
Simulation time 478967161 ps
CPU time 1.54 seconds
Started Jul 22 06:04:13 PM PDT 24
Finished Jul 22 06:04:16 PM PDT 24
Peak memory 201380 kb
Host smart-5f0cacc3-4b2d-48c7-b167-b23ed11e6aad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483820142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1483820142
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3612287857
Short name T851
Test name
Test status
Simulation time 495860446 ps
CPU time 1.78 seconds
Started Jul 22 06:05:00 PM PDT 24
Finished Jul 22 06:05:02 PM PDT 24
Peak memory 201400 kb
Host smart-41cb6852-1682-424e-846e-a8d48a2fd4ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612287857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3612287857
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.24205941
Short name T815
Test name
Test status
Simulation time 414009576 ps
CPU time 1.56 seconds
Started Jul 22 06:04:12 PM PDT 24
Finished Jul 22 06:04:14 PM PDT 24
Peak memory 201444 kb
Host smart-644b391c-3634-477a-a78a-d24327cf01a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24205941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.24205941
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1244122357
Short name T141
Test name
Test status
Simulation time 1139382257 ps
CPU time 4.55 seconds
Started Jul 22 06:04:10 PM PDT 24
Finished Jul 22 06:04:15 PM PDT 24
Peak memory 201704 kb
Host smart-b8fbb329-6ac1-4385-82bf-c20177de823f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244122357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1244122357
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.295180370
Short name T873
Test name
Test status
Simulation time 19070774011 ps
CPU time 40.59 seconds
Started Jul 22 06:05:17 PM PDT 24
Finished Jul 22 06:05:59 PM PDT 24
Peak memory 201688 kb
Host smart-dc5f25d8-7d5b-40ff-9b13-269fa7d1f388
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295180370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.295180370
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4181383253
Short name T920
Test name
Test status
Simulation time 1271184343 ps
CPU time 1.43 seconds
Started Jul 22 06:04:01 PM PDT 24
Finished Jul 22 06:04:03 PM PDT 24
Peak memory 201376 kb
Host smart-a21b739b-b4af-4a1e-af0d-c1ec22f514ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181383253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.4181383253
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2792986206
Short name T848
Test name
Test status
Simulation time 654753981 ps
CPU time 1.25 seconds
Started Jul 22 06:04:02 PM PDT 24
Finished Jul 22 06:04:05 PM PDT 24
Peak memory 201592 kb
Host smart-59dec4d7-41b9-4984-982f-11321f5274cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792986206 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2792986206
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1157000673
Short name T151
Test name
Test status
Simulation time 606240207 ps
CPU time 1.24 seconds
Started Jul 22 06:04:03 PM PDT 24
Finished Jul 22 06:04:05 PM PDT 24
Peak memory 201424 kb
Host smart-1511fba6-d87c-43fb-91ba-675efa115b01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157000673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1157000673
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1703637532
Short name T805
Test name
Test status
Simulation time 404572258 ps
CPU time 0.84 seconds
Started Jul 22 06:04:01 PM PDT 24
Finished Jul 22 06:04:03 PM PDT 24
Peak memory 201428 kb
Host smart-5ec0c204-77a5-4868-86a1-85a3a8936dfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703637532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1703637532
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2216605160
Short name T76
Test name
Test status
Simulation time 4340644931 ps
CPU time 3.29 seconds
Started Jul 22 06:04:48 PM PDT 24
Finished Jul 22 06:04:52 PM PDT 24
Peak memory 201704 kb
Host smart-aaf009db-3548-4e6f-bbe4-c12baa57ba67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216605160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2216605160
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1453057355
Short name T912
Test name
Test status
Simulation time 1075110303 ps
CPU time 2.6 seconds
Started Jul 22 06:04:04 PM PDT 24
Finished Jul 22 06:04:07 PM PDT 24
Peak memory 218056 kb
Host smart-4355fc05-6b28-4436-9974-f040bf167c44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453057355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1453057355
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1258224059
Short name T890
Test name
Test status
Simulation time 4344562972 ps
CPU time 6.32 seconds
Started Jul 22 06:04:06 PM PDT 24
Finished Jul 22 06:04:12 PM PDT 24
Peak memory 201792 kb
Host smart-f1a981da-974b-444c-b57f-631efd7ca224
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258224059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1258224059
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.4083652159
Short name T821
Test name
Test status
Simulation time 303125121 ps
CPU time 0.79 seconds
Started Jul 22 06:05:00 PM PDT 24
Finished Jul 22 06:05:01 PM PDT 24
Peak memory 201400 kb
Host smart-2f8213e0-513a-481d-aa74-9ba452257a48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083652159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.4083652159
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3865057107
Short name T869
Test name
Test status
Simulation time 386829061 ps
CPU time 1.46 seconds
Started Jul 22 06:04:22 PM PDT 24
Finished Jul 22 06:04:24 PM PDT 24
Peak memory 201404 kb
Host smart-9d11bfb7-d894-487a-b3a5-a28aa3520cb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865057107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3865057107
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2816132209
Short name T817
Test name
Test status
Simulation time 523436395 ps
CPU time 0.98 seconds
Started Jul 22 06:04:28 PM PDT 24
Finished Jul 22 06:04:30 PM PDT 24
Peak memory 201404 kb
Host smart-0e05314a-d53a-4d47-9621-e3ff4c258992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816132209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2816132209
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.397397239
Short name T802
Test name
Test status
Simulation time 520818075 ps
CPU time 1.47 seconds
Started Jul 22 06:04:13 PM PDT 24
Finished Jul 22 06:04:15 PM PDT 24
Peak memory 201428 kb
Host smart-e51374c5-df74-433d-9055-c23a3ad358ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397397239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.397397239
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.923079800
Short name T846
Test name
Test status
Simulation time 529240859 ps
CPU time 1.88 seconds
Started Jul 22 06:04:15 PM PDT 24
Finished Jul 22 06:04:19 PM PDT 24
Peak memory 201424 kb
Host smart-68e0614d-fdc7-449f-864c-f3609b46e970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923079800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.923079800
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1087219889
Short name T914
Test name
Test status
Simulation time 518887711 ps
CPU time 0.83 seconds
Started Jul 22 06:04:14 PM PDT 24
Finished Jul 22 06:04:17 PM PDT 24
Peak memory 201376 kb
Host smart-1c134676-51f1-4777-bdb6-f0626379237e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087219889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1087219889
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.276172958
Short name T865
Test name
Test status
Simulation time 398728993 ps
CPU time 0.75 seconds
Started Jul 22 06:04:12 PM PDT 24
Finished Jul 22 06:04:13 PM PDT 24
Peak memory 201408 kb
Host smart-30a129dd-f0eb-49d5-95e1-f45f4a320a3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276172958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.276172958
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4213958348
Short name T903
Test name
Test status
Simulation time 479105736 ps
CPU time 1.87 seconds
Started Jul 22 06:04:15 PM PDT 24
Finished Jul 22 06:04:19 PM PDT 24
Peak memory 201324 kb
Host smart-9bcc165e-b15d-490d-b5da-934c66d0943f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213958348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.4213958348
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2935118123
Short name T844
Test name
Test status
Simulation time 400832514 ps
CPU time 1.64 seconds
Started Jul 22 06:04:13 PM PDT 24
Finished Jul 22 06:04:16 PM PDT 24
Peak memory 201428 kb
Host smart-3ad416ec-12da-413d-9bc9-aef6173f71b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935118123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2935118123
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.982819581
Short name T897
Test name
Test status
Simulation time 433787691 ps
CPU time 1.52 seconds
Started Jul 22 06:07:41 PM PDT 24
Finished Jul 22 06:07:44 PM PDT 24
Peak memory 201436 kb
Host smart-daa8b0c6-5677-4012-a1f7-974914e94a08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982819581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.982819581
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.96102260
Short name T918
Test name
Test status
Simulation time 578282018 ps
CPU time 2.05 seconds
Started Jul 22 06:04:03 PM PDT 24
Finished Jul 22 06:04:06 PM PDT 24
Peak memory 201808 kb
Host smart-1df87c65-61f1-408e-850e-42e787ec2bee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96102260 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.96102260
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1765179977
Short name T909
Test name
Test status
Simulation time 347599326 ps
CPU time 1.05 seconds
Started Jul 22 06:04:16 PM PDT 24
Finished Jul 22 06:04:19 PM PDT 24
Peak memory 201460 kb
Host smart-1a564a8f-b39a-4f4b-811d-7dfb06033188
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765179977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1765179977
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.412442940
Short name T919
Test name
Test status
Simulation time 478403887 ps
CPU time 1.02 seconds
Started Jul 22 06:04:03 PM PDT 24
Finished Jul 22 06:04:05 PM PDT 24
Peak memory 201692 kb
Host smart-544706c1-4d0a-406d-b022-f818dd23ca14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412442940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.412442940
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3663987932
Short name T857
Test name
Test status
Simulation time 4253080074 ps
CPU time 7.53 seconds
Started Jul 22 06:04:06 PM PDT 24
Finished Jul 22 06:04:14 PM PDT 24
Peak memory 201776 kb
Host smart-933f4c32-3105-4cd8-965f-ade917985038
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663987932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3663987932
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.661611508
Short name T823
Test name
Test status
Simulation time 359711434 ps
CPU time 1.69 seconds
Started Jul 22 06:04:06 PM PDT 24
Finished Jul 22 06:04:08 PM PDT 24
Peak memory 201780 kb
Host smart-a1fdeba8-cdf4-4b6f-9e46-073318fae373
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661611508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.661611508
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3720021488
Short name T208
Test name
Test status
Simulation time 4959324500 ps
CPU time 3.26 seconds
Started Jul 22 06:04:02 PM PDT 24
Finished Jul 22 06:04:06 PM PDT 24
Peak memory 201740 kb
Host smart-369d7c76-7aba-4548-a8c1-bc0399a7a030
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720021488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3720021488
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2218684915
Short name T845
Test name
Test status
Simulation time 399516215 ps
CPU time 1.23 seconds
Started Jul 22 06:04:02 PM PDT 24
Finished Jul 22 06:04:04 PM PDT 24
Peak memory 201584 kb
Host smart-f657f96a-cb69-420d-b0aa-e820207296d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218684915 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2218684915
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1080926533
Short name T144
Test name
Test status
Simulation time 364364749 ps
CPU time 1.55 seconds
Started Jul 22 06:04:02 PM PDT 24
Finished Jul 22 06:04:04 PM PDT 24
Peak memory 201452 kb
Host smart-c5134f9b-8f62-4378-bfd1-c6dfdefa2193
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080926533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1080926533
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2214354572
Short name T917
Test name
Test status
Simulation time 350441792 ps
CPU time 1.4 seconds
Started Jul 22 06:03:59 PM PDT 24
Finished Jul 22 06:04:01 PM PDT 24
Peak memory 201536 kb
Host smart-5767e65c-82d9-4a52-bf67-f43834168845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214354572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2214354572
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3686454662
Short name T819
Test name
Test status
Simulation time 1969102635 ps
CPU time 2.06 seconds
Started Jul 22 06:04:02 PM PDT 24
Finished Jul 22 06:04:05 PM PDT 24
Peak memory 201460 kb
Host smart-c06a944d-d806-4b6b-8f44-a300349f8713
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686454662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3686454662
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3504490049
Short name T95
Test name
Test status
Simulation time 497924513 ps
CPU time 3.86 seconds
Started Jul 22 06:04:02 PM PDT 24
Finished Jul 22 06:04:07 PM PDT 24
Peak memory 211004 kb
Host smart-c3bcbd9a-88c9-4159-b3d0-8c0abe660e50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504490049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3504490049
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3269103202
Short name T834
Test name
Test status
Simulation time 8432451407 ps
CPU time 6.85 seconds
Started Jul 22 06:04:02 PM PDT 24
Finished Jul 22 06:04:10 PM PDT 24
Peak memory 201720 kb
Host smart-3753b124-4bf9-4254-9e9e-440699026cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269103202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3269103202
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1205857396
Short name T111
Test name
Test status
Simulation time 539229035 ps
CPU time 1.46 seconds
Started Jul 22 06:04:57 PM PDT 24
Finished Jul 22 06:04:59 PM PDT 24
Peak memory 201584 kb
Host smart-8ec8d1f8-8b15-4372-8db2-a4de460dcd6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205857396 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1205857396
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.4120175985
Short name T877
Test name
Test status
Simulation time 466894012 ps
CPU time 1.35 seconds
Started Jul 22 06:04:05 PM PDT 24
Finished Jul 22 06:04:07 PM PDT 24
Peak memory 201448 kb
Host smart-bb76c8c1-70f2-46c6-908f-b4294db122c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120175985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.4120175985
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3283654266
Short name T841
Test name
Test status
Simulation time 333560752 ps
CPU time 0.73 seconds
Started Jul 22 06:04:05 PM PDT 24
Finished Jul 22 06:04:06 PM PDT 24
Peak memory 201508 kb
Host smart-9836fd42-bb01-4f99-ad3e-51bf4574e611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283654266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3283654266
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3797436868
Short name T75
Test name
Test status
Simulation time 2482223870 ps
CPU time 4.66 seconds
Started Jul 22 06:04:10 PM PDT 24
Finished Jul 22 06:04:16 PM PDT 24
Peak memory 201428 kb
Host smart-6ca82d6d-2a5c-4a04-8776-a729a40ff254
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797436868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3797436868
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4197341306
Short name T82
Test name
Test status
Simulation time 531299542 ps
CPU time 2.89 seconds
Started Jul 22 06:05:17 PM PDT 24
Finished Jul 22 06:05:21 PM PDT 24
Peak memory 209984 kb
Host smart-dbc5a0d3-0308-4e12-98e3-cb95d553050c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197341306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.4197341306
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2565921151
Short name T79
Test name
Test status
Simulation time 4507118023 ps
CPU time 9.04 seconds
Started Jul 22 06:04:57 PM PDT 24
Finished Jul 22 06:05:07 PM PDT 24
Peak memory 201776 kb
Host smart-539084d1-b096-4443-9296-ef7939b3df46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565921151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2565921151
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1269080012
Short name T888
Test name
Test status
Simulation time 351829764 ps
CPU time 1.73 seconds
Started Jul 22 06:04:01 PM PDT 24
Finished Jul 22 06:04:04 PM PDT 24
Peak memory 201820 kb
Host smart-f445290d-b364-4a03-932b-2d9d986a5e78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269080012 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1269080012
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1583317787
Short name T891
Test name
Test status
Simulation time 450338028 ps
CPU time 1.06 seconds
Started Jul 22 06:04:04 PM PDT 24
Finished Jul 22 06:04:06 PM PDT 24
Peak memory 201440 kb
Host smart-44ddec80-f19e-4038-b3ad-2c40f41a1789
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583317787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1583317787
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.29276370
Short name T828
Test name
Test status
Simulation time 328529290 ps
CPU time 1.51 seconds
Started Jul 22 06:04:06 PM PDT 24
Finished Jul 22 06:04:09 PM PDT 24
Peak memory 201324 kb
Host smart-03c3ef11-ce62-4521-8983-38811e71d0ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29276370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.29276370
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2897636267
Short name T853
Test name
Test status
Simulation time 2717298634 ps
CPU time 5.12 seconds
Started Jul 22 06:04:00 PM PDT 24
Finished Jul 22 06:04:06 PM PDT 24
Peak memory 201552 kb
Host smart-94230c7f-0fb3-43d4-9220-01a653073e28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897636267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2897636267
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1145287165
Short name T842
Test name
Test status
Simulation time 4746622770 ps
CPU time 2.25 seconds
Started Jul 22 06:04:10 PM PDT 24
Finished Jul 22 06:04:12 PM PDT 24
Peak memory 201780 kb
Host smart-bdba1938-f568-48cd-be0b-3e47da98f6e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145287165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1145287165
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.675473698
Short name T892
Test name
Test status
Simulation time 396613039 ps
CPU time 1.36 seconds
Started Jul 22 06:05:34 PM PDT 24
Finished Jul 22 06:05:36 PM PDT 24
Peak memory 201500 kb
Host smart-3336ca51-26fa-459a-a439-12172580e52a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675473698 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.675473698
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.865204840
Short name T885
Test name
Test status
Simulation time 298142678 ps
CPU time 1.46 seconds
Started Jul 22 06:04:22 PM PDT 24
Finished Jul 22 06:04:24 PM PDT 24
Peak memory 201408 kb
Host smart-78078612-8d36-46b8-83bf-16c21427fc1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865204840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.865204840
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2257975628
Short name T832
Test name
Test status
Simulation time 507583065 ps
CPU time 1.29 seconds
Started Jul 22 06:04:03 PM PDT 24
Finished Jul 22 06:04:05 PM PDT 24
Peak memory 201448 kb
Host smart-4dd7dde2-3ac0-4783-8d76-9a0a9259e251
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257975628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2257975628
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2956841740
Short name T900
Test name
Test status
Simulation time 4195373687 ps
CPU time 13.24 seconds
Started Jul 22 06:04:11 PM PDT 24
Finished Jul 22 06:04:25 PM PDT 24
Peak memory 201828 kb
Host smart-a4e97af1-a782-48aa-bfb4-eb33f43c160c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956841740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2956841740
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1222157673
Short name T889
Test name
Test status
Simulation time 488168476 ps
CPU time 1.65 seconds
Started Jul 22 06:04:02 PM PDT 24
Finished Jul 22 06:04:04 PM PDT 24
Peak memory 201796 kb
Host smart-083e3263-dd7b-42c7-83ef-7301ab45435d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222157673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1222157673
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1200139962
Short name T210
Test name
Test status
Simulation time 4507534195 ps
CPU time 3.91 seconds
Started Jul 22 06:04:04 PM PDT 24
Finished Jul 22 06:04:08 PM PDT 24
Peak memory 201720 kb
Host smart-d44978d6-fdfd-484e-b896-b9c54ed1d1cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200139962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1200139962
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2806767307
Short name T396
Test name
Test status
Simulation time 525948173 ps
CPU time 0.96 seconds
Started Jul 22 06:04:25 PM PDT 24
Finished Jul 22 06:04:27 PM PDT 24
Peak memory 200944 kb
Host smart-f8492147-8967-49d2-b2f3-4e66d3995f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806767307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2806767307
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.506706492
Short name T229
Test name
Test status
Simulation time 174881765561 ps
CPU time 281.42 seconds
Started Jul 22 06:04:36 PM PDT 24
Finished Jul 22 06:09:18 PM PDT 24
Peak memory 201196 kb
Host smart-ed9739b1-a12f-4341-9d43-53c46d600203
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506706492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.506706492
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.4034524319
Short name T297
Test name
Test status
Simulation time 180210358864 ps
CPU time 226.44 seconds
Started Jul 22 06:04:33 PM PDT 24
Finished Jul 22 06:08:20 PM PDT 24
Peak memory 201228 kb
Host smart-36dc4ab5-46c4-47c0-a211-0925cae0a2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034524319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.4034524319
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.923907439
Short name T333
Test name
Test status
Simulation time 479112597749 ps
CPU time 160.26 seconds
Started Jul 22 06:04:30 PM PDT 24
Finished Jul 22 06:07:10 PM PDT 24
Peak memory 201212 kb
Host smart-94f7ac9f-4566-4952-b231-b7177da04bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923907439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.923907439
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2465136141
Short name T450
Test name
Test status
Simulation time 488459084733 ps
CPU time 1057.72 seconds
Started Jul 22 06:04:36 PM PDT 24
Finished Jul 22 06:22:14 PM PDT 24
Peak memory 201180 kb
Host smart-84c2c543-381a-4377-9b18-2d29860cd4d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465136141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2465136141
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3436629824
Short name T162
Test name
Test status
Simulation time 320954699546 ps
CPU time 190.78 seconds
Started Jul 22 06:04:15 PM PDT 24
Finished Jul 22 06:07:28 PM PDT 24
Peak memory 201112 kb
Host smart-4b85813c-6d40-4f86-b99e-b874c10c808e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436629824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3436629824
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1177401224
Short name T650
Test name
Test status
Simulation time 328108744567 ps
CPU time 785.77 seconds
Started Jul 22 06:04:16 PM PDT 24
Finished Jul 22 06:17:23 PM PDT 24
Peak memory 201096 kb
Host smart-7cbbd296-784c-466a-9462-61ff725b210c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177401224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1177401224
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2709573317
Short name T539
Test name
Test status
Simulation time 397401088735 ps
CPU time 817.52 seconds
Started Jul 22 06:04:32 PM PDT 24
Finished Jul 22 06:18:10 PM PDT 24
Peak memory 201212 kb
Host smart-9742e21c-6ab3-4ff9-b8e4-b77e8169787a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709573317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2709573317
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3257400512
Short name T527
Test name
Test status
Simulation time 97620188689 ps
CPU time 350.52 seconds
Started Jul 22 06:04:47 PM PDT 24
Finished Jul 22 06:10:39 PM PDT 24
Peak memory 201704 kb
Host smart-42d0926d-746c-40ee-97dd-c6b0b0bdd705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257400512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3257400512
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3895977072
Short name T513
Test name
Test status
Simulation time 40948739873 ps
CPU time 21.56 seconds
Started Jul 22 06:04:23 PM PDT 24
Finished Jul 22 06:04:45 PM PDT 24
Peak memory 200956 kb
Host smart-5b8d4ec0-8562-4374-8762-c2b82b3fe4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895977072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3895977072
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.4212730794
Short name T449
Test name
Test status
Simulation time 2974095376 ps
CPU time 5.63 seconds
Started Jul 22 06:04:33 PM PDT 24
Finished Jul 22 06:04:39 PM PDT 24
Peak memory 201216 kb
Host smart-233a2fc5-8323-4139-9582-c4992ffc6b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212730794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.4212730794
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.4169441192
Short name T563
Test name
Test status
Simulation time 5768228322 ps
CPU time 15.07 seconds
Started Jul 22 06:04:14 PM PDT 24
Finished Jul 22 06:04:31 PM PDT 24
Peak memory 201076 kb
Host smart-d5768b97-0226-481e-94d9-d3c233978e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169441192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.4169441192
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1545712214
Short name T300
Test name
Test status
Simulation time 191169578752 ps
CPU time 434.12 seconds
Started Jul 22 06:04:27 PM PDT 24
Finished Jul 22 06:11:42 PM PDT 24
Peak memory 201220 kb
Host smart-cf7252f2-9f31-4fbc-93ec-90a1e46b2a64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545712214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1545712214
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.4040058232
Short name T64
Test name
Test status
Simulation time 100567308246 ps
CPU time 135.42 seconds
Started Jul 22 06:04:42 PM PDT 24
Finished Jul 22 06:06:58 PM PDT 24
Peak memory 217116 kb
Host smart-f003e378-ace1-4eca-9d12-fb0b627b38d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040058232 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.4040058232
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3431711115
Short name T663
Test name
Test status
Simulation time 579743906800 ps
CPU time 315.06 seconds
Started Jul 22 06:04:34 PM PDT 24
Finished Jul 22 06:09:49 PM PDT 24
Peak memory 201196 kb
Host smart-b9a7d496-7434-42f7-a95e-6de6ecb2a373
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431711115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3431711115
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.4062282854
Short name T241
Test name
Test status
Simulation time 163155592426 ps
CPU time 348.12 seconds
Started Jul 22 06:04:34 PM PDT 24
Finished Jul 22 06:10:22 PM PDT 24
Peak memory 201176 kb
Host smart-7985181c-075c-4a5d-a158-ac318703a8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062282854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.4062282854
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.523260410
Short name T496
Test name
Test status
Simulation time 164194678488 ps
CPU time 359.79 seconds
Started Jul 22 06:07:42 PM PDT 24
Finished Jul 22 06:13:44 PM PDT 24
Peak memory 201304 kb
Host smart-fbf40587-80fe-452a-ba5d-93060c864714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523260410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.523260410
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1041943563
Short name T491
Test name
Test status
Simulation time 502672684569 ps
CPU time 315.05 seconds
Started Jul 22 06:04:23 PM PDT 24
Finished Jul 22 06:09:38 PM PDT 24
Peak memory 201200 kb
Host smart-dcd356fe-7afa-48b0-8340-a7d572bfcbfb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041943563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1041943563
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3898372569
Short name T345
Test name
Test status
Simulation time 352287987635 ps
CPU time 851.89 seconds
Started Jul 22 06:04:33 PM PDT 24
Finished Jul 22 06:18:46 PM PDT 24
Peak memory 201208 kb
Host smart-2e388a32-3dc4-4e30-8889-8647002f20d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898372569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3898372569
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.4069963776
Short name T440
Test name
Test status
Simulation time 207127252756 ps
CPU time 238.89 seconds
Started Jul 22 06:04:20 PM PDT 24
Finished Jul 22 06:08:19 PM PDT 24
Peak memory 201140 kb
Host smart-d472bbbc-3c63-4ae7-857c-c5c9a6ffa740
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069963776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.4069963776
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2241858189
Short name T479
Test name
Test status
Simulation time 135941942118 ps
CPU time 496 seconds
Started Jul 22 06:04:26 PM PDT 24
Finished Jul 22 06:12:42 PM PDT 24
Peak memory 201744 kb
Host smart-0b264562-8d49-4077-948c-0ed58fd586be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241858189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2241858189
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2249078248
Short name T385
Test name
Test status
Simulation time 41726992050 ps
CPU time 86.59 seconds
Started Jul 22 06:04:27 PM PDT 24
Finished Jul 22 06:05:54 PM PDT 24
Peak memory 201060 kb
Host smart-115ab3e1-92f5-43a7-b066-870a050e4df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249078248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2249078248
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1132904514
Short name T538
Test name
Test status
Simulation time 3489919654 ps
CPU time 3.14 seconds
Started Jul 22 06:04:37 PM PDT 24
Finished Jul 22 06:04:40 PM PDT 24
Peak memory 201060 kb
Host smart-ed80d343-aa93-43aa-bed6-18fba4df61fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132904514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1132904514
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.228698878
Short name T85
Test name
Test status
Simulation time 7202866546 ps
CPU time 8.61 seconds
Started Jul 22 06:04:31 PM PDT 24
Finished Jul 22 06:04:41 PM PDT 24
Peak memory 218052 kb
Host smart-37522cd7-efbd-4b9f-9716-198d6c57be37
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228698878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.228698878
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2068769461
Short name T458
Test name
Test status
Simulation time 5628776851 ps
CPU time 4.2 seconds
Started Jul 22 06:04:32 PM PDT 24
Finished Jul 22 06:04:37 PM PDT 24
Peak memory 201072 kb
Host smart-2578acaf-2fcc-4ad7-9657-8b698afdd594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068769461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2068769461
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3565161443
Short name T258
Test name
Test status
Simulation time 397143749463 ps
CPU time 83.15 seconds
Started Jul 22 06:04:29 PM PDT 24
Finished Jul 22 06:05:53 PM PDT 24
Peak memory 201188 kb
Host smart-3069232d-d7ac-41b2-a5ce-2825338bcb5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565161443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3565161443
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1568293838
Short name T606
Test name
Test status
Simulation time 267321610831 ps
CPU time 244.18 seconds
Started Jul 22 06:04:19 PM PDT 24
Finished Jul 22 06:08:24 PM PDT 24
Peak memory 209756 kb
Host smart-5c4a5202-42e3-4151-8a19-4c9a159ae3b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568293838 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1568293838
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3837159954
Short name T657
Test name
Test status
Simulation time 522465450 ps
CPU time 0.99 seconds
Started Jul 22 06:05:03 PM PDT 24
Finished Jul 22 06:05:04 PM PDT 24
Peak memory 201016 kb
Host smart-06bda311-62f3-4ada-aac1-6f0b685135fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837159954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3837159954
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3545248568
Short name T244
Test name
Test status
Simulation time 179990477029 ps
CPU time 374.57 seconds
Started Jul 22 06:04:50 PM PDT 24
Finished Jul 22 06:11:05 PM PDT 24
Peak memory 201260 kb
Host smart-36ce8a78-aa91-4fc7-9d79-861514a2101d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545248568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3545248568
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2445791981
Short name T522
Test name
Test status
Simulation time 162632995269 ps
CPU time 92.32 seconds
Started Jul 22 06:04:57 PM PDT 24
Finished Jul 22 06:06:30 PM PDT 24
Peak memory 201248 kb
Host smart-73145469-c370-40ae-9a3b-41e19a22038a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445791981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2445791981
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.422251789
Short name T399
Test name
Test status
Simulation time 494499978089 ps
CPU time 1137.43 seconds
Started Jul 22 06:04:51 PM PDT 24
Finished Jul 22 06:23:50 PM PDT 24
Peak memory 201268 kb
Host smart-ff451bc4-ab69-4362-b518-71f2f8b9c0e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=422251789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.422251789
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3293941902
Short name T656
Test name
Test status
Simulation time 488267142599 ps
CPU time 270.91 seconds
Started Jul 22 06:04:49 PM PDT 24
Finished Jul 22 06:09:21 PM PDT 24
Peak memory 201212 kb
Host smart-ec3062c8-d190-42d2-b94d-b5e146cf1f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293941902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3293941902
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.295601406
Short name T693
Test name
Test status
Simulation time 488996631055 ps
CPU time 530.46 seconds
Started Jul 22 06:04:49 PM PDT 24
Finished Jul 22 06:13:40 PM PDT 24
Peak memory 201228 kb
Host smart-ee68de85-9e2a-4738-839e-cac775a29de6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=295601406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.295601406
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2032673686
Short name T738
Test name
Test status
Simulation time 172200871282 ps
CPU time 396.2 seconds
Started Jul 22 06:04:55 PM PDT 24
Finished Jul 22 06:11:32 PM PDT 24
Peak memory 201292 kb
Host smart-4445b914-9825-45a6-916a-e165e29e82ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032673686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2032673686
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2138324863
Short name T751
Test name
Test status
Simulation time 194836674435 ps
CPU time 397.75 seconds
Started Jul 22 06:04:54 PM PDT 24
Finished Jul 22 06:11:33 PM PDT 24
Peak memory 201140 kb
Host smart-cbdd0eae-d7a3-424a-8ccc-b880a09d4f61
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138324863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2138324863
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2710931796
Short name T175
Test name
Test status
Simulation time 23207858432 ps
CPU time 25.71 seconds
Started Jul 22 06:04:50 PM PDT 24
Finished Jul 22 06:05:17 PM PDT 24
Peak memory 201052 kb
Host smart-2f58ee27-4091-4977-abdf-257b6e758710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710931796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2710931796
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.4268682034
Short name T61
Test name
Test status
Simulation time 4209133025 ps
CPU time 3 seconds
Started Jul 22 06:04:51 PM PDT 24
Finished Jul 22 06:04:55 PM PDT 24
Peak memory 201080 kb
Host smart-1f7d1099-a5cf-4c92-a74b-278df94069b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268682034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.4268682034
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3631071713
Short name T521
Test name
Test status
Simulation time 5964783732 ps
CPU time 8.04 seconds
Started Jul 22 06:04:49 PM PDT 24
Finished Jul 22 06:04:58 PM PDT 24
Peak memory 201100 kb
Host smart-36871e9b-e0c3-4aa8-8985-ceb1456dd7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631071713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3631071713
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3323441640
Short name T339
Test name
Test status
Simulation time 515078384884 ps
CPU time 1356.01 seconds
Started Jul 22 06:04:47 PM PDT 24
Finished Jul 22 06:27:24 PM PDT 24
Peak memory 209840 kb
Host smart-bbd568c9-aacc-4878-aa85-4e47a91af62b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323441640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3323441640
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3876294128
Short name T718
Test name
Test status
Simulation time 336648350 ps
CPU time 1.48 seconds
Started Jul 22 06:04:49 PM PDT 24
Finished Jul 22 06:04:51 PM PDT 24
Peak memory 201072 kb
Host smart-3ba7b59c-0abf-4925-9929-dc01ace19bd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876294128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3876294128
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1709986925
Short name T490
Test name
Test status
Simulation time 178736631413 ps
CPU time 279.44 seconds
Started Jul 22 06:04:58 PM PDT 24
Finished Jul 22 06:09:38 PM PDT 24
Peak memory 201284 kb
Host smart-6093b40d-7617-49f3-880c-cf71c4bc8857
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709986925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1709986925
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.4219479525
Short name T686
Test name
Test status
Simulation time 165659873445 ps
CPU time 410.18 seconds
Started Jul 22 06:04:49 PM PDT 24
Finished Jul 22 06:11:40 PM PDT 24
Peak memory 201272 kb
Host smart-5143bd5e-4d5b-484e-9020-de09dcea7bdb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219479525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.4219479525
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3652480704
Short name T416
Test name
Test status
Simulation time 330688829403 ps
CPU time 743.73 seconds
Started Jul 22 06:04:53 PM PDT 24
Finished Jul 22 06:17:18 PM PDT 24
Peak memory 201184 kb
Host smart-9590e921-227a-4550-a422-4b5d23c26827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652480704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3652480704
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.4276471197
Short name T644
Test name
Test status
Simulation time 489254891564 ps
CPU time 1026.25 seconds
Started Jul 22 06:04:50 PM PDT 24
Finished Jul 22 06:21:57 PM PDT 24
Peak memory 201192 kb
Host smart-98d5a2f0-941e-427c-b12b-205c917dda48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276471197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.4276471197
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1087162531
Short name T25
Test name
Test status
Simulation time 595511319995 ps
CPU time 364.21 seconds
Started Jul 22 06:05:03 PM PDT 24
Finished Jul 22 06:11:08 PM PDT 24
Peak memory 201272 kb
Host smart-1b164500-848e-4bdf-9c33-90ee663b2f32
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087162531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1087162531
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3456136771
Short name T784
Test name
Test status
Simulation time 40658848076 ps
CPU time 68.26 seconds
Started Jul 22 06:06:01 PM PDT 24
Finished Jul 22 06:07:10 PM PDT 24
Peak memory 201056 kb
Host smart-aee49b45-ee0e-4015-b13c-35f7cd944da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456136771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3456136771
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1977941785
Short name T584
Test name
Test status
Simulation time 3982716048 ps
CPU time 5.58 seconds
Started Jul 22 06:04:47 PM PDT 24
Finished Jul 22 06:04:53 PM PDT 24
Peak memory 201012 kb
Host smart-c10e1716-d46a-45ef-9402-113ef9fb4209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977941785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1977941785
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.119826718
Short name T634
Test name
Test status
Simulation time 5710087897 ps
CPU time 4.05 seconds
Started Jul 22 06:04:48 PM PDT 24
Finished Jul 22 06:04:52 PM PDT 24
Peak memory 201064 kb
Host smart-071acb47-26fc-4b6d-92d5-8bc06521961b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119826718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.119826718
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2803032908
Short name T292
Test name
Test status
Simulation time 171022634504 ps
CPU time 107.81 seconds
Started Jul 22 06:04:48 PM PDT 24
Finished Jul 22 06:06:37 PM PDT 24
Peak memory 201188 kb
Host smart-abd05dc3-db1b-450c-a8e3-1355fc906dbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803032908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2803032908
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1880082428
Short name T365
Test name
Test status
Simulation time 373038389 ps
CPU time 0.81 seconds
Started Jul 22 06:06:01 PM PDT 24
Finished Jul 22 06:06:03 PM PDT 24
Peak memory 201020 kb
Host smart-79124932-9aae-4638-a312-592da258e787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880082428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1880082428
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.191429624
Short name T761
Test name
Test status
Simulation time 388133716162 ps
CPU time 457.73 seconds
Started Jul 22 06:04:49 PM PDT 24
Finished Jul 22 06:12:28 PM PDT 24
Peak memory 201116 kb
Host smart-caaccacf-7842-4332-8cf8-e7aa383104ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191429624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.191429624
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.281635573
Short name T315
Test name
Test status
Simulation time 491057218451 ps
CPU time 1204.94 seconds
Started Jul 22 06:04:49 PM PDT 24
Finished Jul 22 06:24:55 PM PDT 24
Peak memory 201196 kb
Host smart-6a4cb916-0470-42ac-9f24-a6fca11ce4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281635573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.281635573
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1568030407
Short name T375
Test name
Test status
Simulation time 165149019910 ps
CPU time 99.68 seconds
Started Jul 22 06:04:57 PM PDT 24
Finished Jul 22 06:06:37 PM PDT 24
Peak memory 201156 kb
Host smart-3ff8afce-2bca-4649-accd-365cdc681743
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568030407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1568030407
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2923364837
Short name T786
Test name
Test status
Simulation time 327733414645 ps
CPU time 765.07 seconds
Started Jul 22 06:04:50 PM PDT 24
Finished Jul 22 06:17:36 PM PDT 24
Peak memory 201244 kb
Host smart-484f1526-d4d9-43af-9761-fdefdc1db1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923364837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2923364837
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.331840670
Short name T418
Test name
Test status
Simulation time 164409717777 ps
CPU time 182.65 seconds
Started Jul 22 06:06:01 PM PDT 24
Finished Jul 22 06:09:04 PM PDT 24
Peak memory 201224 kb
Host smart-1dd8ef5d-8d00-4c10-bc10-0002875effe4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=331840670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.331840670
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.649582935
Short name T759
Test name
Test status
Simulation time 369786383438 ps
CPU time 127.56 seconds
Started Jul 22 06:04:49 PM PDT 24
Finished Jul 22 06:06:58 PM PDT 24
Peak memory 201180 kb
Host smart-241e1f51-8cdb-40f9-babb-b2d1d5fe363c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649582935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.649582935
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1244769776
Short name T635
Test name
Test status
Simulation time 204006591366 ps
CPU time 111.69 seconds
Started Jul 22 06:04:46 PM PDT 24
Finished Jul 22 06:06:38 PM PDT 24
Peak memory 201288 kb
Host smart-8a425008-0283-421a-a65f-c3a440591c2f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244769776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1244769776
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1826882612
Short name T219
Test name
Test status
Simulation time 95764974648 ps
CPU time 453.39 seconds
Started Jul 22 06:04:52 PM PDT 24
Finished Jul 22 06:12:26 PM PDT 24
Peak memory 201884 kb
Host smart-ee3616f0-e856-432a-aaf3-24b7dbaaab66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826882612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1826882612
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.4046798
Short name T359
Test name
Test status
Simulation time 34121824785 ps
CPU time 78.55 seconds
Started Jul 22 06:04:49 PM PDT 24
Finished Jul 22 06:06:09 PM PDT 24
Peak memory 201108 kb
Host smart-4afae5c5-5135-4815-a0ad-1327b94cb1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.4046798
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2284090911
Short name T488
Test name
Test status
Simulation time 3720575583 ps
CPU time 2.87 seconds
Started Jul 22 06:04:53 PM PDT 24
Finished Jul 22 06:04:57 PM PDT 24
Peak memory 201264 kb
Host smart-a7c256c0-3dcd-423d-834e-6b01f8a3e18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284090911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2284090911
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.960547889
Short name T709
Test name
Test status
Simulation time 6061716170 ps
CPU time 4.09 seconds
Started Jul 22 06:04:49 PM PDT 24
Finished Jul 22 06:04:55 PM PDT 24
Peak memory 201064 kb
Host smart-98aeb7b5-1e61-465b-8363-1b10d2205224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960547889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.960547889
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3644255290
Short name T46
Test name
Test status
Simulation time 30380016171 ps
CPU time 67.75 seconds
Started Jul 22 06:05:12 PM PDT 24
Finished Jul 22 06:06:21 PM PDT 24
Peak memory 201064 kb
Host smart-1c8f5d25-2567-4940-bc58-8238103bc884
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644255290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3644255290
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.4002280326
Short name T52
Test name
Test status
Simulation time 172948752305 ps
CPU time 195.95 seconds
Started Jul 22 06:04:56 PM PDT 24
Finished Jul 22 06:08:13 PM PDT 24
Peak memory 218204 kb
Host smart-7bcf3ebe-eaf4-4474-bd25-82b4c25a8976
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002280326 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.4002280326
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.591996683
Short name T660
Test name
Test status
Simulation time 432682049 ps
CPU time 0.89 seconds
Started Jul 22 06:04:54 PM PDT 24
Finished Jul 22 06:04:56 PM PDT 24
Peak memory 201032 kb
Host smart-62a72d65-42e1-491b-b822-899cd2e5d0b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591996683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.591996683
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1994320200
Short name T706
Test name
Test status
Simulation time 163518322894 ps
CPU time 29.84 seconds
Started Jul 22 06:04:47 PM PDT 24
Finished Jul 22 06:05:18 PM PDT 24
Peak memory 201164 kb
Host smart-7ca5bf23-7e40-4fab-9730-7ffaadf4b2bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994320200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1994320200
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1347718231
Short name T579
Test name
Test status
Simulation time 329964893596 ps
CPU time 793.55 seconds
Started Jul 22 06:05:10 PM PDT 24
Finished Jul 22 06:18:24 PM PDT 24
Peak memory 201280 kb
Host smart-5cac3bc7-00f2-4cad-ab4a-f083bacefda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347718231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1347718231
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2474556400
Short name T498
Test name
Test status
Simulation time 492925223573 ps
CPU time 287.15 seconds
Started Jul 22 06:04:50 PM PDT 24
Finished Jul 22 06:09:39 PM PDT 24
Peak memory 201172 kb
Host smart-81208220-52de-4aa6-ac3c-806756cbeaa5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474556400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2474556400
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.986508558
Short name T597
Test name
Test status
Simulation time 366729966597 ps
CPU time 166.61 seconds
Started Jul 22 06:04:56 PM PDT 24
Finished Jul 22 06:07:43 PM PDT 24
Peak memory 201236 kb
Host smart-7dd325ca-fb58-45be-9ec1-b1112a38820c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986508558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.986508558
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.4001851082
Short name T361
Test name
Test status
Simulation time 211657217243 ps
CPU time 91.85 seconds
Started Jul 22 06:04:51 PM PDT 24
Finished Jul 22 06:06:24 PM PDT 24
Peak memory 201188 kb
Host smart-5398f55d-1a64-485b-a1d6-4c985f4eb40c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001851082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.4001851082
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.561329099
Short name T27
Test name
Test status
Simulation time 122722898299 ps
CPU time 627.05 seconds
Started Jul 22 06:05:54 PM PDT 24
Finished Jul 22 06:16:22 PM PDT 24
Peak memory 201640 kb
Host smart-21d17d36-e4ed-42b6-aec1-d386e5d1d9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561329099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.561329099
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2558310823
Short name T410
Test name
Test status
Simulation time 38431801668 ps
CPU time 41.23 seconds
Started Jul 22 06:04:56 PM PDT 24
Finished Jul 22 06:05:38 PM PDT 24
Peak memory 201056 kb
Host smart-0ad1b19f-0628-4299-b073-f78bb38ee7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558310823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2558310823
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2369123584
Short name T108
Test name
Test status
Simulation time 5478954187 ps
CPU time 4.2 seconds
Started Jul 22 06:04:56 PM PDT 24
Finished Jul 22 06:05:01 PM PDT 24
Peak memory 201072 kb
Host smart-2e0c49fb-32ff-4836-a51f-d0194af636f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369123584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2369123584
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.267928296
Short name T419
Test name
Test status
Simulation time 6026636705 ps
CPU time 8.44 seconds
Started Jul 22 06:04:51 PM PDT 24
Finished Jul 22 06:05:01 PM PDT 24
Peak memory 201132 kb
Host smart-1f4017dc-83a2-41e4-954a-0a4e2fb38155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267928296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.267928296
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1404406098
Short name T694
Test name
Test status
Simulation time 455527818066 ps
CPU time 568.21 seconds
Started Jul 22 06:04:54 PM PDT 24
Finished Jul 22 06:14:24 PM PDT 24
Peak memory 209800 kb
Host smart-d7bf0424-de60-4d11-8377-c5204ab3de5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404406098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1404406098
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2037930011
Short name T574
Test name
Test status
Simulation time 242934299433 ps
CPU time 142.17 seconds
Started Jul 22 06:04:58 PM PDT 24
Finished Jul 22 06:07:21 PM PDT 24
Peak memory 209944 kb
Host smart-f13f56bd-240b-4b32-8bdb-5e9235b1fb3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037930011 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2037930011
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2216554980
Short name T103
Test name
Test status
Simulation time 453302244 ps
CPU time 1.18 seconds
Started Jul 22 06:04:53 PM PDT 24
Finished Jul 22 06:04:55 PM PDT 24
Peak memory 200964 kb
Host smart-2da06a4a-bb67-4783-92e3-e096992c6764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216554980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2216554980
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3349728910
Short name T56
Test name
Test status
Simulation time 330287724411 ps
CPU time 54.69 seconds
Started Jul 22 06:04:53 PM PDT 24
Finished Jul 22 06:05:49 PM PDT 24
Peak memory 201208 kb
Host smart-7dbdd442-acbb-4dae-aa8e-3c7f449f0288
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349728910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3349728910
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1123071846
Short name T171
Test name
Test status
Simulation time 170859362372 ps
CPU time 99.13 seconds
Started Jul 22 06:04:53 PM PDT 24
Finished Jul 22 06:06:34 PM PDT 24
Peak memory 201160 kb
Host smart-2102df2b-fadf-4c3d-a3ea-b7268ea1dfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123071846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1123071846
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1939578896
Short name T512
Test name
Test status
Simulation time 166026270739 ps
CPU time 195.71 seconds
Started Jul 22 06:04:56 PM PDT 24
Finished Jul 22 06:08:13 PM PDT 24
Peak memory 201072 kb
Host smart-cb854a09-3d7e-4e3e-8d80-ad3a5252753e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939578896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1939578896
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2597303245
Short name T691
Test name
Test status
Simulation time 482455814966 ps
CPU time 1126.1 seconds
Started Jul 22 06:04:56 PM PDT 24
Finished Jul 22 06:23:43 PM PDT 24
Peak memory 201104 kb
Host smart-c16a6141-914d-41e5-9af8-7a027f7df9d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597303245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2597303245
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3785772988
Short name T224
Test name
Test status
Simulation time 488073743119 ps
CPU time 547.47 seconds
Started Jul 22 06:04:49 PM PDT 24
Finished Jul 22 06:13:58 PM PDT 24
Peak memory 201316 kb
Host smart-55677d38-7494-4321-9285-d62da887783d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785772988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3785772988
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2812307145
Short name T183
Test name
Test status
Simulation time 500752814291 ps
CPU time 317.92 seconds
Started Jul 22 06:04:52 PM PDT 24
Finished Jul 22 06:10:11 PM PDT 24
Peak memory 201224 kb
Host smart-2bc48f34-39ff-4a7f-a6d0-5644c5b6f8f7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812307145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2812307145
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.4172516053
Short name T792
Test name
Test status
Simulation time 395252053291 ps
CPU time 933.16 seconds
Started Jul 22 06:04:52 PM PDT 24
Finished Jul 22 06:20:26 PM PDT 24
Peak memory 201280 kb
Host smart-66a985fd-a379-4cfc-9f70-e93a93edff6b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172516053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.4172516053
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.476659565
Short name T670
Test name
Test status
Simulation time 75185795306 ps
CPU time 304.55 seconds
Started Jul 22 06:05:16 PM PDT 24
Finished Jul 22 06:10:21 PM PDT 24
Peak memory 201664 kb
Host smart-de6b107f-4dcb-4708-9c41-9dd77027f8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476659565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.476659565
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3249419524
Short name T715
Test name
Test status
Simulation time 40398037923 ps
CPU time 49.25 seconds
Started Jul 22 06:04:59 PM PDT 24
Finished Jul 22 06:05:48 PM PDT 24
Peak memory 201072 kb
Host smart-ec532f7c-5158-4fe7-8f2a-8462dcff9ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249419524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3249419524
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1843342108
Short name T9
Test name
Test status
Simulation time 3390707842 ps
CPU time 4.67 seconds
Started Jul 22 06:06:09 PM PDT 24
Finished Jul 22 06:06:14 PM PDT 24
Peak memory 200960 kb
Host smart-72103c10-167e-4c8a-90e0-a9cd7920ff34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843342108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1843342108
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.271287975
Short name T29
Test name
Test status
Simulation time 6078301006 ps
CPU time 2.73 seconds
Started Jul 22 06:04:51 PM PDT 24
Finished Jul 22 06:04:55 PM PDT 24
Peak memory 201132 kb
Host smart-344a3599-623c-41aa-b3a8-b883e2eb81ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271287975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.271287975
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2374282539
Short name T787
Test name
Test status
Simulation time 521265773 ps
CPU time 0.92 seconds
Started Jul 22 06:04:52 PM PDT 24
Finished Jul 22 06:04:54 PM PDT 24
Peak memory 201000 kb
Host smart-85111864-12f4-47dc-a1f0-de568b07b778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374282539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2374282539
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1643681974
Short name T299
Test name
Test status
Simulation time 337703234754 ps
CPU time 702.87 seconds
Started Jul 22 06:04:51 PM PDT 24
Finished Jul 22 06:16:35 PM PDT 24
Peak memory 201196 kb
Host smart-da3c7ca2-3e64-4ce3-bd74-2563f4b7312f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643681974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1643681974
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1543775602
Short name T661
Test name
Test status
Simulation time 327111388119 ps
CPU time 221.96 seconds
Started Jul 22 06:04:53 PM PDT 24
Finished Jul 22 06:08:36 PM PDT 24
Peak memory 201252 kb
Host smart-9cca1799-bf87-4b5b-9b9c-b1f59979d152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543775602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1543775602
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3689243728
Short name T383
Test name
Test status
Simulation time 169072777698 ps
CPU time 422.8 seconds
Started Jul 22 06:04:53 PM PDT 24
Finished Jul 22 06:11:57 PM PDT 24
Peak memory 201156 kb
Host smart-8151993e-3d19-42e4-976c-a1586a9d18a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689243728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3689243728
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2734942785
Short name T170
Test name
Test status
Simulation time 502351165120 ps
CPU time 170.63 seconds
Started Jul 22 06:04:56 PM PDT 24
Finished Jul 22 06:07:47 PM PDT 24
Peak memory 201284 kb
Host smart-8b721d4b-a135-4913-9fb4-c6b36bbe5eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734942785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2734942785
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2135557873
Short name T129
Test name
Test status
Simulation time 329991840380 ps
CPU time 167.97 seconds
Started Jul 22 06:04:52 PM PDT 24
Finished Jul 22 06:07:41 PM PDT 24
Peak memory 201240 kb
Host smart-bb7b5092-8a6a-430a-a8ef-e234e77c1701
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135557873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2135557873
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3253401868
Short name T580
Test name
Test status
Simulation time 528841039985 ps
CPU time 148.7 seconds
Started Jul 22 06:04:52 PM PDT 24
Finished Jul 22 06:07:22 PM PDT 24
Peak memory 201224 kb
Host smart-05b78438-2621-4ff9-aedd-caca227e493b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253401868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3253401868
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3563902490
Short name T476
Test name
Test status
Simulation time 119682440796 ps
CPU time 483.55 seconds
Started Jul 22 06:04:57 PM PDT 24
Finished Jul 22 06:13:02 PM PDT 24
Peak memory 201696 kb
Host smart-beb10327-58ad-4bb5-8e65-a1c9bbede030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563902490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3563902490
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3613912886
Short name T58
Test name
Test status
Simulation time 36470175659 ps
CPU time 19.96 seconds
Started Jul 22 06:04:54 PM PDT 24
Finished Jul 22 06:05:15 PM PDT 24
Peak memory 201036 kb
Host smart-c8f0b5a4-ab03-4891-99aa-9e82b5d26a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613912886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3613912886
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2299662490
Short name T462
Test name
Test status
Simulation time 3430914165 ps
CPU time 7.25 seconds
Started Jul 22 06:04:55 PM PDT 24
Finished Jul 22 06:05:03 PM PDT 24
Peak memory 201020 kb
Host smart-364eb3ce-e4cd-40aa-a539-81e6fb73d152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299662490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2299662490
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1090573452
Short name T116
Test name
Test status
Simulation time 5820763685 ps
CPU time 15.32 seconds
Started Jul 22 06:04:53 PM PDT 24
Finished Jul 22 06:05:10 PM PDT 24
Peak memory 201024 kb
Host smart-937b73ce-0819-44f8-9a47-3894e081c1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090573452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1090573452
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3845757341
Short name T357
Test name
Test status
Simulation time 251658398016 ps
CPU time 396.96 seconds
Started Jul 22 06:05:54 PM PDT 24
Finished Jul 22 06:12:32 PM PDT 24
Peak memory 209824 kb
Host smart-6c19bf22-e8d4-4bab-a77d-e9d18435f024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845757341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3845757341
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.4269019504
Short name T701
Test name
Test status
Simulation time 95104676438 ps
CPU time 146.32 seconds
Started Jul 22 06:04:59 PM PDT 24
Finished Jul 22 06:07:25 PM PDT 24
Peak memory 210004 kb
Host smart-ae33f718-687a-47a4-a7ab-afc8a9a66d27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269019504 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.4269019504
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.176859324
Short name T415
Test name
Test status
Simulation time 492105810 ps
CPU time 1.23 seconds
Started Jul 22 06:04:56 PM PDT 24
Finished Jul 22 06:04:58 PM PDT 24
Peak memory 200796 kb
Host smart-f2cfe39f-e102-4706-88ec-4bd384ea5996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176859324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.176859324
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3546275757
Short name T185
Test name
Test status
Simulation time 165024514707 ps
CPU time 133.35 seconds
Started Jul 22 06:04:55 PM PDT 24
Finished Jul 22 06:07:09 PM PDT 24
Peak memory 201180 kb
Host smart-752391d8-9aa6-41d2-93db-12ce052832bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546275757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3546275757
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2078596344
Short name T689
Test name
Test status
Simulation time 329821684519 ps
CPU time 209.26 seconds
Started Jul 22 06:04:52 PM PDT 24
Finished Jul 22 06:08:23 PM PDT 24
Peak memory 201168 kb
Host smart-36cd8fa2-89cb-4fa6-a765-f40dc31d6991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078596344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2078596344
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3651564346
Short name T326
Test name
Test status
Simulation time 327235624284 ps
CPU time 695.16 seconds
Started Jul 22 06:04:52 PM PDT 24
Finished Jul 22 06:16:29 PM PDT 24
Peak memory 201212 kb
Host smart-9a4e9ca9-cebd-466d-9e4f-bef6c561d676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651564346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3651564346
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1448875461
Short name T392
Test name
Test status
Simulation time 168856446422 ps
CPU time 231.69 seconds
Started Jul 22 06:04:53 PM PDT 24
Finished Jul 22 06:08:46 PM PDT 24
Peak memory 201224 kb
Host smart-db7b841a-f77a-40ef-97b0-1256a6cfd405
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448875461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1448875461
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3880802390
Short name T518
Test name
Test status
Simulation time 328901651327 ps
CPU time 799.24 seconds
Started Jul 22 06:05:16 PM PDT 24
Finished Jul 22 06:18:36 PM PDT 24
Peak memory 201276 kb
Host smart-2ccf1202-6524-44bf-98fa-eb5fd4c40c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880802390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3880802390
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3946050683
Short name T132
Test name
Test status
Simulation time 163446005599 ps
CPU time 352.28 seconds
Started Jul 22 06:04:59 PM PDT 24
Finished Jul 22 06:10:52 PM PDT 24
Peak memory 201204 kb
Host smart-de0f6d96-c9ba-4d48-a06c-a7f6d6ce85f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946050683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3946050683
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1177715936
Short name T765
Test name
Test status
Simulation time 208142706216 ps
CPU time 31.3 seconds
Started Jul 22 06:04:52 PM PDT 24
Finished Jul 22 06:05:25 PM PDT 24
Peak memory 201192 kb
Host smart-d9926f2f-7e33-4759-9f93-0d9face6168f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177715936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1177715936
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1121158333
Short name T631
Test name
Test status
Simulation time 74955548528 ps
CPU time 364.27 seconds
Started Jul 22 06:04:59 PM PDT 24
Finished Jul 22 06:11:03 PM PDT 24
Peak memory 201676 kb
Host smart-64b685d0-8a6e-421a-b50b-39f5cd3cea45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121158333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1121158333
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.3676488257
Short name T791
Test name
Test status
Simulation time 29656832733 ps
CPU time 70.23 seconds
Started Jul 22 06:04:54 PM PDT 24
Finished Jul 22 06:06:05 PM PDT 24
Peak memory 201080 kb
Host smart-76ac54bd-7dd2-474f-8e7f-f67ec1536b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676488257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.3676488257
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.871490638
Short name T653
Test name
Test status
Simulation time 3226780694 ps
CPU time 8.13 seconds
Started Jul 22 06:04:50 PM PDT 24
Finished Jul 22 06:04:59 PM PDT 24
Peak memory 201056 kb
Host smart-747d086a-4452-42e1-9645-3f930c29e20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871490638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.871490638
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.121740670
Short name T10
Test name
Test status
Simulation time 6095564260 ps
CPU time 4.62 seconds
Started Jul 22 06:04:54 PM PDT 24
Finished Jul 22 06:05:00 PM PDT 24
Peak memory 201076 kb
Host smart-820a0fe7-9911-43ec-9ffc-36564b813439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121740670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.121740670
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3171296016
Short name T541
Test name
Test status
Simulation time 12326496175 ps
CPU time 5.59 seconds
Started Jul 22 06:04:52 PM PDT 24
Finished Jul 22 06:04:59 PM PDT 24
Peak memory 201196 kb
Host smart-2706687a-57e8-4d22-b54d-b228c5509f22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171296016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3171296016
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3145097493
Short name T388
Test name
Test status
Simulation time 490095905 ps
CPU time 0.87 seconds
Started Jul 22 06:05:07 PM PDT 24
Finished Jul 22 06:05:09 PM PDT 24
Peak memory 201020 kb
Host smart-bd6fc4b2-1db3-477b-9572-750fd2b04417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145097493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3145097493
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2477670581
Short name T755
Test name
Test status
Simulation time 166339960811 ps
CPU time 355.6 seconds
Started Jul 22 06:05:41 PM PDT 24
Finished Jul 22 06:11:38 PM PDT 24
Peak memory 201228 kb
Host smart-23d23340-6541-4ab5-9385-34cb6dd6592b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477670581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2477670581
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3220246767
Short name T57
Test name
Test status
Simulation time 156619182874 ps
CPU time 348.73 seconds
Started Jul 22 06:05:41 PM PDT 24
Finished Jul 22 06:11:32 PM PDT 24
Peak memory 201296 kb
Host smart-6eef9ff2-369e-4c83-9d27-a1efa4ac53a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220246767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3220246767
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3532134468
Short name T203
Test name
Test status
Simulation time 326349981417 ps
CPU time 709.27 seconds
Started Jul 22 06:04:56 PM PDT 24
Finished Jul 22 06:16:46 PM PDT 24
Peak memory 201220 kb
Host smart-d53dc98a-fc5d-4074-84b8-db8d43956544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532134468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3532134468
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3357230587
Short name T3
Test name
Test status
Simulation time 325749403084 ps
CPU time 761.57 seconds
Started Jul 22 06:04:54 PM PDT 24
Finished Jul 22 06:17:37 PM PDT 24
Peak memory 201188 kb
Host smart-d16a1dff-c029-4e55-a167-32aee0bd15ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357230587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3357230587
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2919213480
Short name T464
Test name
Test status
Simulation time 334842346628 ps
CPU time 213.63 seconds
Started Jul 22 06:05:04 PM PDT 24
Finished Jul 22 06:08:39 PM PDT 24
Peak memory 201272 kb
Host smart-10dd3aac-74aa-4c58-8210-ac782e5f69af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919213480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2919213480
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1517082069
Short name T391
Test name
Test status
Simulation time 497830639692 ps
CPU time 527.74 seconds
Started Jul 22 06:05:03 PM PDT 24
Finished Jul 22 06:13:51 PM PDT 24
Peak memory 201220 kb
Host smart-e59e7330-8ca7-4a19-9234-b89efa946d91
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517082069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1517082069
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3858826717
Short name T290
Test name
Test status
Simulation time 348843290665 ps
CPU time 420.77 seconds
Started Jul 22 06:04:58 PM PDT 24
Finished Jul 22 06:11:59 PM PDT 24
Peak memory 201180 kb
Host smart-ea3dbff4-cf36-4cd2-9a5b-3e79411921d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858826717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3858826717
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1313746251
Short name T602
Test name
Test status
Simulation time 600924307949 ps
CPU time 1397.48 seconds
Started Jul 22 06:04:57 PM PDT 24
Finished Jul 22 06:28:15 PM PDT 24
Peak memory 201164 kb
Host smart-928fb7a4-6696-4fda-a606-43b1973616d3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313746251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1313746251
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2517468235
Short name T708
Test name
Test status
Simulation time 88370814505 ps
CPU time 427.85 seconds
Started Jul 22 06:04:52 PM PDT 24
Finished Jul 22 06:12:01 PM PDT 24
Peak memory 201668 kb
Host smart-b9c7d441-207c-4448-b01c-1dbd0bbf30e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517468235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2517468235
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.124290681
Short name T662
Test name
Test status
Simulation time 25907353327 ps
CPU time 63.05 seconds
Started Jul 22 06:04:53 PM PDT 24
Finished Jul 22 06:05:57 PM PDT 24
Peak memory 201052 kb
Host smart-7647830e-0b0e-4cc6-b9bd-df1381fa62f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124290681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.124290681
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2357154613
Short name T677
Test name
Test status
Simulation time 3041757622 ps
CPU time 1.78 seconds
Started Jul 22 06:04:57 PM PDT 24
Finished Jul 22 06:04:59 PM PDT 24
Peak memory 201024 kb
Host smart-914f21d3-aaa8-4591-b5c4-4de551314e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357154613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2357154613
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1776996045
Short name T778
Test name
Test status
Simulation time 5968624652 ps
CPU time 15.64 seconds
Started Jul 22 06:04:53 PM PDT 24
Finished Jul 22 06:05:10 PM PDT 24
Peak memory 201088 kb
Host smart-d345e4e5-acd5-4159-98d2-5b364b826a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776996045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1776996045
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2325262462
Short name T777
Test name
Test status
Simulation time 325541366213 ps
CPU time 780.59 seconds
Started Jul 22 06:04:54 PM PDT 24
Finished Jul 22 06:17:56 PM PDT 24
Peak memory 201164 kb
Host smart-d4763d36-455a-4bf9-9218-6213873e0c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325262462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2325262462
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1454079420
Short name T435
Test name
Test status
Simulation time 82611424821 ps
CPU time 158.27 seconds
Started Jul 22 06:04:57 PM PDT 24
Finished Jul 22 06:07:36 PM PDT 24
Peak memory 209960 kb
Host smart-ac54d229-b43d-4228-9e33-7415b59ea108
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454079420 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1454079420
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3245560007
Short name T109
Test name
Test status
Simulation time 416473928 ps
CPU time 0.87 seconds
Started Jul 22 06:05:04 PM PDT 24
Finished Jul 22 06:05:05 PM PDT 24
Peak memory 200968 kb
Host smart-f626eec2-a1db-460d-8371-0c788fcc2d96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245560007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3245560007
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1373733936
Short name T526
Test name
Test status
Simulation time 164157058655 ps
CPU time 380.94 seconds
Started Jul 22 06:04:58 PM PDT 24
Finished Jul 22 06:11:20 PM PDT 24
Peak memory 201224 kb
Host smart-e54de473-7b67-46f2-936b-f42175c48ea7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373733936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1373733936
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2547851891
Short name T263
Test name
Test status
Simulation time 176539659944 ps
CPU time 191.23 seconds
Started Jul 22 06:04:57 PM PDT 24
Finished Jul 22 06:08:09 PM PDT 24
Peak memory 201188 kb
Host smart-09b709cd-036a-48dc-b693-1e23ab82f19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547851891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2547851891
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.670659333
Short name T187
Test name
Test status
Simulation time 162909641292 ps
CPU time 236.49 seconds
Started Jul 22 06:04:55 PM PDT 24
Finished Jul 22 06:08:52 PM PDT 24
Peak memory 201184 kb
Host smart-18a3e607-0e7b-4dc3-a786-29d5f4164eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670659333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.670659333
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2322810865
Short name T727
Test name
Test status
Simulation time 162100814357 ps
CPU time 168.54 seconds
Started Jul 22 06:06:08 PM PDT 24
Finished Jul 22 06:08:57 PM PDT 24
Peak memory 201248 kb
Host smart-7d96b0f0-4c38-420e-9f0e-4b1b0ebd2cd5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322810865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2322810865
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3953747096
Short name T647
Test name
Test status
Simulation time 162459151007 ps
CPU time 320.66 seconds
Started Jul 22 06:04:58 PM PDT 24
Finished Jul 22 06:10:19 PM PDT 24
Peak memory 201176 kb
Host smart-02d6b8db-a55c-4226-8ed3-42ea282e2b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953747096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3953747096
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.691245483
Short name T690
Test name
Test status
Simulation time 498304508826 ps
CPU time 79.78 seconds
Started Jul 22 06:05:00 PM PDT 24
Finished Jul 22 06:06:21 PM PDT 24
Peak memory 200440 kb
Host smart-0233a2ec-f875-4eac-9e14-bdc6c34cba1a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=691245483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.691245483
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3494362470
Short name T680
Test name
Test status
Simulation time 394578313093 ps
CPU time 209.33 seconds
Started Jul 22 06:04:59 PM PDT 24
Finished Jul 22 06:08:29 PM PDT 24
Peak memory 201220 kb
Host smart-25739d91-6cc7-4073-a4dd-d19edb483a59
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494362470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3494362470
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.753851719
Short name T489
Test name
Test status
Simulation time 115632363972 ps
CPU time 349.52 seconds
Started Jul 22 06:04:59 PM PDT 24
Finished Jul 22 06:10:49 PM PDT 24
Peak memory 201668 kb
Host smart-7e7679bb-b7b7-4e1f-aa5e-4076ab006a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753851719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.753851719
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1100796371
Short name T437
Test name
Test status
Simulation time 40605443313 ps
CPU time 20.61 seconds
Started Jul 22 06:04:55 PM PDT 24
Finished Jul 22 06:05:16 PM PDT 24
Peak memory 201012 kb
Host smart-a389c91c-0c40-4da8-bfcc-358813b727b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100796371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1100796371
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3335123321
Short name T688
Test name
Test status
Simulation time 4226944446 ps
CPU time 3.12 seconds
Started Jul 22 06:05:12 PM PDT 24
Finished Jul 22 06:05:16 PM PDT 24
Peak memory 201052 kb
Host smart-45594cf0-77c3-4448-9759-fc26e59e19ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335123321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3335123321
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.4033338750
Short name T546
Test name
Test status
Simulation time 5953855086 ps
CPU time 13.36 seconds
Started Jul 22 06:04:58 PM PDT 24
Finished Jul 22 06:05:12 PM PDT 24
Peak memory 201044 kb
Host smart-590b7410-ad80-4bfb-b8df-7200a114cef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033338750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.4033338750
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1129273554
Short name T322
Test name
Test status
Simulation time 335086376593 ps
CPU time 251.05 seconds
Started Jul 22 06:04:57 PM PDT 24
Finished Jul 22 06:09:09 PM PDT 24
Peak memory 201260 kb
Host smart-dbff4cc2-89f0-4b61-a286-37121aca66cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129273554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1129273554
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1741723280
Short name T494
Test name
Test status
Simulation time 68499508583 ps
CPU time 160.59 seconds
Started Jul 22 06:05:00 PM PDT 24
Finished Jul 22 06:07:41 PM PDT 24
Peak memory 209252 kb
Host smart-af246c24-a1a7-4791-9008-b6049db27412
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741723280 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1741723280
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3255658635
Short name T697
Test name
Test status
Simulation time 509004075 ps
CPU time 0.82 seconds
Started Jul 22 06:05:01 PM PDT 24
Finished Jul 22 06:05:03 PM PDT 24
Peak memory 201024 kb
Host smart-491a1be2-eea6-473d-aa60-0ec890d607fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255658635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3255658635
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3606083394
Short name T201
Test name
Test status
Simulation time 165149913041 ps
CPU time 177.14 seconds
Started Jul 22 06:05:01 PM PDT 24
Finished Jul 22 06:07:59 PM PDT 24
Peak memory 201172 kb
Host smart-e7602d68-7bc7-4700-b771-01b71a42fbc2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606083394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3606083394
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2420302619
Short name T594
Test name
Test status
Simulation time 355722233105 ps
CPU time 119.3 seconds
Started Jul 22 06:05:03 PM PDT 24
Finished Jul 22 06:07:03 PM PDT 24
Peak memory 201168 kb
Host smart-48ba7f75-1af9-4722-8f4e-644105b70b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420302619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2420302619
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1508712283
Short name T552
Test name
Test status
Simulation time 335160149557 ps
CPU time 171.39 seconds
Started Jul 22 06:05:01 PM PDT 24
Finished Jul 22 06:07:54 PM PDT 24
Peak memory 201264 kb
Host smart-3fbab1da-94ff-4f83-820d-aa06815bf559
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508712283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1508712283
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1971056501
Short name T161
Test name
Test status
Simulation time 481922843244 ps
CPU time 874.9 seconds
Started Jul 22 06:05:09 PM PDT 24
Finished Jul 22 06:19:45 PM PDT 24
Peak memory 201280 kb
Host smart-f7c5b5ca-5eb5-45bd-b328-3b8f003d2952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971056501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1971056501
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.630235502
Short name T561
Test name
Test status
Simulation time 340042312778 ps
CPU time 184.28 seconds
Started Jul 22 06:06:07 PM PDT 24
Finished Jul 22 06:09:12 PM PDT 24
Peak memory 201216 kb
Host smart-6e87b571-0d3a-4a6b-a05a-13931cd8c9e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=630235502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.630235502
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.351024258
Short name T648
Test name
Test status
Simulation time 400721956884 ps
CPU time 937.36 seconds
Started Jul 22 06:05:41 PM PDT 24
Finished Jul 22 06:21:20 PM PDT 24
Peak memory 201236 kb
Host smart-e7304f38-d277-4c22-a096-40659ec07001
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351024258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.351024258
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2273387075
Short name T633
Test name
Test status
Simulation time 102617082351 ps
CPU time 563.78 seconds
Started Jul 22 06:05:07 PM PDT 24
Finished Jul 22 06:14:31 PM PDT 24
Peak memory 201680 kb
Host smart-8d4ddd55-2485-4bc8-b226-e2a5ba9ead8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273387075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2273387075
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.4270562820
Short name T531
Test name
Test status
Simulation time 34517363249 ps
CPU time 39.77 seconds
Started Jul 22 06:05:02 PM PDT 24
Finished Jul 22 06:05:42 PM PDT 24
Peak memory 201116 kb
Host smart-4a926859-2010-49a9-8896-9337b75bd24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270562820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.4270562820
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3756636418
Short name T407
Test name
Test status
Simulation time 3271856143 ps
CPU time 4.7 seconds
Started Jul 22 06:05:20 PM PDT 24
Finished Jul 22 06:05:26 PM PDT 24
Peak memory 201032 kb
Host smart-c8f87f91-7508-49f2-a542-894793451ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756636418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3756636418
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1215630428
Short name T595
Test name
Test status
Simulation time 5719560152 ps
CPU time 13.35 seconds
Started Jul 22 06:05:09 PM PDT 24
Finished Jul 22 06:05:23 PM PDT 24
Peak memory 201040 kb
Host smart-513f89f3-d2aa-4261-89ae-a9a156201c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215630428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1215630428
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3252942281
Short name T12
Test name
Test status
Simulation time 270135951709 ps
CPU time 626.58 seconds
Started Jul 22 06:05:15 PM PDT 24
Finished Jul 22 06:15:42 PM PDT 24
Peak memory 201640 kb
Host smart-17042267-95b1-4a3c-a9be-798ce642ab2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252942281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3252942281
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1766635534
Short name T13
Test name
Test status
Simulation time 18600481507 ps
CPU time 60.82 seconds
Started Jul 22 06:05:12 PM PDT 24
Finished Jul 22 06:06:13 PM PDT 24
Peak memory 215716 kb
Host smart-4b9f17d7-9bbb-40bb-97a2-e1e81fc7c9b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766635534 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1766635534
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1776178157
Short name T397
Test name
Test status
Simulation time 472792616 ps
CPU time 0.91 seconds
Started Jul 22 06:04:39 PM PDT 24
Finished Jul 22 06:04:41 PM PDT 24
Peak memory 201020 kb
Host smart-7c367385-897a-4458-be38-98c16f2c421e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776178157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1776178157
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.4235170978
Short name T196
Test name
Test status
Simulation time 527583840787 ps
CPU time 115.23 seconds
Started Jul 22 06:04:25 PM PDT 24
Finished Jul 22 06:06:20 PM PDT 24
Peak memory 201272 kb
Host smart-bad01f36-6176-488b-bc6b-1c29f9442cdf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235170978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.4235170978
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3768872155
Short name T265
Test name
Test status
Simulation time 167146442192 ps
CPU time 100.35 seconds
Started Jul 22 06:04:25 PM PDT 24
Finished Jul 22 06:06:06 PM PDT 24
Peak memory 201168 kb
Host smart-e1726785-1a98-4971-a458-c380ac0e3295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768872155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3768872155
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2955967642
Short name T228
Test name
Test status
Simulation time 322042861294 ps
CPU time 149.9 seconds
Started Jul 22 06:04:29 PM PDT 24
Finished Jul 22 06:06:59 PM PDT 24
Peak memory 201168 kb
Host smart-6778c21c-5312-4772-acdf-be05ce5b694e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955967642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2955967642
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1719310325
Short name T711
Test name
Test status
Simulation time 488285060238 ps
CPU time 1188.87 seconds
Started Jul 22 06:07:41 PM PDT 24
Finished Jul 22 06:27:31 PM PDT 24
Peak memory 201212 kb
Host smart-be6ce4f8-d734-4d5f-b69a-9da43d03a188
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719310325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1719310325
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.250827752
Short name T469
Test name
Test status
Simulation time 163245498422 ps
CPU time 371.92 seconds
Started Jul 22 06:04:38 PM PDT 24
Finished Jul 22 06:10:50 PM PDT 24
Peak memory 201236 kb
Host smart-61ff4ac2-fea6-4841-af11-86ac40e36ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250827752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.250827752
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.685337844
Short name T474
Test name
Test status
Simulation time 162373064463 ps
CPU time 179.98 seconds
Started Jul 22 06:04:27 PM PDT 24
Finished Jul 22 06:07:27 PM PDT 24
Peak memory 201208 kb
Host smart-cc48d49a-070c-4f0c-8f97-4576cb3f0908
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=685337844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.685337844
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.911056741
Short name T618
Test name
Test status
Simulation time 547967479147 ps
CPU time 97.6 seconds
Started Jul 22 06:04:18 PM PDT 24
Finished Jul 22 06:05:56 PM PDT 24
Peak memory 201232 kb
Host smart-6ff40be8-ae91-47da-b244-4937da468861
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911056741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.911056741
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3311287655
Short name T719
Test name
Test status
Simulation time 403687031362 ps
CPU time 176.6 seconds
Started Jul 22 06:04:27 PM PDT 24
Finished Jul 22 06:07:24 PM PDT 24
Peak memory 201196 kb
Host smart-25c870f5-4024-4f7c-8ae6-3b36813078dd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311287655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3311287655
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3304718346
Short name T70
Test name
Test status
Simulation time 106323497133 ps
CPU time 446.01 seconds
Started Jul 22 06:04:24 PM PDT 24
Finished Jul 22 06:11:50 PM PDT 24
Peak memory 201676 kb
Host smart-826f2706-8d6a-44ec-a175-cff82c0a667c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304718346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3304718346
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2197985869
Short name T119
Test name
Test status
Simulation time 29099950850 ps
CPU time 67.2 seconds
Started Jul 22 06:04:21 PM PDT 24
Finished Jul 22 06:05:29 PM PDT 24
Peak memory 201072 kb
Host smart-efbb1ab8-1bee-4436-91ff-7a1a0ece0868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197985869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2197985869
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.843876467
Short name T364
Test name
Test status
Simulation time 3170159424 ps
CPU time 8.94 seconds
Started Jul 22 06:04:22 PM PDT 24
Finished Jul 22 06:04:31 PM PDT 24
Peak memory 201040 kb
Host smart-c4977f40-ef69-47fe-b35b-8f99016da94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843876467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.843876467
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3104679258
Short name T101
Test name
Test status
Simulation time 8558663631 ps
CPU time 6.09 seconds
Started Jul 22 06:04:37 PM PDT 24
Finished Jul 22 06:04:44 PM PDT 24
Peak memory 217976 kb
Host smart-331c0d6c-ea44-48cd-b674-abade81b5e42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104679258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3104679258
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3725980732
Short name T417
Test name
Test status
Simulation time 5877983906 ps
CPU time 9.05 seconds
Started Jul 22 06:04:33 PM PDT 24
Finished Jul 22 06:04:42 PM PDT 24
Peak memory 201064 kb
Host smart-979b31ba-d16b-4503-92a2-63df3b8b3930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725980732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3725980732
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1605576097
Short name T67
Test name
Test status
Simulation time 1805932289139 ps
CPU time 1340.71 seconds
Started Jul 22 06:04:31 PM PDT 24
Finished Jul 22 06:26:52 PM PDT 24
Peak memory 209988 kb
Host smart-ac6cab96-f01c-428c-b1e4-cb4423357009
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605576097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1605576097
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3114354317
Short name T505
Test name
Test status
Simulation time 452983644 ps
CPU time 1.16 seconds
Started Jul 22 06:07:43 PM PDT 24
Finished Jul 22 06:07:46 PM PDT 24
Peak memory 201024 kb
Host smart-ad944946-fc93-46c0-bae2-6c342ad2bd2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114354317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3114354317
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.4197776904
Short name T732
Test name
Test status
Simulation time 492568260898 ps
CPU time 203.66 seconds
Started Jul 22 06:07:43 PM PDT 24
Finished Jul 22 06:11:08 PM PDT 24
Peak memory 201232 kb
Host smart-9167b30b-6216-4bd6-b729-aa6e7076e75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197776904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.4197776904
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2520674226
Short name T471
Test name
Test status
Simulation time 330890220926 ps
CPU time 190.2 seconds
Started Jul 22 06:05:16 PM PDT 24
Finished Jul 22 06:08:27 PM PDT 24
Peak memory 201236 kb
Host smart-ca0c0c87-01b7-4425-9bbf-e4abf5e0c20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520674226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2520674226
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1930400027
Short name T637
Test name
Test status
Simulation time 324850966860 ps
CPU time 398.74 seconds
Started Jul 22 06:05:41 PM PDT 24
Finished Jul 22 06:12:21 PM PDT 24
Peak memory 201212 kb
Host smart-82381a3e-be8e-4502-94d1-bc03bab8457b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930400027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1930400027
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3065983286
Short name T268
Test name
Test status
Simulation time 489474024447 ps
CPU time 298.28 seconds
Started Jul 22 06:05:04 PM PDT 24
Finished Jul 22 06:10:03 PM PDT 24
Peak memory 201128 kb
Host smart-b4176745-cb3f-4a07-a29b-0af02724bf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065983286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3065983286
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1292912593
Short name T764
Test name
Test status
Simulation time 327629843070 ps
CPU time 126.49 seconds
Started Jul 22 06:05:00 PM PDT 24
Finished Jul 22 06:07:06 PM PDT 24
Peak memory 201180 kb
Host smart-0a9b55ca-6bf9-49a1-ab8d-7ae33c817c91
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292912593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1292912593
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.764932265
Short name T426
Test name
Test status
Simulation time 192416812921 ps
CPU time 221.1 seconds
Started Jul 22 06:05:02 PM PDT 24
Finished Jul 22 06:08:44 PM PDT 24
Peak memory 201228 kb
Host smart-46baf3bd-2496-4ba1-a8a5-b1888a846374
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764932265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.764932265
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1675187980
Short name T352
Test name
Test status
Simulation time 128425787325 ps
CPU time 518.51 seconds
Started Jul 22 06:05:20 PM PDT 24
Finished Jul 22 06:13:59 PM PDT 24
Peak memory 201580 kb
Host smart-3f03101e-54a6-4235-9cab-7ac032ab5842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675187980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1675187980
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1586842229
Short name T514
Test name
Test status
Simulation time 44078673875 ps
CPU time 17.94 seconds
Started Jul 22 06:05:20 PM PDT 24
Finished Jul 22 06:05:38 PM PDT 24
Peak memory 201012 kb
Host smart-5158da4c-6e71-4386-aef2-b1bba46decad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586842229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1586842229
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2402373417
Short name T386
Test name
Test status
Simulation time 3750977088 ps
CPU time 1.16 seconds
Started Jul 22 06:05:12 PM PDT 24
Finished Jul 22 06:05:14 PM PDT 24
Peak memory 201052 kb
Host smart-3350bfa5-7a12-4373-914f-f82ed0249a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402373417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2402373417
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.621211603
Short name T362
Test name
Test status
Simulation time 5976220101 ps
CPU time 3.93 seconds
Started Jul 22 06:04:59 PM PDT 24
Finished Jul 22 06:05:04 PM PDT 24
Peak memory 201072 kb
Host smart-f489fe4a-4a2e-4bbd-bc92-10c8c0386cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621211603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.621211603
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2521203448
Short name T243
Test name
Test status
Simulation time 222824779904 ps
CPU time 252.75 seconds
Started Jul 22 06:05:04 PM PDT 24
Finished Jul 22 06:09:18 PM PDT 24
Peak memory 201436 kb
Host smart-a50b633a-3284-4a45-9744-6e11dd2c68da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521203448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2521203448
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1863468470
Short name T302
Test name
Test status
Simulation time 72042641660 ps
CPU time 40.37 seconds
Started Jul 22 06:05:01 PM PDT 24
Finished Jul 22 06:05:43 PM PDT 24
Peak memory 211088 kb
Host smart-0fb296ea-829f-408e-b415-057639c815e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863468470 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1863468470
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.726003544
Short name T681
Test name
Test status
Simulation time 380676841 ps
CPU time 0.83 seconds
Started Jul 22 06:05:12 PM PDT 24
Finished Jul 22 06:05:13 PM PDT 24
Peak memory 200984 kb
Host smart-97e9222b-fa6b-44b9-b339-6daae0b0151f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726003544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.726003544
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1583323105
Short name T316
Test name
Test status
Simulation time 325264519966 ps
CPU time 139.64 seconds
Started Jul 22 06:05:04 PM PDT 24
Finished Jul 22 06:07:25 PM PDT 24
Peak memory 201192 kb
Host smart-8547b3f5-e439-4372-ad6c-78f3555573ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583323105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1583323105
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3400585045
Short name T577
Test name
Test status
Simulation time 349330977621 ps
CPU time 630.4 seconds
Started Jul 22 06:05:03 PM PDT 24
Finished Jul 22 06:15:34 PM PDT 24
Peak memory 201192 kb
Host smart-71d27eeb-cc45-4347-997a-c9adac2d56ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400585045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3400585045
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.410428870
Short name T262
Test name
Test status
Simulation time 332144442136 ps
CPU time 782.06 seconds
Started Jul 22 06:07:43 PM PDT 24
Finished Jul 22 06:20:47 PM PDT 24
Peak memory 201288 kb
Host smart-8fa67cf5-eb92-4c76-911b-5a7a9048dd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410428870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.410428870
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1396068230
Short name T723
Test name
Test status
Simulation time 331858713113 ps
CPU time 192.23 seconds
Started Jul 22 06:05:08 PM PDT 24
Finished Jul 22 06:08:21 PM PDT 24
Peak memory 201212 kb
Host smart-4777c023-e5a3-4f8f-8024-62d77ea3a1a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396068230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1396068230
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2573996262
Short name T342
Test name
Test status
Simulation time 162016292768 ps
CPU time 369.97 seconds
Started Jul 22 06:05:08 PM PDT 24
Finished Jul 22 06:11:18 PM PDT 24
Peak memory 201296 kb
Host smart-fc3bfd70-723f-4b10-a636-621c02ac2a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573996262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2573996262
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.4202828134
Short name T632
Test name
Test status
Simulation time 492122207367 ps
CPU time 537.44 seconds
Started Jul 22 06:05:00 PM PDT 24
Finished Jul 22 06:13:58 PM PDT 24
Peak memory 201228 kb
Host smart-ee417bcd-bd81-43f4-ac1f-27d8b8bfc603
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202828134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.4202828134
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1895654767
Short name T280
Test name
Test status
Simulation time 184521655823 ps
CPU time 74.34 seconds
Started Jul 22 06:05:09 PM PDT 24
Finished Jul 22 06:06:24 PM PDT 24
Peak memory 201284 kb
Host smart-ca033ca1-f2f8-4800-892f-c868f673cb42
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895654767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1895654767
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.4009967246
Short name T501
Test name
Test status
Simulation time 404133873479 ps
CPU time 197.93 seconds
Started Jul 22 06:05:13 PM PDT 24
Finished Jul 22 06:08:31 PM PDT 24
Peak memory 201236 kb
Host smart-df1a0510-156f-4dba-96c9-9781709c18f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009967246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.4009967246
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3079221079
Short name T222
Test name
Test status
Simulation time 114961849603 ps
CPU time 392.69 seconds
Started Jul 22 06:05:14 PM PDT 24
Finished Jul 22 06:11:47 PM PDT 24
Peak memory 201716 kb
Host smart-670e048f-0329-4e1b-8b78-736a3949386f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079221079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3079221079
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.4061192340
Short name T467
Test name
Test status
Simulation time 43545693111 ps
CPU time 95.15 seconds
Started Jul 22 06:05:08 PM PDT 24
Finished Jul 22 06:06:43 PM PDT 24
Peak memory 201064 kb
Host smart-8ee3969a-1ff1-42ab-9a03-6b2a319dcad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061192340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.4061192340
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2477319428
Short name T603
Test name
Test status
Simulation time 3473292425 ps
CPU time 4.43 seconds
Started Jul 22 06:05:08 PM PDT 24
Finished Jul 22 06:05:13 PM PDT 24
Peak memory 201052 kb
Host smart-499e0e4b-c862-4525-809e-cb4ef8d207a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477319428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2477319428
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2302828163
Short name T537
Test name
Test status
Simulation time 5761102383 ps
CPU time 6.16 seconds
Started Jul 22 06:05:09 PM PDT 24
Finished Jul 22 06:05:15 PM PDT 24
Peak memory 201068 kb
Host smart-a6ca6872-3d2a-439c-b36c-bfdaeed8d2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302828163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2302828163
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2804293100
Short name T294
Test name
Test status
Simulation time 347599909142 ps
CPU time 404.51 seconds
Started Jul 22 06:05:16 PM PDT 24
Finished Jul 22 06:12:01 PM PDT 24
Peak memory 201212 kb
Host smart-8ff2e96c-bfdd-4329-9a88-0728b38dd2e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804293100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2804293100
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2552881530
Short name T550
Test name
Test status
Simulation time 64015533404 ps
CPU time 177.38 seconds
Started Jul 22 06:05:13 PM PDT 24
Finished Jul 22 06:08:11 PM PDT 24
Peak memory 211004 kb
Host smart-ce6fed1c-8b38-4131-a3cf-87b7180da409
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552881530 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2552881530
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3566930960
Short name T667
Test name
Test status
Simulation time 559091767 ps
CPU time 0.8 seconds
Started Jul 22 06:05:14 PM PDT 24
Finished Jul 22 06:05:15 PM PDT 24
Peak memory 201032 kb
Host smart-93752580-d24c-4499-a4d9-afbea404c8fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566930960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3566930960
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1207040273
Short name T725
Test name
Test status
Simulation time 157685276319 ps
CPU time 189.03 seconds
Started Jul 22 06:05:04 PM PDT 24
Finished Jul 22 06:08:14 PM PDT 24
Peak memory 201100 kb
Host smart-32f1c75c-e960-41bd-9ac3-127d549bfbf3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207040273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1207040273
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2463273971
Short name T483
Test name
Test status
Simulation time 163406435336 ps
CPU time 73.99 seconds
Started Jul 22 06:05:12 PM PDT 24
Finished Jul 22 06:06:27 PM PDT 24
Peak memory 201200 kb
Host smart-6b50b80f-7c5a-4779-aeac-ab0327365e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463273971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2463273971
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2244288599
Short name T343
Test name
Test status
Simulation time 479884196827 ps
CPU time 1087.81 seconds
Started Jul 22 06:05:07 PM PDT 24
Finished Jul 22 06:23:15 PM PDT 24
Peak memory 201176 kb
Host smart-be0ee0df-6ecf-4e87-8c5f-6b6dec4e763b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244288599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2244288599
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1135025881
Short name T408
Test name
Test status
Simulation time 492907650426 ps
CPU time 290.53 seconds
Started Jul 22 06:05:05 PM PDT 24
Finished Jul 22 06:09:56 PM PDT 24
Peak memory 201224 kb
Host smart-e7c10472-fbfa-47f3-9c39-80bdaab1677d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135025881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1135025881
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.981676968
Short name T459
Test name
Test status
Simulation time 494290388284 ps
CPU time 713.01 seconds
Started Jul 22 06:05:04 PM PDT 24
Finished Jul 22 06:16:58 PM PDT 24
Peak memory 201232 kb
Host smart-7832b953-48ce-437b-8b82-a8d050ef98a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981676968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.981676968
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.67429887
Short name T401
Test name
Test status
Simulation time 171693391859 ps
CPU time 57.98 seconds
Started Jul 22 06:05:04 PM PDT 24
Finished Jul 22 06:06:03 PM PDT 24
Peak memory 201188 kb
Host smart-5c101be4-37a3-40da-bc67-0f4e9fb371f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=67429887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixed
.67429887
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.110994756
Short name T340
Test name
Test status
Simulation time 539481508536 ps
CPU time 300.89 seconds
Started Jul 22 06:06:07 PM PDT 24
Finished Jul 22 06:11:09 PM PDT 24
Peak memory 201224 kb
Host smart-3dc8b5cc-ebbd-4dec-8e87-03d4cb9345ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110994756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.110994756
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1076745331
Short name T532
Test name
Test status
Simulation time 204355026955 ps
CPU time 448.26 seconds
Started Jul 22 06:05:05 PM PDT 24
Finished Jul 22 06:12:34 PM PDT 24
Peak memory 201164 kb
Host smart-4d88db76-9b86-487f-9c07-ef87321ffd7a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076745331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1076745331
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.717585330
Short name T481
Test name
Test status
Simulation time 114026410830 ps
CPU time 412.03 seconds
Started Jul 22 06:05:20 PM PDT 24
Finished Jul 22 06:12:13 PM PDT 24
Peak memory 201684 kb
Host smart-e1175198-f70e-4468-b975-804c657554d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717585330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.717585330
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1849554576
Short name T456
Test name
Test status
Simulation time 28441062671 ps
CPU time 34.37 seconds
Started Jul 22 06:05:04 PM PDT 24
Finished Jul 22 06:05:39 PM PDT 24
Peak memory 201052 kb
Host smart-5f77ccf0-f39d-4167-b986-3fdf92dd56af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849554576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1849554576
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2956176344
Short name T578
Test name
Test status
Simulation time 4774315315 ps
CPU time 12.47 seconds
Started Jul 22 06:05:07 PM PDT 24
Finished Jul 22 06:05:20 PM PDT 24
Peak memory 201044 kb
Host smart-dc0614be-c72b-47d8-b67e-6244745104b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956176344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2956176344
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2815722414
Short name T737
Test name
Test status
Simulation time 5848511907 ps
CPU time 7.58 seconds
Started Jul 22 06:05:02 PM PDT 24
Finished Jul 22 06:05:10 PM PDT 24
Peak memory 201136 kb
Host smart-0b4e1301-ff6d-46bd-ba39-cef8315a4993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815722414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2815722414
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2454906849
Short name T296
Test name
Test status
Simulation time 365444384136 ps
CPU time 222.54 seconds
Started Jul 22 06:05:20 PM PDT 24
Finished Jul 22 06:09:03 PM PDT 24
Peak memory 201116 kb
Host smart-9da6269a-e444-468c-b593-3453de0fe450
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454906849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2454906849
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1377955902
Short name T48
Test name
Test status
Simulation time 266090071981 ps
CPU time 276 seconds
Started Jul 22 06:05:09 PM PDT 24
Finished Jul 22 06:09:45 PM PDT 24
Peak memory 209972 kb
Host smart-3f11aaa2-adba-4bc8-95a6-8e617296b561
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377955902 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1377955902
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.380635861
Short name T746
Test name
Test status
Simulation time 527791724 ps
CPU time 1.2 seconds
Started Jul 22 06:05:18 PM PDT 24
Finished Jul 22 06:05:20 PM PDT 24
Peak memory 201008 kb
Host smart-63702a00-3a82-4b5d-a491-8a3c151d100c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380635861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.380635861
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3183223909
Short name T310
Test name
Test status
Simulation time 498428277347 ps
CPU time 1150.09 seconds
Started Jul 22 06:05:20 PM PDT 24
Finished Jul 22 06:24:31 PM PDT 24
Peak memory 201172 kb
Host smart-6ad64552-3e65-4235-92a0-eb6ec4b980fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183223909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3183223909
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.916278203
Short name T30
Test name
Test status
Simulation time 163924555967 ps
CPU time 388.75 seconds
Started Jul 22 06:05:07 PM PDT 24
Finished Jul 22 06:11:36 PM PDT 24
Peak memory 201272 kb
Host smart-6fea7e89-5a6b-4d53-b742-5ee8447f7015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916278203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.916278203
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1343742036
Short name T600
Test name
Test status
Simulation time 331917950744 ps
CPU time 780.22 seconds
Started Jul 22 06:05:03 PM PDT 24
Finished Jul 22 06:18:04 PM PDT 24
Peak memory 201160 kb
Host smart-54de4490-b458-496c-b4a1-73f365074d26
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343742036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1343742036
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2333737268
Short name T204
Test name
Test status
Simulation time 165864967110 ps
CPU time 176.65 seconds
Started Jul 22 06:05:09 PM PDT 24
Finished Jul 22 06:08:06 PM PDT 24
Peak memory 201192 kb
Host smart-c7ba55eb-fbba-480b-8d11-0feeb01f407e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333737268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2333737268
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3286609704
Short name T638
Test name
Test status
Simulation time 328016853267 ps
CPU time 226.57 seconds
Started Jul 22 06:05:20 PM PDT 24
Finished Jul 22 06:09:07 PM PDT 24
Peak memory 201160 kb
Host smart-ebe67c8e-4a1a-4f32-a41f-776d958a03de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286609704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3286609704
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2053971972
Short name T195
Test name
Test status
Simulation time 587472044362 ps
CPU time 350.51 seconds
Started Jul 22 06:05:42 PM PDT 24
Finished Jul 22 06:11:33 PM PDT 24
Peak memory 201216 kb
Host smart-80638b37-6a03-422d-924d-5c92960e013e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053971972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2053971972
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2308738863
Short name T753
Test name
Test status
Simulation time 84019742781 ps
CPU time 411.3 seconds
Started Jul 22 06:05:03 PM PDT 24
Finished Jul 22 06:11:55 PM PDT 24
Peak memory 201644 kb
Host smart-3a0bf649-9c0e-456a-8393-0720743b888f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308738863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2308738863
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1014358983
Short name T436
Test name
Test status
Simulation time 39519799900 ps
CPU time 26.43 seconds
Started Jul 22 06:05:09 PM PDT 24
Finished Jul 22 06:05:36 PM PDT 24
Peak memory 201032 kb
Host smart-7774a097-ce91-44fc-81fb-4ae55d95b305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014358983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1014358983
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1982141973
Short name T735
Test name
Test status
Simulation time 5533755651 ps
CPU time 3.7 seconds
Started Jul 22 06:05:00 PM PDT 24
Finished Jul 22 06:05:04 PM PDT 24
Peak memory 201072 kb
Host smart-031bfab6-75b5-4c97-be1d-d0e85734876a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982141973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1982141973
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1434110072
Short name T457
Test name
Test status
Simulation time 5706313256 ps
CPU time 4.16 seconds
Started Jul 22 06:05:07 PM PDT 24
Finished Jul 22 06:05:12 PM PDT 24
Peak memory 201092 kb
Host smart-ca3c103b-7fca-4b90-89f8-f76fc51473f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434110072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1434110072
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1126663564
Short name T613
Test name
Test status
Simulation time 172637018749 ps
CPU time 97.15 seconds
Started Jul 22 06:05:09 PM PDT 24
Finished Jul 22 06:06:48 PM PDT 24
Peak memory 201148 kb
Host smart-8072ede4-9c8a-4605-af1b-a278cee197a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126663564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1126663564
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.845384854
Short name T748
Test name
Test status
Simulation time 46778967258 ps
CPU time 29.62 seconds
Started Jul 22 06:05:13 PM PDT 24
Finished Jul 22 06:05:43 PM PDT 24
Peak memory 201384 kb
Host smart-11fe306f-ccf6-494f-b24d-b2f793852050
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845384854 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.845384854
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.4062501258
Short name T666
Test name
Test status
Simulation time 315301024 ps
CPU time 1.24 seconds
Started Jul 22 06:05:11 PM PDT 24
Finished Jul 22 06:05:12 PM PDT 24
Peak memory 201012 kb
Host smart-25877c77-b910-46e7-ba9d-c951633324ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062501258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.4062501258
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.278426783
Short name T684
Test name
Test status
Simulation time 161025130913 ps
CPU time 211.7 seconds
Started Jul 22 06:05:09 PM PDT 24
Finished Jul 22 06:08:41 PM PDT 24
Peak memory 201232 kb
Host smart-7a8261b6-1ce5-432e-8722-00f9efe925c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278426783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.278426783
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2688289498
Short name T430
Test name
Test status
Simulation time 490793350138 ps
CPU time 591.63 seconds
Started Jul 22 06:05:09 PM PDT 24
Finished Jul 22 06:15:02 PM PDT 24
Peak memory 201208 kb
Host smart-657115af-c8f6-4a75-9a50-eb22431e2eef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688289498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2688289498
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2114815622
Short name T486
Test name
Test status
Simulation time 492203983246 ps
CPU time 991.41 seconds
Started Jul 22 06:05:27 PM PDT 24
Finished Jul 22 06:21:59 PM PDT 24
Peak memory 201192 kb
Host smart-063c5321-7def-48b8-b84b-cfba830b3252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114815622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2114815622
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2351423715
Short name T658
Test name
Test status
Simulation time 489271492200 ps
CPU time 269.22 seconds
Started Jul 22 06:05:09 PM PDT 24
Finished Jul 22 06:09:40 PM PDT 24
Peak memory 201144 kb
Host smart-e76e9dc9-6ffe-4fe0-951d-32c23161ed93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351423715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2351423715
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3926922048
Short name T39
Test name
Test status
Simulation time 187017802540 ps
CPU time 107.24 seconds
Started Jul 22 06:05:27 PM PDT 24
Finished Jul 22 06:07:15 PM PDT 24
Peak memory 201200 kb
Host smart-22bfff17-a0fa-465e-9518-3a27dbb33cd1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926922048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3926922048
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.167671572
Short name T636
Test name
Test status
Simulation time 201990398973 ps
CPU time 223.1 seconds
Started Jul 22 06:07:06 PM PDT 24
Finished Jul 22 06:10:50 PM PDT 24
Peak memory 201164 kb
Host smart-1a5dba83-62dd-44e7-86c3-b5150f1b6aa3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167671572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.167671572
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1734869124
Short name T351
Test name
Test status
Simulation time 76847572974 ps
CPU time 322.54 seconds
Started Jul 22 06:05:18 PM PDT 24
Finished Jul 22 06:10:41 PM PDT 24
Peak memory 201632 kb
Host smart-2e883774-626e-45a9-b81f-118b8a192968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734869124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1734869124
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3755248621
Short name T69
Test name
Test status
Simulation time 31047307414 ps
CPU time 75.45 seconds
Started Jul 22 06:05:11 PM PDT 24
Finished Jul 22 06:06:28 PM PDT 24
Peak memory 201064 kb
Host smart-13d38c1d-4e98-4490-85bd-698aa2f48fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755248621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3755248621
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.4285225109
Short name T528
Test name
Test status
Simulation time 3626486195 ps
CPU time 8.42 seconds
Started Jul 22 06:05:41 PM PDT 24
Finished Jul 22 06:05:50 PM PDT 24
Peak memory 200996 kb
Host smart-16101b57-8a1e-432e-9677-b18596a97789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285225109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.4285225109
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3512085068
Short name T376
Test name
Test status
Simulation time 5665819585 ps
CPU time 7.64 seconds
Started Jul 22 06:05:40 PM PDT 24
Finished Jul 22 06:05:48 PM PDT 24
Peak memory 201028 kb
Host smart-4cf6ed0a-eedf-47ab-a8ec-6c1804594cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512085068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3512085068
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.4268632064
Short name T782
Test name
Test status
Simulation time 331699612841 ps
CPU time 314.03 seconds
Started Jul 22 06:07:43 PM PDT 24
Finished Jul 22 06:12:59 PM PDT 24
Peak memory 201268 kb
Host smart-9179d7ed-4ce8-4414-a834-6fb9003bf2f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268632064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.4268632064
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3903593129
Short name T54
Test name
Test status
Simulation time 374131162268 ps
CPU time 98.63 seconds
Started Jul 22 06:05:15 PM PDT 24
Finished Jul 22 06:06:54 PM PDT 24
Peak memory 209552 kb
Host smart-bedbe773-6dd2-4309-892f-3de6888e59d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903593129 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3903593129
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.950785887
Short name T92
Test name
Test status
Simulation time 300259089 ps
CPU time 0.76 seconds
Started Jul 22 06:05:28 PM PDT 24
Finished Jul 22 06:05:29 PM PDT 24
Peak memory 201008 kb
Host smart-1f7d88da-96dc-4cf4-9c2c-116f378d5698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950785887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.950785887
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3528136007
Short name T328
Test name
Test status
Simulation time 568944483746 ps
CPU time 126.5 seconds
Started Jul 22 06:07:05 PM PDT 24
Finished Jul 22 06:09:11 PM PDT 24
Peak memory 201200 kb
Host smart-cb3c6a51-6ae8-47ba-b53d-c9bc8884350d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528136007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3528136007
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3169589995
Short name T191
Test name
Test status
Simulation time 350198204883 ps
CPU time 212.55 seconds
Started Jul 22 06:05:19 PM PDT 24
Finished Jul 22 06:08:52 PM PDT 24
Peak memory 201292 kb
Host smart-e5f9463b-3b15-481f-b858-6c8f95f02ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169589995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3169589995
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2149531989
Short name T314
Test name
Test status
Simulation time 163414107881 ps
CPU time 392.56 seconds
Started Jul 22 06:05:11 PM PDT 24
Finished Jul 22 06:11:44 PM PDT 24
Peak memory 201308 kb
Host smart-8779f1e8-6e1e-4895-a7ff-552e9411f954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149531989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2149531989
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2965525744
Short name T104
Test name
Test status
Simulation time 334043091776 ps
CPU time 400.74 seconds
Started Jul 22 06:07:06 PM PDT 24
Finished Jul 22 06:13:48 PM PDT 24
Peak memory 201188 kb
Host smart-90a7cbd1-183a-469a-9e6b-5f5a117850ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965525744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2965525744
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2397059603
Short name T255
Test name
Test status
Simulation time 327055782544 ps
CPU time 748.35 seconds
Started Jul 22 06:05:09 PM PDT 24
Finished Jul 22 06:17:39 PM PDT 24
Peak memory 201216 kb
Host smart-bfa4a3f4-1124-4656-bf97-edace2c42e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397059603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2397059603
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.543744514
Short name T174
Test name
Test status
Simulation time 164843106984 ps
CPU time 39.47 seconds
Started Jul 22 06:05:40 PM PDT 24
Finished Jul 22 06:06:20 PM PDT 24
Peak memory 201164 kb
Host smart-e8d89f8d-9a1e-4a2d-9123-6d5c8d2fc939
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=543744514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.543744514
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2220986415
Short name T394
Test name
Test status
Simulation time 401013230629 ps
CPU time 214.14 seconds
Started Jul 22 06:05:19 PM PDT 24
Finished Jul 22 06:08:54 PM PDT 24
Peak memory 201188 kb
Host smart-122b5946-050d-4f47-8478-ced334b35e1c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220986415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2220986415
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1057297953
Short name T68
Test name
Test status
Simulation time 57930539747 ps
CPU time 246.97 seconds
Started Jul 22 06:05:23 PM PDT 24
Finished Jul 22 06:09:30 PM PDT 24
Peak memory 201604 kb
Host smart-05d86dc4-cfb2-49a2-9e34-fa112ea4aa18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057297953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1057297953
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1588820771
Short name T455
Test name
Test status
Simulation time 35313704425 ps
CPU time 78.51 seconds
Started Jul 22 06:05:31 PM PDT 24
Finished Jul 22 06:06:50 PM PDT 24
Peak memory 201040 kb
Host smart-3a25b3c0-c4b8-4cc5-9f8f-116298511b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588820771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1588820771
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.411406386
Short name T453
Test name
Test status
Simulation time 3255007897 ps
CPU time 7.4 seconds
Started Jul 22 06:05:21 PM PDT 24
Finished Jul 22 06:05:29 PM PDT 24
Peak memory 201048 kb
Host smart-8005b78e-f7a9-46d0-801f-cbed89404675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411406386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.411406386
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3155501177
Short name T380
Test name
Test status
Simulation time 6083263744 ps
CPU time 15.45 seconds
Started Jul 22 06:05:39 PM PDT 24
Finished Jul 22 06:05:55 PM PDT 24
Peak memory 201072 kb
Host smart-01ed6452-e588-4453-804c-b49af6f5cdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155501177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3155501177
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.901024695
Short name T747
Test name
Test status
Simulation time 289500679809 ps
CPU time 642.39 seconds
Started Jul 22 06:05:27 PM PDT 24
Finished Jul 22 06:16:10 PM PDT 24
Peak memory 209808 kb
Host smart-4e8f6e8c-9904-4fa9-bf88-009afd0b4fe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901024695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
901024695
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3343777293
Short name T51
Test name
Test status
Simulation time 441031422262 ps
CPU time 219.64 seconds
Started Jul 22 06:05:24 PM PDT 24
Finished Jul 22 06:09:04 PM PDT 24
Peak memory 217412 kb
Host smart-557a41cb-d9ee-4142-9a02-5c422a8f2809
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343777293 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3343777293
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3410624910
Short name T734
Test name
Test status
Simulation time 358256832 ps
CPU time 1.41 seconds
Started Jul 22 06:05:24 PM PDT 24
Finished Jul 22 06:05:26 PM PDT 24
Peak memory 201032 kb
Host smart-00cf50d1-b42d-4239-8565-686877f6ac2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410624910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3410624910
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3930975152
Short name T246
Test name
Test status
Simulation time 401128859659 ps
CPU time 183.28 seconds
Started Jul 22 06:05:20 PM PDT 24
Finished Jul 22 06:08:25 PM PDT 24
Peak memory 201276 kb
Host smart-5b912981-0212-4262-bd29-bd7b1cfc92c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930975152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3930975152
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3699495487
Short name T321
Test name
Test status
Simulation time 498027935658 ps
CPU time 104.4 seconds
Started Jul 22 06:05:19 PM PDT 24
Finished Jul 22 06:07:04 PM PDT 24
Peak memory 201180 kb
Host smart-ea12f069-bc1c-4570-8541-8602c9cb2bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699495487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3699495487
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.586104528
Short name T400
Test name
Test status
Simulation time 489305009446 ps
CPU time 289 seconds
Started Jul 22 06:05:19 PM PDT 24
Finished Jul 22 06:10:09 PM PDT 24
Peak memory 201184 kb
Host smart-184c978c-394a-4bd2-ba00-22f5850f1fee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=586104528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.586104528
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3967571634
Short name T659
Test name
Test status
Simulation time 488933189133 ps
CPU time 1164.35 seconds
Started Jul 22 06:05:31 PM PDT 24
Finished Jul 22 06:24:56 PM PDT 24
Peak memory 201256 kb
Host smart-f8a44664-7525-4fff-ada2-218f4d91e743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967571634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3967571634
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1805038024
Short name T425
Test name
Test status
Simulation time 332441521850 ps
CPU time 551.31 seconds
Started Jul 22 06:05:24 PM PDT 24
Finished Jul 22 06:14:36 PM PDT 24
Peak memory 201204 kb
Host smart-c8694840-63c4-4b04-98a6-35e6a846bf78
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805038024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1805038024
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3115680891
Short name T181
Test name
Test status
Simulation time 198108099381 ps
CPU time 104.37 seconds
Started Jul 22 06:05:16 PM PDT 24
Finished Jul 22 06:07:01 PM PDT 24
Peak memory 201280 kb
Host smart-891073f2-7de2-468a-b980-5188573c8ed1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115680891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3115680891
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3200559127
Short name T413
Test name
Test status
Simulation time 203692849925 ps
CPU time 223.27 seconds
Started Jul 22 06:05:25 PM PDT 24
Finished Jul 22 06:09:08 PM PDT 24
Peak memory 201200 kb
Host smart-5c6c002c-e028-4122-a081-68bfa91903fa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200559127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3200559127
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3052080013
Short name T672
Test name
Test status
Simulation time 31754438394 ps
CPU time 68.29 seconds
Started Jul 22 06:05:27 PM PDT 24
Finished Jul 22 06:06:35 PM PDT 24
Peak memory 201072 kb
Host smart-011922db-0cbd-4142-b866-f3cf1958026d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052080013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3052080013
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3010151208
Short name T374
Test name
Test status
Simulation time 5243197523 ps
CPU time 12.43 seconds
Started Jul 22 06:05:19 PM PDT 24
Finished Jul 22 06:05:33 PM PDT 24
Peak memory 200952 kb
Host smart-8e6b5e2e-edac-45de-87f4-abc73bc6d8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010151208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3010151208
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2452640346
Short name T664
Test name
Test status
Simulation time 5641656821 ps
CPU time 3.78 seconds
Started Jul 22 06:05:20 PM PDT 24
Finished Jul 22 06:05:25 PM PDT 24
Peak memory 201064 kb
Host smart-c152fec9-c992-4eab-b384-db2884b88448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452640346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2452640346
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.675663600
Short name T178
Test name
Test status
Simulation time 170191558405 ps
CPU time 65.16 seconds
Started Jul 22 06:05:51 PM PDT 24
Finished Jul 22 06:06:56 PM PDT 24
Peak memory 201224 kb
Host smart-c08c55f4-a9a3-4ac5-ab27-2c362dc3a4cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675663600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
675663600
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3184742055
Short name T50
Test name
Test status
Simulation time 312115453384 ps
CPU time 473.1 seconds
Started Jul 22 06:05:18 PM PDT 24
Finished Jul 22 06:13:11 PM PDT 24
Peak memory 209976 kb
Host smart-c25b2023-6df6-4448-8aa7-9f7c2f6684fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184742055 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3184742055
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3089878676
Short name T63
Test name
Test status
Simulation time 377229334 ps
CPU time 1.52 seconds
Started Jul 22 06:05:30 PM PDT 24
Finished Jul 22 06:05:32 PM PDT 24
Peak memory 200964 kb
Host smart-5f6568d0-bdd7-4366-b9d4-c6d05ac883c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089878676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3089878676
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.459843933
Short name T780
Test name
Test status
Simulation time 528260974623 ps
CPU time 591.02 seconds
Started Jul 22 06:05:30 PM PDT 24
Finished Jul 22 06:15:22 PM PDT 24
Peak memory 201260 kb
Host smart-fef79273-f7f5-4de3-b95b-3c78dd24ad2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459843933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.459843933
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.838111089
Short name T188
Test name
Test status
Simulation time 414430028873 ps
CPU time 227.83 seconds
Started Jul 22 06:05:37 PM PDT 24
Finished Jul 22 06:09:25 PM PDT 24
Peak memory 201204 kb
Host smart-0afe2ca4-aea4-496e-809e-6e0d4de8094c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838111089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.838111089
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3281976318
Short name T287
Test name
Test status
Simulation time 330373171017 ps
CPU time 520.99 seconds
Started Jul 22 06:05:30 PM PDT 24
Finished Jul 22 06:14:12 PM PDT 24
Peak memory 201216 kb
Host smart-1f4d2532-3b69-46b9-9dde-91493f583ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281976318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3281976318
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1631663327
Short name T673
Test name
Test status
Simulation time 334148683676 ps
CPU time 768.55 seconds
Started Jul 22 06:07:10 PM PDT 24
Finished Jul 22 06:20:00 PM PDT 24
Peak memory 201192 kb
Host smart-d51d4458-d127-4fb3-ab17-9e4addf977ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631663327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1631663327
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1667996561
Short name T121
Test name
Test status
Simulation time 498030386761 ps
CPU time 93.59 seconds
Started Jul 22 06:05:20 PM PDT 24
Finished Jul 22 06:06:55 PM PDT 24
Peak memory 201096 kb
Host smart-375be829-7eef-41a3-abfa-af29f46ee31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667996561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1667996561
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2820437950
Short name T477
Test name
Test status
Simulation time 497053761358 ps
CPU time 283.43 seconds
Started Jul 22 06:05:38 PM PDT 24
Finished Jul 22 06:10:22 PM PDT 24
Peak memory 201188 kb
Host smart-40322f01-7ff4-461e-96a4-4a9ae4a3b175
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820437950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2820437950
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3100366751
Short name T251
Test name
Test status
Simulation time 348553342738 ps
CPU time 139.56 seconds
Started Jul 22 06:05:31 PM PDT 24
Finished Jul 22 06:07:51 PM PDT 24
Peak memory 201340 kb
Host smart-61434648-36a4-4742-8748-50198af92e36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100366751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3100366751
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2158945172
Short name T507
Test name
Test status
Simulation time 595433034351 ps
CPU time 375.53 seconds
Started Jul 22 06:05:31 PM PDT 24
Finished Jul 22 06:11:47 PM PDT 24
Peak memory 201244 kb
Host smart-816625cf-ec46-4757-ac81-ed6e21c4b2af
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158945172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2158945172
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3164831815
Short name T470
Test name
Test status
Simulation time 90279948108 ps
CPU time 362.34 seconds
Started Jul 22 06:05:37 PM PDT 24
Finished Jul 22 06:11:41 PM PDT 24
Peak memory 201652 kb
Host smart-a949df8a-9c18-4ca5-a390-1a0c03313dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164831815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3164831815
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1185045192
Short name T679
Test name
Test status
Simulation time 21453301525 ps
CPU time 25.77 seconds
Started Jul 22 06:05:37 PM PDT 24
Finished Jul 22 06:06:04 PM PDT 24
Peak memory 201012 kb
Host smart-c62bc1fc-4c64-4ba5-9abf-5db5b658f1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185045192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1185045192
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3576941831
Short name T444
Test name
Test status
Simulation time 5383099490 ps
CPU time 3.74 seconds
Started Jul 22 06:05:29 PM PDT 24
Finished Jul 22 06:05:33 PM PDT 24
Peak memory 201100 kb
Host smart-51d86bf5-ecad-4bf4-9f5f-5438a497b784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576941831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3576941831
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2722514716
Short name T369
Test name
Test status
Simulation time 5605798418 ps
CPU time 13.12 seconds
Started Jul 22 06:05:20 PM PDT 24
Finished Jul 22 06:05:34 PM PDT 24
Peak memory 200964 kb
Host smart-33bcb23d-fa4e-4361-9a44-3d10a73558cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722514716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2722514716
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3882494433
Short name T623
Test name
Test status
Simulation time 179554133309 ps
CPU time 428.9 seconds
Started Jul 22 06:05:32 PM PDT 24
Finished Jul 22 06:12:42 PM PDT 24
Peak memory 201268 kb
Host smart-6c896bfb-5730-453f-bfce-be8bd9757972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882494433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3882494433
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.336542268
Short name T703
Test name
Test status
Simulation time 529131169 ps
CPU time 1.87 seconds
Started Jul 22 06:05:31 PM PDT 24
Finished Jul 22 06:05:34 PM PDT 24
Peak memory 201024 kb
Host smart-94710191-e4c9-4ef9-91ce-8c2e824f0b7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336542268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.336542268
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.825902044
Short name T762
Test name
Test status
Simulation time 489838376630 ps
CPU time 1096.58 seconds
Started Jul 22 06:07:06 PM PDT 24
Finished Jul 22 06:25:24 PM PDT 24
Peak memory 201188 kb
Host smart-be782659-b7ff-4353-a72e-e02081d5c7d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=825902044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.825902044
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3547265728
Short name T157
Test name
Test status
Simulation time 328077165647 ps
CPU time 353.48 seconds
Started Jul 22 06:05:30 PM PDT 24
Finished Jul 22 06:11:24 PM PDT 24
Peak memory 201172 kb
Host smart-6daf8608-c3bd-4d1c-9cb4-9eda093f1add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547265728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3547265728
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.605695854
Short name T627
Test name
Test status
Simulation time 160652992700 ps
CPU time 370.02 seconds
Started Jul 22 06:07:13 PM PDT 24
Finished Jul 22 06:13:23 PM PDT 24
Peak memory 201224 kb
Host smart-62361a29-119f-45fb-8a79-707d06959774
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=605695854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.605695854
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3424675609
Short name T411
Test name
Test status
Simulation time 588591450763 ps
CPU time 158.03 seconds
Started Jul 22 06:05:29 PM PDT 24
Finished Jul 22 06:08:08 PM PDT 24
Peak memory 201196 kb
Host smart-189365e6-0152-4a26-bbdc-4e63843dff26
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424675609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3424675609
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.634653232
Short name T551
Test name
Test status
Simulation time 79216015466 ps
CPU time 348.9 seconds
Started Jul 22 06:05:31 PM PDT 24
Finished Jul 22 06:11:20 PM PDT 24
Peak memory 201728 kb
Host smart-19611707-5bff-435d-9494-cb35138dd763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634653232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.634653232
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1176450962
Short name T442
Test name
Test status
Simulation time 35038199956 ps
CPU time 20.35 seconds
Started Jul 22 06:05:31 PM PDT 24
Finished Jul 22 06:05:52 PM PDT 24
Peak memory 201056 kb
Host smart-94fdffed-c98b-4b97-8801-bd88ffbe4ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176450962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1176450962
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.76893669
Short name T559
Test name
Test status
Simulation time 4822867179 ps
CPU time 11.71 seconds
Started Jul 22 06:05:37 PM PDT 24
Finished Jul 22 06:05:50 PM PDT 24
Peak memory 201060 kb
Host smart-40c0fbf4-9782-4974-bfa1-dc5890ffa92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76893669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.76893669
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.590802613
Short name T665
Test name
Test status
Simulation time 6115602540 ps
CPU time 15.35 seconds
Started Jul 22 06:05:38 PM PDT 24
Finished Jul 22 06:05:54 PM PDT 24
Peak memory 201048 kb
Host smart-88ea5a11-3d88-41ac-9388-a70d88c2e7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590802613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.590802613
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.562771974
Short name T731
Test name
Test status
Simulation time 643850421715 ps
CPU time 442.57 seconds
Started Jul 22 06:07:06 PM PDT 24
Finished Jul 22 06:14:29 PM PDT 24
Peak memory 212528 kb
Host smart-748dd777-9317-417c-806d-d03eeb004891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562771974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
562771974
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.404042373
Short name T14
Test name
Test status
Simulation time 75946578167 ps
CPU time 61.24 seconds
Started Jul 22 06:05:37 PM PDT 24
Finished Jul 22 06:06:39 PM PDT 24
Peak memory 209616 kb
Host smart-d73dc09c-3fbc-497d-b1bd-c3f5ef35c6b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404042373 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.404042373
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3751244431
Short name T543
Test name
Test status
Simulation time 471440331 ps
CPU time 0.86 seconds
Started Jul 22 06:05:42 PM PDT 24
Finished Jul 22 06:05:44 PM PDT 24
Peak memory 201000 kb
Host smart-a5ada85f-5494-41b1-907a-e617a33213be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751244431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3751244431
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1394763690
Short name T770
Test name
Test status
Simulation time 165334250687 ps
CPU time 220.56 seconds
Started Jul 22 06:05:35 PM PDT 24
Finished Jul 22 06:09:16 PM PDT 24
Peak memory 201288 kb
Host smart-d436d981-2ae8-43a8-abb4-ea2b82215b2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394763690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1394763690
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1447255185
Short name T692
Test name
Test status
Simulation time 163459929260 ps
CPU time 395.76 seconds
Started Jul 22 06:05:38 PM PDT 24
Finished Jul 22 06:12:14 PM PDT 24
Peak memory 201204 kb
Host smart-3d5fdb47-1731-4ab6-89e4-810cbf60d68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447255185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1447255185
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3746880980
Short name T555
Test name
Test status
Simulation time 491358799029 ps
CPU time 252.34 seconds
Started Jul 22 06:06:28 PM PDT 24
Finished Jul 22 06:10:41 PM PDT 24
Peak memory 201272 kb
Host smart-e87add9f-cb58-4b75-8d61-d0831a28942e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746880980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3746880980
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.463788648
Short name T702
Test name
Test status
Simulation time 161196867410 ps
CPU time 347.61 seconds
Started Jul 22 06:05:31 PM PDT 24
Finished Jul 22 06:11:20 PM PDT 24
Peak memory 201156 kb
Host smart-dc3ff6e2-906d-45d4-a140-1331ca296348
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=463788648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.463788648
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2311446421
Short name T164
Test name
Test status
Simulation time 501433685447 ps
CPU time 1228.13 seconds
Started Jul 22 06:05:31 PM PDT 24
Finished Jul 22 06:26:00 PM PDT 24
Peak memory 201236 kb
Host smart-cb0dff21-bae5-40c8-b00d-81fd08edab59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311446421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2311446421
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.959927839
Short name T795
Test name
Test status
Simulation time 332222086208 ps
CPU time 786.66 seconds
Started Jul 22 06:05:27 PM PDT 24
Finished Jul 22 06:18:34 PM PDT 24
Peak memory 201216 kb
Host smart-22a1f23b-552c-49e5-819e-01f7eb6af042
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=959927839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.959927839
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3821274251
Short name T676
Test name
Test status
Simulation time 557050366911 ps
CPU time 666.69 seconds
Started Jul 22 06:07:13 PM PDT 24
Finished Jul 22 06:18:20 PM PDT 24
Peak memory 201300 kb
Host smart-4159a0d0-d567-4d0c-ae4a-b8a6092eccfa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821274251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3821274251
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2068007448
Short name T372
Test name
Test status
Simulation time 202939893979 ps
CPU time 308.98 seconds
Started Jul 22 06:06:27 PM PDT 24
Finished Jul 22 06:11:38 PM PDT 24
Peak memory 201184 kb
Host smart-216a883c-408d-40c1-a6b0-ebd02bff181e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068007448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2068007448
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3778040296
Short name T452
Test name
Test status
Simulation time 109750815953 ps
CPU time 476.63 seconds
Started Jul 22 06:05:39 PM PDT 24
Finished Jul 22 06:13:37 PM PDT 24
Peak memory 201740 kb
Host smart-bdbe9b00-9472-4ea3-85c7-9d1d7eb84f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778040296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3778040296
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2284244016
Short name T569
Test name
Test status
Simulation time 39350381888 ps
CPU time 38.22 seconds
Started Jul 22 06:05:30 PM PDT 24
Finished Jul 22 06:06:09 PM PDT 24
Peak memory 201124 kb
Host smart-93940060-21b8-4f51-830c-5e76df477779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284244016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2284244016
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1179374428
Short name T515
Test name
Test status
Simulation time 5437915170 ps
CPU time 14.17 seconds
Started Jul 22 06:05:31 PM PDT 24
Finished Jul 22 06:05:45 PM PDT 24
Peak memory 201080 kb
Host smart-5a86ca4d-280e-460d-9c03-3abd73990c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179374428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1179374428
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3821493036
Short name T377
Test name
Test status
Simulation time 5787374267 ps
CPU time 13.67 seconds
Started Jul 22 06:05:38 PM PDT 24
Finished Jul 22 06:05:52 PM PDT 24
Peak memory 201072 kb
Host smart-e911550d-752e-49e9-9068-15c33214048d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821493036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3821493036
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3778743884
Short name T272
Test name
Test status
Simulation time 40423740547 ps
CPU time 106.48 seconds
Started Jul 22 06:05:45 PM PDT 24
Finished Jul 22 06:07:31 PM PDT 24
Peak memory 218040 kb
Host smart-a64af691-e8af-43e5-ab28-7f7103ec718b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778743884 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3778743884
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2063394275
Short name T384
Test name
Test status
Simulation time 347691370 ps
CPU time 1.39 seconds
Started Jul 22 06:04:27 PM PDT 24
Finished Jul 22 06:04:29 PM PDT 24
Peak memory 201012 kb
Host smart-42991f1b-4298-4046-8b84-b3ee988ac8cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063394275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2063394275
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1115074570
Short name T350
Test name
Test status
Simulation time 540763300068 ps
CPU time 1257.79 seconds
Started Jul 22 06:04:35 PM PDT 24
Finished Jul 22 06:25:33 PM PDT 24
Peak memory 201216 kb
Host smart-82c30fbd-c596-457c-a0c7-4ccc7629878a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115074570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1115074570
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1525993748
Short name T675
Test name
Test status
Simulation time 160586849065 ps
CPU time 102.81 seconds
Started Jul 22 06:04:39 PM PDT 24
Finished Jul 22 06:06:22 PM PDT 24
Peak memory 201204 kb
Host smart-e919622a-4cf1-4ea8-b43c-ea3178db2fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525993748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1525993748
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.512185706
Short name T758
Test name
Test status
Simulation time 169470643271 ps
CPU time 106.48 seconds
Started Jul 22 06:04:24 PM PDT 24
Finished Jul 22 06:06:11 PM PDT 24
Peak memory 201180 kb
Host smart-63f26b3e-6b67-4dc1-8733-e9e8ae02504d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512185706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.512185706
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.586062475
Short name T544
Test name
Test status
Simulation time 326564600735 ps
CPU time 347.45 seconds
Started Jul 22 06:04:39 PM PDT 24
Finished Jul 22 06:10:27 PM PDT 24
Peak memory 201280 kb
Host smart-50ca3b02-0ea9-4234-87b7-64f31bc39c4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=586062475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.586062475
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1850165866
Short name T621
Test name
Test status
Simulation time 333821791201 ps
CPU time 399.23 seconds
Started Jul 22 06:04:30 PM PDT 24
Finished Jul 22 06:11:09 PM PDT 24
Peak memory 201280 kb
Host smart-b806b1b8-b0b4-4486-b3d4-8d194956cfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850165866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1850165866
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1644819287
Short name T525
Test name
Test status
Simulation time 327865427081 ps
CPU time 201.62 seconds
Started Jul 22 06:04:35 PM PDT 24
Finished Jul 22 06:07:57 PM PDT 24
Peak memory 201268 kb
Host smart-3703ff2c-8963-42cd-9cf3-756e0a939969
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644819287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1644819287
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.147552633
Short name T736
Test name
Test status
Simulation time 171717928068 ps
CPU time 213.2 seconds
Started Jul 22 06:04:35 PM PDT 24
Finished Jul 22 06:08:09 PM PDT 24
Peak memory 201252 kb
Host smart-b1ef892b-9a8e-417e-add6-ec538dd640b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147552633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.147552633
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2165037539
Short name T794
Test name
Test status
Simulation time 211556929455 ps
CPU time 242.35 seconds
Started Jul 22 06:04:35 PM PDT 24
Finished Jul 22 06:08:38 PM PDT 24
Peak memory 201356 kb
Host smart-8f71186d-4722-4084-8780-ce5f1ce66cff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165037539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2165037539
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1637914007
Short name T640
Test name
Test status
Simulation time 108294790191 ps
CPU time 554.8 seconds
Started Jul 22 06:04:23 PM PDT 24
Finished Jul 22 06:13:39 PM PDT 24
Peak memory 201572 kb
Host smart-a186e34f-6f6c-4c8b-b753-93eee41c1ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637914007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1637914007
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3538654376
Short name T406
Test name
Test status
Simulation time 27821742573 ps
CPU time 67.74 seconds
Started Jul 22 06:04:22 PM PDT 24
Finished Jul 22 06:05:30 PM PDT 24
Peak memory 201064 kb
Host smart-6f88261f-43fb-40a6-b10c-29d75da5b636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538654376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3538654376
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3237006736
Short name T617
Test name
Test status
Simulation time 3538606510 ps
CPU time 2.39 seconds
Started Jul 22 06:04:30 PM PDT 24
Finished Jul 22 06:04:33 PM PDT 24
Peak memory 201080 kb
Host smart-a1c909d9-54f5-41a5-9180-039daca05e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237006736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3237006736
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3508796390
Short name T100
Test name
Test status
Simulation time 4086344386 ps
CPU time 1.71 seconds
Started Jul 22 06:04:39 PM PDT 24
Finished Jul 22 06:04:42 PM PDT 24
Peak memory 216888 kb
Host smart-dbc6f13a-ecd7-4ccb-89e0-f314710f0883
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508796390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3508796390
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3536775514
Short name T568
Test name
Test status
Simulation time 5756930431 ps
CPU time 3.4 seconds
Started Jul 22 06:04:32 PM PDT 24
Finished Jul 22 06:04:36 PM PDT 24
Peak memory 201072 kb
Host smart-4b90981f-c3fd-4581-ba81-61c068dfc821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536775514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3536775514
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2796427128
Short name T113
Test name
Test status
Simulation time 349987313258 ps
CPU time 182.89 seconds
Started Jul 22 06:04:53 PM PDT 24
Finished Jul 22 06:07:57 PM PDT 24
Peak memory 201228 kb
Host smart-38938fee-6112-4494-a9c8-449a2104ed9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796427128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2796427128
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3662347167
Short name T284
Test name
Test status
Simulation time 54496712240 ps
CPU time 83.24 seconds
Started Jul 22 06:04:38 PM PDT 24
Finished Jul 22 06:06:03 PM PDT 24
Peak memory 209956 kb
Host smart-44357925-a7ae-4f88-b625-17d8cc7c14d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662347167 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3662347167
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2486438099
Short name T33
Test name
Test status
Simulation time 358607139 ps
CPU time 1.01 seconds
Started Jul 22 06:05:42 PM PDT 24
Finished Jul 22 06:05:44 PM PDT 24
Peak memory 201004 kb
Host smart-2f8e3706-b20a-40a1-a7e8-f7683ede78ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486438099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2486438099
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2663718940
Short name T713
Test name
Test status
Simulation time 169912665094 ps
CPU time 200.32 seconds
Started Jul 22 06:05:41 PM PDT 24
Finished Jul 22 06:09:02 PM PDT 24
Peak memory 201224 kb
Host smart-85e67201-87aa-4632-aa36-c30a87b799ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663718940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2663718940
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1834987408
Short name T797
Test name
Test status
Simulation time 332212949300 ps
CPU time 760.7 seconds
Started Jul 22 06:05:39 PM PDT 24
Finished Jul 22 06:18:21 PM PDT 24
Peak memory 201280 kb
Host smart-ea447d1f-15c6-485c-b729-f99f1794c629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834987408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1834987408
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.75011546
Short name T533
Test name
Test status
Simulation time 165734965310 ps
CPU time 381.15 seconds
Started Jul 22 06:07:36 PM PDT 24
Finished Jul 22 06:13:58 PM PDT 24
Peak memory 201204 kb
Host smart-8396f28c-a018-4fe1-9f5a-3f1ec0c59aff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=75011546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt
_fixed.75011546
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3676278541
Short name T40
Test name
Test status
Simulation time 332513718869 ps
CPU time 198.03 seconds
Started Jul 22 06:05:40 PM PDT 24
Finished Jul 22 06:08:59 PM PDT 24
Peak memory 201200 kb
Host smart-240bf430-142f-4479-8ced-a55ab245960e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676278541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3676278541
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1009875872
Short name T793
Test name
Test status
Simulation time 393910870773 ps
CPU time 137.56 seconds
Started Jul 22 06:05:45 PM PDT 24
Finished Jul 22 06:08:03 PM PDT 24
Peak memory 201212 kb
Host smart-70866b0b-4e81-4b79-8732-c44887c7a96e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009875872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1009875872
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3933237531
Short name T704
Test name
Test status
Simulation time 122429060077 ps
CPU time 618.7 seconds
Started Jul 22 06:05:40 PM PDT 24
Finished Jul 22 06:16:00 PM PDT 24
Peak memory 201648 kb
Host smart-1c8273bd-9931-4406-bf3f-a9b0b7a47083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933237531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3933237531
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3702165734
Short name T379
Test name
Test status
Simulation time 40115060143 ps
CPU time 73.97 seconds
Started Jul 22 06:07:12 PM PDT 24
Finished Jul 22 06:08:27 PM PDT 24
Peak memory 201028 kb
Host smart-4038d592-eee5-400c-9285-8bed9748467e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702165734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3702165734
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1180922297
Short name T427
Test name
Test status
Simulation time 5088703653 ps
CPU time 3.19 seconds
Started Jul 22 06:05:43 PM PDT 24
Finished Jul 22 06:05:47 PM PDT 24
Peak memory 201004 kb
Host smart-18169d88-47f1-4022-a201-6f2a7c97cdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180922297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1180922297
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3765247989
Short name T593
Test name
Test status
Simulation time 5731525951 ps
CPU time 7.07 seconds
Started Jul 22 06:05:41 PM PDT 24
Finished Jul 22 06:05:49 PM PDT 24
Peak memory 201072 kb
Host smart-1532f36f-e68c-4a75-80b6-1a23d071421f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765247989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3765247989
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3487467975
Short name T42
Test name
Test status
Simulation time 35702020784 ps
CPU time 81.8 seconds
Started Jul 22 06:07:42 PM PDT 24
Finished Jul 22 06:09:05 PM PDT 24
Peak memory 201060 kb
Host smart-bab83998-a425-4f19-8e92-50f2cf99c2fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487467975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3487467975
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1991532048
Short name T32
Test name
Test status
Simulation time 72031046189 ps
CPU time 171.26 seconds
Started Jul 22 06:05:43 PM PDT 24
Finished Jul 22 06:08:35 PM PDT 24
Peak memory 209496 kb
Host smart-ed419610-1e99-426f-bc40-50ff9fc3ad46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991532048 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1991532048
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1069929628
Short name T760
Test name
Test status
Simulation time 516377594 ps
CPU time 1.78 seconds
Started Jul 22 06:05:44 PM PDT 24
Finished Jul 22 06:05:46 PM PDT 24
Peak memory 201044 kb
Host smart-130de552-1487-4f29-be10-e78337bfef20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069929628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1069929628
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3828625402
Short name T118
Test name
Test status
Simulation time 169582384831 ps
CPU time 184.09 seconds
Started Jul 22 06:05:38 PM PDT 24
Finished Jul 22 06:08:43 PM PDT 24
Peak memory 201280 kb
Host smart-d3f6bdf9-e716-4cb2-99db-ef4c28e38030
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828625402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3828625402
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2392360673
Short name T105
Test name
Test status
Simulation time 166813376122 ps
CPU time 366.14 seconds
Started Jul 22 06:05:44 PM PDT 24
Finished Jul 22 06:11:51 PM PDT 24
Peak memory 201228 kb
Host smart-d1f640ca-faf5-4b83-9bce-dc30457b5ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392360673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2392360673
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.4066202466
Short name T461
Test name
Test status
Simulation time 332482004934 ps
CPU time 189.7 seconds
Started Jul 22 06:05:39 PM PDT 24
Finished Jul 22 06:08:50 PM PDT 24
Peak memory 201156 kb
Host smart-0187e606-c539-48c3-92f0-d908e5faf825
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066202466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.4066202466
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2973560926
Short name T169
Test name
Test status
Simulation time 489848149067 ps
CPU time 327.8 seconds
Started Jul 22 06:05:39 PM PDT 24
Finished Jul 22 06:11:07 PM PDT 24
Peak memory 201196 kb
Host smart-448bf635-9518-410e-a4a2-2f3c8dfabda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973560926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2973560926
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1865672482
Short name T4
Test name
Test status
Simulation time 322311978011 ps
CPU time 670.78 seconds
Started Jul 22 06:05:42 PM PDT 24
Finished Jul 22 06:16:54 PM PDT 24
Peak memory 201180 kb
Host smart-7eb25d15-9111-4290-a810-0aa6e490dacb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865672482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1865672482
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2912814978
Short name T585
Test name
Test status
Simulation time 585427213601 ps
CPU time 510.37 seconds
Started Jul 22 06:05:42 PM PDT 24
Finished Jul 22 06:14:13 PM PDT 24
Peak memory 201224 kb
Host smart-44d21a37-0d75-4457-aa5f-c504a5f29f67
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912814978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2912814978
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.407422324
Short name T441
Test name
Test status
Simulation time 198693643984 ps
CPU time 85.18 seconds
Started Jul 22 06:05:39 PM PDT 24
Finished Jul 22 06:07:05 PM PDT 24
Peak memory 201212 kb
Host smart-3c4feb8a-2c0f-4c2d-a6e6-b41397111ac0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407422324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.407422324
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.707294033
Short name T774
Test name
Test status
Simulation time 89536818023 ps
CPU time 303.24 seconds
Started Jul 22 06:05:41 PM PDT 24
Finished Jul 22 06:10:45 PM PDT 24
Peak memory 201704 kb
Host smart-952351f1-0c48-4cf5-820a-f4c4fa1d8137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707294033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.707294033
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2914228034
Short name T378
Test name
Test status
Simulation time 23209626917 ps
CPU time 13.13 seconds
Started Jul 22 06:05:40 PM PDT 24
Finished Jul 22 06:05:54 PM PDT 24
Peak memory 201052 kb
Host smart-5aebb98c-982c-411d-81df-c4893a93e03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914228034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2914228034
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3883098966
Short name T560
Test name
Test status
Simulation time 4110823625 ps
CPU time 2.93 seconds
Started Jul 22 06:05:40 PM PDT 24
Finished Jul 22 06:05:44 PM PDT 24
Peak memory 201092 kb
Host smart-3d1fccc6-a75b-414a-b267-5dd99f35425a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883098966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3883098966
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1646254112
Short name T382
Test name
Test status
Simulation time 5577853511 ps
CPU time 3.98 seconds
Started Jul 22 06:05:41 PM PDT 24
Finished Jul 22 06:05:45 PM PDT 24
Peak memory 201064 kb
Host smart-f9481d5e-dee7-4bea-8011-0dd4e7d12f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646254112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1646254112
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.956430620
Short name T616
Test name
Test status
Simulation time 170683082228 ps
CPU time 106 seconds
Started Jul 22 06:05:37 PM PDT 24
Finished Jul 22 06:07:24 PM PDT 24
Peak memory 201452 kb
Host smart-fdacc4be-12ea-4382-a1b5-713821a6ccd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956430620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
956430620
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3350541857
Short name T771
Test name
Test status
Simulation time 226997105865 ps
CPU time 139.55 seconds
Started Jul 22 06:05:39 PM PDT 24
Finished Jul 22 06:08:00 PM PDT 24
Peak memory 209996 kb
Host smart-bef2ee0c-5077-49b9-9bbd-23c4fa313104
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350541857 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3350541857
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3585074533
Short name T393
Test name
Test status
Simulation time 481759613 ps
CPU time 1.7 seconds
Started Jul 22 06:05:54 PM PDT 24
Finished Jul 22 06:05:56 PM PDT 24
Peak memory 201000 kb
Host smart-d71db86f-22b9-4d75-aa9f-b0add060a057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585074533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3585074533
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2432824020
Short name T313
Test name
Test status
Simulation time 330442640085 ps
CPU time 765.6 seconds
Started Jul 22 06:05:55 PM PDT 24
Finished Jul 22 06:18:41 PM PDT 24
Peak memory 201232 kb
Host smart-4f937fec-03ab-4131-9ede-f704396cdf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432824020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2432824020
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2372257467
Short name T687
Test name
Test status
Simulation time 326347954374 ps
CPU time 190.89 seconds
Started Jul 22 06:05:55 PM PDT 24
Finished Jul 22 06:09:06 PM PDT 24
Peak memory 201168 kb
Host smart-8f9b219d-c6ac-4945-972a-a64db31a3d7e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372257467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2372257467
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2472517673
Short name T176
Test name
Test status
Simulation time 331708833250 ps
CPU time 350.69 seconds
Started Jul 22 06:05:46 PM PDT 24
Finished Jul 22 06:11:36 PM PDT 24
Peak memory 201224 kb
Host smart-76f7c581-717c-4068-8640-f5fbb850fd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472517673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2472517673
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1933802709
Short name T409
Test name
Test status
Simulation time 495018283022 ps
CPU time 279.88 seconds
Started Jul 22 06:07:11 PM PDT 24
Finished Jul 22 06:11:52 PM PDT 24
Peak memory 201196 kb
Host smart-09b00c7b-f47a-408a-8b20-40239a975729
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933802709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1933802709
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3232008451
Short name T508
Test name
Test status
Simulation time 299710569260 ps
CPU time 694.05 seconds
Started Jul 22 06:05:54 PM PDT 24
Finished Jul 22 06:17:28 PM PDT 24
Peak memory 201280 kb
Host smart-9fde36ff-88de-4372-9fdd-a86670e2874f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232008451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3232008451
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.453508894
Short name T447
Test name
Test status
Simulation time 208690988133 ps
CPU time 189.37 seconds
Started Jul 22 06:05:53 PM PDT 24
Finished Jul 22 06:09:02 PM PDT 24
Peak memory 201212 kb
Host smart-1dccaa8f-a76f-4d4e-aa8f-444005d6c8cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453508894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.453508894
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.4123989892
Short name T582
Test name
Test status
Simulation time 87104070513 ps
CPU time 318.25 seconds
Started Jul 22 06:06:21 PM PDT 24
Finished Jul 22 06:11:40 PM PDT 24
Peak memory 201604 kb
Host smart-b338a966-3e4e-4fa3-ab9e-74f38a3e583d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123989892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.4123989892
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3014283553
Short name T463
Test name
Test status
Simulation time 46079877480 ps
CPU time 22.94 seconds
Started Jul 22 06:05:54 PM PDT 24
Finished Jul 22 06:06:18 PM PDT 24
Peak memory 201064 kb
Host smart-a30ef859-2990-4633-b1d5-1c3d853019a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014283553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3014283553
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.943046732
Short name T591
Test name
Test status
Simulation time 3443229350 ps
CPU time 7.96 seconds
Started Jul 22 06:05:56 PM PDT 24
Finished Jul 22 06:06:04 PM PDT 24
Peak memory 201040 kb
Host smart-5b747a38-27c3-4186-ba21-61343df384e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943046732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.943046732
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2364552593
Short name T754
Test name
Test status
Simulation time 6018753403 ps
CPU time 8.09 seconds
Started Jul 22 06:05:44 PM PDT 24
Finished Jul 22 06:05:53 PM PDT 24
Peak memory 201092 kb
Host smart-08079d20-e5d9-49f9-9a7e-5fc2bbb0e871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364552593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2364552593
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3881157798
Short name T336
Test name
Test status
Simulation time 59398478545 ps
CPU time 121.36 seconds
Started Jul 22 06:05:55 PM PDT 24
Finished Jul 22 06:07:57 PM PDT 24
Peak memory 209528 kb
Host smart-72c4b03d-8865-4817-a2af-56135d6ea269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881157798 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3881157798
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3883228212
Short name T126
Test name
Test status
Simulation time 436183877 ps
CPU time 0.65 seconds
Started Jul 22 06:07:35 PM PDT 24
Finished Jul 22 06:07:36 PM PDT 24
Peak memory 201000 kb
Host smart-8bdc5d88-5ee0-4d11-ab32-80c3be127885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883228212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3883228212
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.421177949
Short name T338
Test name
Test status
Simulation time 166450972139 ps
CPU time 200.67 seconds
Started Jul 22 06:05:53 PM PDT 24
Finished Jul 22 06:09:14 PM PDT 24
Peak memory 201276 kb
Host smart-d1ea522f-b657-4b0a-beb6-cd1acbe4ea49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421177949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.421177949
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3793176273
Short name T182
Test name
Test status
Simulation time 167435620671 ps
CPU time 202.28 seconds
Started Jul 22 06:05:52 PM PDT 24
Finished Jul 22 06:09:15 PM PDT 24
Peak memory 201108 kb
Host smart-bb7683df-5f28-4965-b992-f2b9601da7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793176273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3793176273
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1744935142
Short name T742
Test name
Test status
Simulation time 159358375015 ps
CPU time 245.24 seconds
Started Jul 22 06:05:53 PM PDT 24
Finished Jul 22 06:09:59 PM PDT 24
Peak memory 201252 kb
Host smart-2c18c8af-4829-4663-9420-edf317efa4a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744935142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1744935142
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.291330915
Short name T733
Test name
Test status
Simulation time 325540734688 ps
CPU time 175.83 seconds
Started Jul 22 06:05:54 PM PDT 24
Finished Jul 22 06:08:50 PM PDT 24
Peak memory 201216 kb
Host smart-0e7b9dd7-f38a-4589-9a96-4adc9226c915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291330915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.291330915
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2654449017
Short name T55
Test name
Test status
Simulation time 164636607455 ps
CPU time 189.6 seconds
Started Jul 22 06:05:56 PM PDT 24
Finished Jul 22 06:09:06 PM PDT 24
Peak memory 201212 kb
Host smart-83d6ae94-2a97-4086-8882-dcd3aac82331
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654449017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2654449017
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2514758803
Short name T2
Test name
Test status
Simulation time 199006328360 ps
CPU time 219.01 seconds
Started Jul 22 06:05:53 PM PDT 24
Finished Jul 22 06:09:32 PM PDT 24
Peak memory 201228 kb
Host smart-dc6cc7f2-87f9-4131-b4d1-16ad0a18e52e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514758803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2514758803
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.4040500747
Short name T739
Test name
Test status
Simulation time 216135669276 ps
CPU time 470.53 seconds
Started Jul 22 06:05:54 PM PDT 24
Finished Jul 22 06:13:46 PM PDT 24
Peak memory 201224 kb
Host smart-07389cfa-c8fa-4394-9d25-9ff83e2f4e40
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040500747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.4040500747
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3630578416
Short name T716
Test name
Test status
Simulation time 84543176592 ps
CPU time 350.91 seconds
Started Jul 22 06:06:05 PM PDT 24
Finished Jul 22 06:11:56 PM PDT 24
Peak memory 201632 kb
Host smart-fa2aa73b-9a15-4a4f-9f8c-3878c90285c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630578416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3630578416
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3834442555
Short name T575
Test name
Test status
Simulation time 37732243064 ps
CPU time 6.73 seconds
Started Jul 22 06:06:04 PM PDT 24
Finished Jul 22 06:06:11 PM PDT 24
Peak memory 201056 kb
Host smart-7c9f0499-24bb-4e8b-9f32-a8cd68779530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834442555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3834442555
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3522273236
Short name T783
Test name
Test status
Simulation time 3040902954 ps
CPU time 7.95 seconds
Started Jul 22 06:06:04 PM PDT 24
Finished Jul 22 06:06:12 PM PDT 24
Peak memory 201052 kb
Host smart-0391ee6a-e594-43ea-885c-2470b28949a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522273236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3522273236
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3577956926
Short name T553
Test name
Test status
Simulation time 5731008136 ps
CPU time 3.62 seconds
Started Jul 22 06:05:53 PM PDT 24
Finished Jul 22 06:05:57 PM PDT 24
Peak memory 201072 kb
Host smart-fb5edccb-68bc-4102-b6df-f0a9f6064481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577956926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3577956926
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.4155023721
Short name T44
Test name
Test status
Simulation time 306491019698 ps
CPU time 584.64 seconds
Started Jul 22 06:07:26 PM PDT 24
Finished Jul 22 06:17:10 PM PDT 24
Peak memory 201612 kb
Host smart-73bcffbf-1fe5-4862-b7eb-bfaa150a56db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155023721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.4155023721
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3115535194
Short name T487
Test name
Test status
Simulation time 55714782144 ps
CPU time 182.17 seconds
Started Jul 22 06:07:21 PM PDT 24
Finished Jul 22 06:10:24 PM PDT 24
Peak memory 218124 kb
Host smart-35b58181-cffe-45d7-81c4-ea0e5ebb310e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115535194 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3115535194
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3688332625
Short name T524
Test name
Test status
Simulation time 350736991 ps
CPU time 1.46 seconds
Started Jul 22 06:07:33 PM PDT 24
Finished Jul 22 06:07:35 PM PDT 24
Peak memory 201004 kb
Host smart-8940082c-d377-451a-8e87-22e876fc575c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688332625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3688332625
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3503571520
Short name T335
Test name
Test status
Simulation time 365076797419 ps
CPU time 438.55 seconds
Started Jul 22 06:06:06 PM PDT 24
Finished Jul 22 06:13:25 PM PDT 24
Peak memory 201208 kb
Host smart-bfc11a34-8b01-434a-902a-773f41965e1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503571520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3503571520
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.496335209
Short name T726
Test name
Test status
Simulation time 330111855710 ps
CPU time 406.16 seconds
Started Jul 22 06:06:06 PM PDT 24
Finished Jul 22 06:12:52 PM PDT 24
Peak memory 201184 kb
Host smart-c3ab2aa6-8d13-44c1-bc38-d340dfdeb7dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=496335209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.496335209
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3442687975
Short name T327
Test name
Test status
Simulation time 334977652223 ps
CPU time 184.85 seconds
Started Jul 22 06:06:01 PM PDT 24
Finished Jul 22 06:09:06 PM PDT 24
Peak memory 201224 kb
Host smart-cb563177-f43a-44b0-aff9-53d75971c908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442687975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3442687975
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.394375192
Short name T547
Test name
Test status
Simulation time 159774744262 ps
CPU time 83.83 seconds
Started Jul 22 06:08:28 PM PDT 24
Finished Jul 22 06:09:53 PM PDT 24
Peak memory 201200 kb
Host smart-d05b8664-293f-41aa-8ac2-5e4c317be6fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=394375192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.394375192
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.394461228
Short name T545
Test name
Test status
Simulation time 171625482917 ps
CPU time 356.01 seconds
Started Jul 22 06:06:03 PM PDT 24
Finished Jul 22 06:12:00 PM PDT 24
Peak memory 201224 kb
Host smart-d0cf9113-a765-4bf1-b595-3380fd367931
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394461228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.394461228
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1230889882
Short name T370
Test name
Test status
Simulation time 588958717584 ps
CPU time 1423.36 seconds
Started Jul 22 06:08:03 PM PDT 24
Finished Jul 22 06:31:47 PM PDT 24
Peak memory 201240 kb
Host smart-28c4b6e6-d0ae-4a15-b95e-b5617963a096
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230889882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1230889882
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1610662676
Short name T516
Test name
Test status
Simulation time 93683768573 ps
CPU time 456.16 seconds
Started Jul 22 06:08:09 PM PDT 24
Finished Jul 22 06:15:46 PM PDT 24
Peak memory 201576 kb
Host smart-a0f9e0e7-4bc9-43cb-a53e-ad8ed7e8362c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610662676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1610662676
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3562191324
Short name T610
Test name
Test status
Simulation time 36813446469 ps
CPU time 20.98 seconds
Started Jul 22 06:06:03 PM PDT 24
Finished Jul 22 06:06:24 PM PDT 24
Peak memory 201008 kb
Host smart-a76849ae-f214-4867-9cd6-28f37427edff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562191324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3562191324
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2482891161
Short name T366
Test name
Test status
Simulation time 3688921939 ps
CPU time 4.57 seconds
Started Jul 22 06:06:06 PM PDT 24
Finished Jul 22 06:06:11 PM PDT 24
Peak memory 201048 kb
Host smart-039e38f7-7d9d-4c38-90bd-6d8185802592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482891161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2482891161
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.257787064
Short name T775
Test name
Test status
Simulation time 5663205637 ps
CPU time 14.05 seconds
Started Jul 22 06:08:02 PM PDT 24
Finished Jul 22 06:08:16 PM PDT 24
Peak memory 201088 kb
Host smart-43c497b3-f1d3-43ee-8a54-f5b2eca6252c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257787064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.257787064
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3968859270
Short name T160
Test name
Test status
Simulation time 331645332197 ps
CPU time 634.23 seconds
Started Jul 22 06:06:05 PM PDT 24
Finished Jul 22 06:16:39 PM PDT 24
Peak memory 201196 kb
Host smart-356f11cf-2778-42e1-a738-6ee81f427c79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968859270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3968859270
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.386084579
Short name T19
Test name
Test status
Simulation time 67561107600 ps
CPU time 106.7 seconds
Started Jul 22 06:07:53 PM PDT 24
Finished Jul 22 06:09:40 PM PDT 24
Peak memory 209556 kb
Host smart-36b7ee90-cceb-4120-aedb-966999d3691a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386084579 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.386084579
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.574696536
Short name T367
Test name
Test status
Simulation time 463176492 ps
CPU time 0.88 seconds
Started Jul 22 06:06:10 PM PDT 24
Finished Jul 22 06:06:11 PM PDT 24
Peak memory 201240 kb
Host smart-ae8d4cdf-0882-4ee9-9e5b-992cf483a4b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574696536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.574696536
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2264348797
Short name T625
Test name
Test status
Simulation time 323513120640 ps
CPU time 429.63 seconds
Started Jul 22 06:06:05 PM PDT 24
Finished Jul 22 06:13:15 PM PDT 24
Peak memory 201276 kb
Host smart-42f2eeec-7c69-4708-9aed-dff14dd8ed75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264348797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2264348797
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2898910809
Short name T439
Test name
Test status
Simulation time 165814002278 ps
CPU time 97.8 seconds
Started Jul 22 06:07:58 PM PDT 24
Finished Jul 22 06:09:36 PM PDT 24
Peak memory 201164 kb
Host smart-e4ac02e0-3e52-4398-a701-4e8557bd6b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898910809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2898910809
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2563648462
Short name T601
Test name
Test status
Simulation time 329939235590 ps
CPU time 98.13 seconds
Started Jul 22 06:07:24 PM PDT 24
Finished Jul 22 06:09:03 PM PDT 24
Peak memory 201180 kb
Host smart-53d1b357-f08c-4e03-a510-27cd69a81c6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563648462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2563648462
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.678329229
Short name T37
Test name
Test status
Simulation time 160593489867 ps
CPU time 387.31 seconds
Started Jul 22 06:06:10 PM PDT 24
Finished Jul 22 06:12:38 PM PDT 24
Peak memory 201236 kb
Host smart-47a1c399-81b3-400f-9d0d-05014835f975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678329229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.678329229
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3774405994
Short name T431
Test name
Test status
Simulation time 165104571877 ps
CPU time 100.07 seconds
Started Jul 22 06:06:03 PM PDT 24
Finished Jul 22 06:07:43 PM PDT 24
Peak memory 201212 kb
Host smart-e6d2f856-e777-409b-9e4f-a0f1e5ad71ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774405994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3774405994
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1658041666
Short name T798
Test name
Test status
Simulation time 401655462228 ps
CPU time 464.89 seconds
Started Jul 22 06:07:58 PM PDT 24
Finished Jul 22 06:15:44 PM PDT 24
Peak memory 201160 kb
Host smart-737a7d82-d7c1-499f-99c8-6de5c898dbb1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658041666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1658041666
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2195670979
Short name T71
Test name
Test status
Simulation time 90826933423 ps
CPU time 285.54 seconds
Started Jul 22 06:06:13 PM PDT 24
Finished Jul 22 06:10:59 PM PDT 24
Peak memory 201644 kb
Host smart-737f7b12-6aad-449e-b2b8-7e628a838335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195670979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2195670979
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1991733100
Short name T678
Test name
Test status
Simulation time 44856413166 ps
CPU time 52.68 seconds
Started Jul 22 06:06:07 PM PDT 24
Finished Jul 22 06:07:00 PM PDT 24
Peak memory 201052 kb
Host smart-c3f5d4fa-a84e-42d0-bf8e-0b4c775d21ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991733100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1991733100
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1839720507
Short name T685
Test name
Test status
Simulation time 4465177176 ps
CPU time 11.68 seconds
Started Jul 22 06:06:11 PM PDT 24
Finished Jul 22 06:06:23 PM PDT 24
Peak memory 201068 kb
Host smart-9872dc4b-7c5d-40a7-b01c-21d5c3092808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839720507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1839720507
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.480100101
Short name T570
Test name
Test status
Simulation time 5951352254 ps
CPU time 3.86 seconds
Started Jul 22 06:07:25 PM PDT 24
Finished Jul 22 06:07:29 PM PDT 24
Peak memory 201056 kb
Host smart-b2fde653-3e43-497d-a506-8ee10d7766da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480100101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.480100101
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2596960861
Short name T520
Test name
Test status
Simulation time 173174139468 ps
CPU time 233.03 seconds
Started Jul 22 06:06:13 PM PDT 24
Finished Jul 22 06:10:07 PM PDT 24
Peak memory 210016 kb
Host smart-58e8e09e-d090-481a-8b25-665ee22584df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596960861 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2596960861
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2188054124
Short name T363
Test name
Test status
Simulation time 338841367 ps
CPU time 1.39 seconds
Started Jul 22 06:06:12 PM PDT 24
Finished Jul 22 06:06:14 PM PDT 24
Peak memory 201012 kb
Host smart-71076f13-0904-4043-9e57-95ae2cd7e5fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188054124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2188054124
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3671962243
Short name T346
Test name
Test status
Simulation time 573392632977 ps
CPU time 678.29 seconds
Started Jul 22 06:07:40 PM PDT 24
Finished Jul 22 06:19:00 PM PDT 24
Peak memory 201228 kb
Host smart-a716c0b5-cde0-4d6f-b10f-a8818a73c3bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671962243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3671962243
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3183969261
Short name T273
Test name
Test status
Simulation time 156921671530 ps
CPU time 192.5 seconds
Started Jul 22 06:06:14 PM PDT 24
Finished Jul 22 06:09:27 PM PDT 24
Peak memory 201220 kb
Host smart-5ba0f7f3-5136-40b8-b7a4-661615afeaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183969261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3183969261
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2087711197
Short name T564
Test name
Test status
Simulation time 330725364750 ps
CPU time 236.35 seconds
Started Jul 22 06:08:28 PM PDT 24
Finished Jul 22 06:12:25 PM PDT 24
Peak memory 201200 kb
Host smart-d6613cb2-5667-41d3-a5bf-fd1c6a1e9334
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087711197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2087711197
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3172406479
Short name T107
Test name
Test status
Simulation time 160052093844 ps
CPU time 172.37 seconds
Started Jul 22 06:06:13 PM PDT 24
Finished Jul 22 06:09:05 PM PDT 24
Peak memory 201168 kb
Host smart-9351b08b-220f-4e8b-a057-fb566d286cf4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172406479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3172406479
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3572128085
Short name T728
Test name
Test status
Simulation time 189450185982 ps
CPU time 204.34 seconds
Started Jul 22 06:07:39 PM PDT 24
Finished Jul 22 06:11:05 PM PDT 24
Peak memory 201228 kb
Host smart-4164172d-a596-4534-97d3-537a22da4067
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572128085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3572128085
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3977892029
Short name T608
Test name
Test status
Simulation time 592428330258 ps
CPU time 1467.77 seconds
Started Jul 22 06:06:14 PM PDT 24
Finished Jul 22 06:30:42 PM PDT 24
Peak memory 201140 kb
Host smart-80f04d30-ec7d-409d-aebe-c6bb958298d8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977892029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3977892029
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1699706242
Short name T472
Test name
Test status
Simulation time 107881533805 ps
CPU time 429.22 seconds
Started Jul 22 06:06:15 PM PDT 24
Finished Jul 22 06:13:24 PM PDT 24
Peak memory 201672 kb
Host smart-ac3d7743-71bd-4a49-b26e-575d8c32a856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699706242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1699706242
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3441882691
Short name T629
Test name
Test status
Simulation time 31884306741 ps
CPU time 35.75 seconds
Started Jul 22 06:06:13 PM PDT 24
Finished Jul 22 06:06:49 PM PDT 24
Peak memory 201024 kb
Host smart-2bf4bfd8-d13a-4f49-9c2a-3d923a361548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441882691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3441882691
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3678137974
Short name T523
Test name
Test status
Simulation time 4794347604 ps
CPU time 12.03 seconds
Started Jul 22 06:06:32 PM PDT 24
Finished Jul 22 06:06:45 PM PDT 24
Peak memory 201048 kb
Host smart-6d5b4468-fe94-4aa4-8088-63dca54efcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678137974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3678137974
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3038151870
Short name T724
Test name
Test status
Simulation time 5685138773 ps
CPU time 12.66 seconds
Started Jul 22 06:06:12 PM PDT 24
Finished Jul 22 06:06:25 PM PDT 24
Peak memory 201064 kb
Host smart-e61b7f7f-5786-49d6-b243-db68c6bbd076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038151870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3038151870
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2920642710
Short name T45
Test name
Test status
Simulation time 336153965838 ps
CPU time 191.49 seconds
Started Jul 22 06:06:15 PM PDT 24
Finished Jul 22 06:09:27 PM PDT 24
Peak memory 201204 kb
Host smart-f0cdbd01-6ab3-42ae-8596-97dec4fdcfc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920642710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2920642710
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.261733996
Short name T722
Test name
Test status
Simulation time 102444574577 ps
CPU time 154.15 seconds
Started Jul 22 06:07:53 PM PDT 24
Finished Jul 22 06:10:28 PM PDT 24
Peak memory 218144 kb
Host smart-4040dd53-291f-47c9-8beb-aa2da90f9c2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261733996 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.261733996
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2481284517
Short name T587
Test name
Test status
Simulation time 394391704 ps
CPU time 0.84 seconds
Started Jul 22 06:06:24 PM PDT 24
Finished Jul 22 06:06:25 PM PDT 24
Peak memory 200968 kb
Host smart-96dee44d-441f-4f3c-8848-17f6132817dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481284517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2481284517
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1595250917
Short name T517
Test name
Test status
Simulation time 518656628142 ps
CPU time 825.95 seconds
Started Jul 22 06:07:01 PM PDT 24
Finished Jul 22 06:20:47 PM PDT 24
Peak memory 201192 kb
Host smart-8144a5b6-7d49-4ae3-82cd-21ca5beb8109
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595250917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1595250917
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.273098716
Short name T285
Test name
Test status
Simulation time 165016366480 ps
CPU time 104.68 seconds
Started Jul 22 06:06:15 PM PDT 24
Finished Jul 22 06:08:00 PM PDT 24
Peak memory 201200 kb
Host smart-32dc02be-7394-435a-8071-3514022a1463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273098716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.273098716
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.570502785
Short name T446
Test name
Test status
Simulation time 487522244222 ps
CPU time 472.01 seconds
Started Jul 22 06:08:08 PM PDT 24
Finished Jul 22 06:16:01 PM PDT 24
Peak memory 201244 kb
Host smart-1ea435f5-d1f2-4c81-a214-d9d9dd77221d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=570502785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.570502785
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.176759088
Short name T612
Test name
Test status
Simulation time 321732016293 ps
CPU time 673.63 seconds
Started Jul 22 06:07:40 PM PDT 24
Finished Jul 22 06:18:54 PM PDT 24
Peak memory 201236 kb
Host smart-cd18c431-6b2e-423b-b371-3981ac4aa767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176759088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.176759088
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.639305771
Short name T799
Test name
Test status
Simulation time 496344206786 ps
CPU time 902.5 seconds
Started Jul 22 06:06:13 PM PDT 24
Finished Jul 22 06:21:16 PM PDT 24
Peak memory 201132 kb
Host smart-ec5bea96-f16e-4b96-a214-f17fa8c1878b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=639305771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.639305771
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2241764925
Short name T611
Test name
Test status
Simulation time 201345875193 ps
CPU time 475.46 seconds
Started Jul 22 06:08:08 PM PDT 24
Finished Jul 22 06:16:04 PM PDT 24
Peak memory 201188 kb
Host smart-915d12bc-9723-45dd-b369-dfef95af0930
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241764925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2241764925
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2771296083
Short name T776
Test name
Test status
Simulation time 98033022401 ps
CPU time 356.94 seconds
Started Jul 22 06:06:22 PM PDT 24
Finished Jul 22 06:12:19 PM PDT 24
Peak memory 201660 kb
Host smart-93626df5-98ef-49c7-b8d5-ed0e71ba7d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771296083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2771296083
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1060850747
Short name T445
Test name
Test status
Simulation time 37201177932 ps
CPU time 16.45 seconds
Started Jul 22 06:07:40 PM PDT 24
Finished Jul 22 06:07:58 PM PDT 24
Peak memory 201076 kb
Host smart-b571e1dd-8e82-4701-9de8-82c1828986c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060850747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1060850747
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.144607460
Short name T405
Test name
Test status
Simulation time 4493343153 ps
CPU time 5.71 seconds
Started Jul 22 06:06:14 PM PDT 24
Finished Jul 22 06:06:20 PM PDT 24
Peak memory 201004 kb
Host smart-afe6e417-9c2a-4ae4-8e3c-aa3386d796c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144607460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.144607460
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2576277590
Short name T155
Test name
Test status
Simulation time 5960959103 ps
CPU time 1.44 seconds
Started Jul 22 06:07:33 PM PDT 24
Finished Jul 22 06:07:35 PM PDT 24
Peak memory 201068 kb
Host smart-e3106cc5-dadb-4e88-9063-1c33f15aaa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576277590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2576277590
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1645552810
Short name T696
Test name
Test status
Simulation time 90289483755 ps
CPU time 96.35 seconds
Started Jul 22 06:06:10 PM PDT 24
Finished Jul 22 06:07:47 PM PDT 24
Peak memory 209616 kb
Host smart-ec9e7a87-00f4-41db-b4f7-0983b88f6853
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645552810 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1645552810
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.587112678
Short name T91
Test name
Test status
Simulation time 458225239 ps
CPU time 0.65 seconds
Started Jul 22 06:08:12 PM PDT 24
Finished Jul 22 06:08:13 PM PDT 24
Peak memory 200996 kb
Host smart-e2188e91-4f6c-474f-8f07-6233b25b9734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587112678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.587112678
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3815440885
Short name T312
Test name
Test status
Simulation time 544648797704 ps
CPU time 1256.37 seconds
Started Jul 22 06:06:23 PM PDT 24
Finished Jul 22 06:27:20 PM PDT 24
Peak memory 201244 kb
Host smart-3ba6659b-71f9-4748-8377-2922d17c8f02
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815440885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3815440885
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2529872980
Short name T59
Test name
Test status
Simulation time 326366534917 ps
CPU time 667.02 seconds
Started Jul 22 06:08:12 PM PDT 24
Finished Jul 22 06:19:20 PM PDT 24
Peak memory 201192 kb
Host smart-d0658195-bada-4c38-881e-a4136f6028de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529872980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2529872980
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.631994027
Short name T423
Test name
Test status
Simulation time 163818362598 ps
CPU time 82.23 seconds
Started Jul 22 06:06:23 PM PDT 24
Finished Jul 22 06:07:46 PM PDT 24
Peak memory 201096 kb
Host smart-a4963557-0828-4a97-89e1-72c7a9146a9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=631994027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.631994027
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.4116974387
Short name T158
Test name
Test status
Simulation time 490633910112 ps
CPU time 261.47 seconds
Started Jul 22 06:06:23 PM PDT 24
Finished Jul 22 06:10:45 PM PDT 24
Peak memory 201264 kb
Host smart-6e834633-6efd-41ea-86f3-3ce04eefdc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116974387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.4116974387
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3258712850
Short name T519
Test name
Test status
Simulation time 319143193104 ps
CPU time 66.56 seconds
Started Jul 22 06:06:23 PM PDT 24
Finished Jul 22 06:07:30 PM PDT 24
Peak memory 201156 kb
Host smart-a85ce421-ad22-4d42-b520-f9ab2907627c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258712850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3258712850
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.118446436
Short name T184
Test name
Test status
Simulation time 595057114945 ps
CPU time 317.09 seconds
Started Jul 22 06:06:23 PM PDT 24
Finished Jul 22 06:11:40 PM PDT 24
Peak memory 201276 kb
Host smart-164d3728-6c44-4c07-be0f-634a8133d87f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118446436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.118446436
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1548707433
Short name T497
Test name
Test status
Simulation time 592226101721 ps
CPU time 1335.51 seconds
Started Jul 22 06:06:22 PM PDT 24
Finished Jul 22 06:28:38 PM PDT 24
Peak memory 201172 kb
Host smart-aba56970-c9ab-484c-993b-4c82f41e7a98
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548707433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1548707433
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2712596414
Short name T767
Test name
Test status
Simulation time 100180215347 ps
CPU time 461.33 seconds
Started Jul 22 06:08:12 PM PDT 24
Finished Jul 22 06:15:55 PM PDT 24
Peak memory 201620 kb
Host smart-14df3b1d-3ef2-45fb-a9c8-494a8fc8afe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712596414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2712596414
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3460135345
Short name T402
Test name
Test status
Simulation time 23185539276 ps
CPU time 10.28 seconds
Started Jul 22 06:08:12 PM PDT 24
Finished Jul 22 06:08:24 PM PDT 24
Peak memory 201048 kb
Host smart-5e34b32f-c8eb-407b-9741-e5d0e8df65ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460135345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3460135345
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1648862355
Short name T729
Test name
Test status
Simulation time 4128102909 ps
CPU time 9.68 seconds
Started Jul 22 06:06:23 PM PDT 24
Finished Jul 22 06:06:33 PM PDT 24
Peak memory 201196 kb
Host smart-d45bf4f8-6e71-46c0-a9c3-71ce291ce304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648862355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1648862355
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3455882635
Short name T125
Test name
Test status
Simulation time 5736089840 ps
CPU time 14 seconds
Started Jul 22 06:06:22 PM PDT 24
Finished Jul 22 06:06:37 PM PDT 24
Peak memory 201080 kb
Host smart-4c94da50-748a-488e-a81f-540af539bbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455882635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3455882635
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.2814718364
Short name T238
Test name
Test status
Simulation time 496323107598 ps
CPU time 1191.33 seconds
Started Jul 22 06:06:23 PM PDT 24
Finished Jul 22 06:26:15 PM PDT 24
Peak memory 201212 kb
Host smart-43d28395-4262-4272-a116-975e7b9d084a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814718364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.2814718364
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.447831099
Short name T15
Test name
Test status
Simulation time 29661797965 ps
CPU time 67.74 seconds
Started Jul 22 06:06:23 PM PDT 24
Finished Jul 22 06:07:31 PM PDT 24
Peak memory 209980 kb
Host smart-6e055167-ba6d-4f8f-a750-f5f48967fb62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447831099 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.447831099
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1382419974
Short name T641
Test name
Test status
Simulation time 531200873 ps
CPU time 1.77 seconds
Started Jul 22 06:06:35 PM PDT 24
Finished Jul 22 06:06:37 PM PDT 24
Peak memory 200984 kb
Host smart-79c6b3c3-941a-430f-8722-5a6f3b41d0d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382419974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1382419974
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2444938157
Short name T645
Test name
Test status
Simulation time 196948970170 ps
CPU time 424.57 seconds
Started Jul 22 06:06:32 PM PDT 24
Finished Jul 22 06:13:37 PM PDT 24
Peak memory 201208 kb
Host smart-a8af957b-10f4-4416-a0ef-258697c8aefd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444938157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2444938157
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1567410574
Short name T311
Test name
Test status
Simulation time 325636936928 ps
CPU time 774.39 seconds
Started Jul 22 06:06:35 PM PDT 24
Finished Jul 22 06:19:30 PM PDT 24
Peak memory 201188 kb
Host smart-138e90fc-d0bf-4e6a-ae06-534127acedb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567410574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1567410574
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.465336399
Short name T626
Test name
Test status
Simulation time 159047000314 ps
CPU time 73.64 seconds
Started Jul 22 06:06:32 PM PDT 24
Finished Jul 22 06:07:47 PM PDT 24
Peak memory 201252 kb
Host smart-b01ddb27-af9f-4d57-aff5-6ba91452d095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465336399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.465336399
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3450102272
Short name T592
Test name
Test status
Simulation time 495684332486 ps
CPU time 336.74 seconds
Started Jul 22 06:06:35 PM PDT 24
Finished Jul 22 06:12:12 PM PDT 24
Peak memory 201236 kb
Host smart-52f1d5cf-fcf9-4dfd-9291-ee6ebf8b1c82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450102272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3450102272
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1956861422
Short name T432
Test name
Test status
Simulation time 166188431278 ps
CPU time 391.5 seconds
Started Jul 22 06:06:23 PM PDT 24
Finished Jul 22 06:12:55 PM PDT 24
Peak memory 201228 kb
Host smart-470dc15e-e15a-4d5e-aa19-75acb3b3839b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956861422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1956861422
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1888372333
Short name T434
Test name
Test status
Simulation time 488847808062 ps
CPU time 295.18 seconds
Started Jul 22 06:06:23 PM PDT 24
Finished Jul 22 06:11:19 PM PDT 24
Peak memory 201232 kb
Host smart-9e43da4d-9ec4-47a3-bf7d-ea727b179319
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888372333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1888372333
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3202694659
Short name T173
Test name
Test status
Simulation time 189585958977 ps
CPU time 103.61 seconds
Started Jul 22 06:06:33 PM PDT 24
Finished Jul 22 06:08:17 PM PDT 24
Peak memory 201276 kb
Host smart-187c33f0-5aca-4f92-be6f-f9627172dd82
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202694659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3202694659
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.926307289
Short name T730
Test name
Test status
Simulation time 202890414323 ps
CPU time 481.21 seconds
Started Jul 22 06:06:33 PM PDT 24
Finished Jul 22 06:14:35 PM PDT 24
Peak memory 201260 kb
Host smart-911328fa-c025-4d5f-9b58-695ccf0f080a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926307289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.926307289
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3965859320
Short name T556
Test name
Test status
Simulation time 86136373273 ps
CPU time 425.54 seconds
Started Jul 22 06:06:34 PM PDT 24
Finished Jul 22 06:13:40 PM PDT 24
Peak memory 201704 kb
Host smart-9e3d2941-d694-4aed-b272-3c0b8fcc8f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965859320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3965859320
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2822249201
Short name T482
Test name
Test status
Simulation time 35551687987 ps
CPU time 88.29 seconds
Started Jul 22 06:06:35 PM PDT 24
Finished Jul 22 06:08:04 PM PDT 24
Peak memory 201112 kb
Host smart-a6c5dff4-7e3c-4d37-8ada-1f9face68708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822249201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2822249201
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1203600532
Short name T466
Test name
Test status
Simulation time 4271738054 ps
CPU time 11.09 seconds
Started Jul 22 06:06:29 PM PDT 24
Finished Jul 22 06:06:41 PM PDT 24
Peak memory 201052 kb
Host smart-5d2eed7f-2852-4dd6-a500-50678307b2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203600532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1203600532
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2174576983
Short name T699
Test name
Test status
Simulation time 6189008004 ps
CPU time 9.93 seconds
Started Jul 22 06:06:24 PM PDT 24
Finished Jul 22 06:06:34 PM PDT 24
Peak memory 201024 kb
Host smart-2997b188-705a-46af-94a2-04d8d27c7d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174576983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2174576983
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3922660981
Short name T540
Test name
Test status
Simulation time 164515629232 ps
CPU time 218.2 seconds
Started Jul 22 06:08:26 PM PDT 24
Finished Jul 22 06:12:05 PM PDT 24
Peak memory 201140 kb
Host smart-0027c1f1-c2c2-4d28-a738-e44bc6712789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922660981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3922660981
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1528106779
Short name T565
Test name
Test status
Simulation time 166962534133 ps
CPU time 158.98 seconds
Started Jul 22 06:06:34 PM PDT 24
Finished Jul 22 06:09:13 PM PDT 24
Peak memory 209956 kb
Host smart-712372f0-0f1b-47bd-a500-6a73e7ad8bb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528106779 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1528106779
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2823916708
Short name T387
Test name
Test status
Simulation time 448368957 ps
CPU time 1.17 seconds
Started Jul 22 06:04:38 PM PDT 24
Finished Jul 22 06:04:40 PM PDT 24
Peak memory 200980 kb
Host smart-0a26bf7b-e6b7-46c6-92d1-74c5de9ca8a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823916708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2823916708
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.337194507
Short name T651
Test name
Test status
Simulation time 547959332807 ps
CPU time 112.57 seconds
Started Jul 22 06:04:27 PM PDT 24
Finished Jul 22 06:06:20 PM PDT 24
Peak memory 201200 kb
Host smart-1ce04935-1407-433d-831a-e279f54f488f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337194507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.337194507
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2574518573
Short name T604
Test name
Test status
Simulation time 378231365937 ps
CPU time 936.5 seconds
Started Jul 22 06:04:41 PM PDT 24
Finished Jul 22 06:20:18 PM PDT 24
Peak memory 201280 kb
Host smart-b99895e9-963e-4490-b314-baa8d653a3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574518573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2574518573
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.301797503
Short name T192
Test name
Test status
Simulation time 321857326461 ps
CPU time 189.64 seconds
Started Jul 22 06:04:27 PM PDT 24
Finished Jul 22 06:07:37 PM PDT 24
Peak memory 201200 kb
Host smart-91b1f2f1-6455-4bfa-9cba-2d9d26994136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301797503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.301797503
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.817107847
Short name T468
Test name
Test status
Simulation time 168799844074 ps
CPU time 209.93 seconds
Started Jul 22 06:04:23 PM PDT 24
Finished Jul 22 06:07:53 PM PDT 24
Peak memory 201168 kb
Host smart-05734a0e-837a-4340-8a47-b1e343435014
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=817107847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.817107847
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.436222109
Short name T331
Test name
Test status
Simulation time 169448314494 ps
CPU time 198.79 seconds
Started Jul 22 06:07:42 PM PDT 24
Finished Jul 22 06:11:02 PM PDT 24
Peak memory 201232 kb
Host smart-fb378760-8a0c-4d15-9235-49bbdab16bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436222109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.436222109
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.124293622
Short name T381
Test name
Test status
Simulation time 163087003087 ps
CPU time 354.03 seconds
Started Jul 22 06:04:23 PM PDT 24
Finished Jul 22 06:10:18 PM PDT 24
Peak memory 201180 kb
Host smart-f2567424-f555-4d1c-bce5-bbb58419a444
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=124293622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.124293622
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3781975303
Short name T60
Test name
Test status
Simulation time 196257465424 ps
CPU time 449.49 seconds
Started Jul 22 06:04:31 PM PDT 24
Finished Jul 22 06:12:01 PM PDT 24
Peak memory 201200 kb
Host smart-17eb4a53-e9b8-49d6-84e4-fc0a95e832bf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781975303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3781975303
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2993102595
Short name T72
Test name
Test status
Simulation time 119035654533 ps
CPU time 433.99 seconds
Started Jul 22 06:04:40 PM PDT 24
Finished Jul 22 06:11:55 PM PDT 24
Peak memory 201648 kb
Host smart-e9870cc5-94bc-46e6-8fe3-1f8cbef43421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993102595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2993102595
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2295662276
Short name T695
Test name
Test status
Simulation time 31271484248 ps
CPU time 71 seconds
Started Jul 22 06:04:47 PM PDT 24
Finished Jul 22 06:05:59 PM PDT 24
Peak memory 201024 kb
Host smart-25b25137-0510-4f3a-a87e-9b22664f5a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295662276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2295662276
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2629957746
Short name T628
Test name
Test status
Simulation time 3477779886 ps
CPU time 9.41 seconds
Started Jul 22 06:04:32 PM PDT 24
Finished Jul 22 06:04:42 PM PDT 24
Peak memory 201052 kb
Host smart-ab124d30-e690-4d30-a071-d4e4a997d2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629957746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2629957746
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1761500253
Short name T84
Test name
Test status
Simulation time 4503599054 ps
CPU time 10.71 seconds
Started Jul 22 06:04:39 PM PDT 24
Finished Jul 22 06:04:51 PM PDT 24
Peak memory 216848 kb
Host smart-0a08ea8e-f768-42a8-a098-a80e9f4323b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761500253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1761500253
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1716283591
Short name T768
Test name
Test status
Simulation time 5888142962 ps
CPU time 15.61 seconds
Started Jul 22 06:04:36 PM PDT 24
Finished Jul 22 06:04:52 PM PDT 24
Peak memory 201088 kb
Host smart-334580a8-f528-41d5-a13f-1833e62a437d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716283591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1716283591
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.651365441
Short name T669
Test name
Test status
Simulation time 164256808616 ps
CPU time 345.99 seconds
Started Jul 22 06:04:40 PM PDT 24
Finished Jul 22 06:10:27 PM PDT 24
Peak memory 201236 kb
Host smart-e1bc3806-c215-4b96-8825-42133fe78ec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651365441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.651365441
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.4236166560
Short name T510
Test name
Test status
Simulation time 386610036 ps
CPU time 1.08 seconds
Started Jul 22 06:06:43 PM PDT 24
Finished Jul 22 06:06:45 PM PDT 24
Peak memory 200980 kb
Host smart-f11bb733-1d3f-4f33-94e0-7824b3bd9e83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236166560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.4236166560
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3013265366
Short name T332
Test name
Test status
Simulation time 590505168491 ps
CPU time 729.08 seconds
Started Jul 22 06:06:44 PM PDT 24
Finished Jul 22 06:18:53 PM PDT 24
Peak memory 201240 kb
Host smart-648d7895-ef59-420b-aac0-55045ec28c0c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013265366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3013265366
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3968327665
Short name T741
Test name
Test status
Simulation time 162445253426 ps
CPU time 100.92 seconds
Started Jul 22 06:06:33 PM PDT 24
Finished Jul 22 06:08:15 PM PDT 24
Peak memory 201220 kb
Host smart-01ecbce6-b79b-4148-a47a-e85c44bc05f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968327665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3968327665
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3801282857
Short name T368
Test name
Test status
Simulation time 320741726176 ps
CPU time 709.67 seconds
Started Jul 22 06:06:34 PM PDT 24
Finished Jul 22 06:18:24 PM PDT 24
Peak memory 201208 kb
Host smart-b75d40c7-ae43-4924-b1df-426bb55754a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801282857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3801282857
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3017164338
Short name T609
Test name
Test status
Simulation time 492608221065 ps
CPU time 227.31 seconds
Started Jul 22 06:06:33 PM PDT 24
Finished Jul 22 06:10:21 PM PDT 24
Peak memory 201180 kb
Host smart-903bc60a-2bcc-43c1-984d-33fff6e5dc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017164338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3017164338
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.557877708
Short name T128
Test name
Test status
Simulation time 162389027022 ps
CPU time 95.68 seconds
Started Jul 22 06:06:33 PM PDT 24
Finished Jul 22 06:08:09 PM PDT 24
Peak memory 201204 kb
Host smart-f0b3eb19-9161-490d-8696-1ce504087003
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=557877708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.557877708
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1240800042
Short name T41
Test name
Test status
Simulation time 382108257171 ps
CPU time 227.82 seconds
Started Jul 22 06:06:33 PM PDT 24
Finished Jul 22 06:10:21 PM PDT 24
Peak memory 201204 kb
Host smart-55aeef39-f65e-494f-8a92-0e3099e5eef6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240800042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1240800042
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3791319348
Short name T642
Test name
Test status
Simulation time 404645835939 ps
CPU time 228.59 seconds
Started Jul 22 06:06:29 PM PDT 24
Finished Jul 22 06:10:18 PM PDT 24
Peak memory 201200 kb
Host smart-72cc788e-7a3d-4b02-97b3-74684bc8be0d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791319348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3791319348
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2336756972
Short name T649
Test name
Test status
Simulation time 88581003820 ps
CPU time 427.1 seconds
Started Jul 22 06:08:25 PM PDT 24
Finished Jul 22 06:15:33 PM PDT 24
Peak memory 201644 kb
Host smart-bdda3188-5778-48f7-89c8-21d50d9e2f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336756972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2336756972
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2829225025
Short name T28
Test name
Test status
Simulation time 43507814869 ps
CPU time 6.96 seconds
Started Jul 22 06:06:43 PM PDT 24
Finished Jul 22 06:06:50 PM PDT 24
Peak memory 201056 kb
Host smart-b14bf99a-43da-4e8f-b17b-a5778482ecdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829225025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2829225025
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.356089325
Short name T781
Test name
Test status
Simulation time 4282285226 ps
CPU time 3.3 seconds
Started Jul 22 06:08:26 PM PDT 24
Finished Jul 22 06:08:29 PM PDT 24
Peak memory 200884 kb
Host smart-cab85733-238e-4efa-93ac-f4b188f896f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356089325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.356089325
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3461042035
Short name T599
Test name
Test status
Simulation time 5982434809 ps
CPU time 3.95 seconds
Started Jul 22 06:07:59 PM PDT 24
Finished Jul 22 06:08:03 PM PDT 24
Peak memory 201064 kb
Host smart-db62ab85-12e3-4911-b43b-587835fe809d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461042035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3461042035
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.411760491
Short name T590
Test name
Test status
Simulation time 383032236994 ps
CPU time 240.63 seconds
Started Jul 22 06:06:43 PM PDT 24
Finished Jul 22 06:10:44 PM PDT 24
Peak memory 201184 kb
Host smart-7f92d477-2a3a-4824-8f1a-5d2a2cdc0a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411760491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
411760491
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.340349718
Short name T750
Test name
Test status
Simulation time 44518237851 ps
CPU time 27.27 seconds
Started Jul 22 06:06:44 PM PDT 24
Finished Jul 22 06:07:11 PM PDT 24
Peak memory 209504 kb
Host smart-61f567f3-fd8c-4692-9989-0afa544799b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340349718 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.340349718
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.867028880
Short name T567
Test name
Test status
Simulation time 378761539 ps
CPU time 0.83 seconds
Started Jul 22 06:06:54 PM PDT 24
Finished Jul 22 06:06:56 PM PDT 24
Peak memory 201004 kb
Host smart-1a67520f-364e-4ce5-ae79-ad9a15ae0c95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867028880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.867028880
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2080019583
Short name T317
Test name
Test status
Simulation time 339363482689 ps
CPU time 193.46 seconds
Started Jul 22 06:08:25 PM PDT 24
Finished Jul 22 06:11:39 PM PDT 24
Peak memory 201092 kb
Host smart-309d7216-353f-4f1c-a623-75951a5e9a22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080019583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2080019583
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.75963259
Short name T639
Test name
Test status
Simulation time 409925265096 ps
CPU time 910.53 seconds
Started Jul 22 06:06:43 PM PDT 24
Finished Jul 22 06:21:54 PM PDT 24
Peak memory 201240 kb
Host smart-87612323-5af2-434f-bf05-8c2b80db980c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75963259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.75963259
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1756294715
Short name T276
Test name
Test status
Simulation time 162284112616 ps
CPU time 185.58 seconds
Started Jul 22 06:07:55 PM PDT 24
Finished Jul 22 06:11:01 PM PDT 24
Peak memory 201204 kb
Host smart-31a0812d-45ed-4f86-82c5-5559458a7a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756294715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1756294715
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2032267850
Short name T740
Test name
Test status
Simulation time 330140089768 ps
CPU time 740.68 seconds
Started Jul 22 06:06:43 PM PDT 24
Finished Jul 22 06:19:04 PM PDT 24
Peak memory 201200 kb
Host smart-c1471327-5558-423f-a069-379336359cc3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032267850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2032267850
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2187701609
Short name T237
Test name
Test status
Simulation time 333676333232 ps
CPU time 755.64 seconds
Started Jul 22 06:06:42 PM PDT 24
Finished Jul 22 06:19:18 PM PDT 24
Peak memory 201288 kb
Host smart-7e4ee996-89a7-4139-a6fb-cfe7153c74e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187701609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2187701609
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3660934916
Short name T509
Test name
Test status
Simulation time 333090144117 ps
CPU time 809.27 seconds
Started Jul 22 06:06:42 PM PDT 24
Finished Jul 22 06:20:11 PM PDT 24
Peak memory 201240 kb
Host smart-5b73cdd1-59c2-4d09-a306-ea7e37b53b79
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660934916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3660934916
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1309090957
Short name T247
Test name
Test status
Simulation time 169245873039 ps
CPU time 85.26 seconds
Started Jul 22 06:08:35 PM PDT 24
Finished Jul 22 06:10:01 PM PDT 24
Peak memory 201232 kb
Host smart-c5beff40-1fba-4447-be31-2b3ba8329aa9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309090957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1309090957
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1543236805
Short name T451
Test name
Test status
Simulation time 398736222169 ps
CPU time 146.48 seconds
Started Jul 22 06:06:41 PM PDT 24
Finished Jul 22 06:09:07 PM PDT 24
Peak memory 201196 kb
Host smart-c0ad8f37-4a6e-4738-9be0-21f414a9815a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543236805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1543236805
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3099144751
Short name T433
Test name
Test status
Simulation time 103346826672 ps
CPU time 592.85 seconds
Started Jul 22 06:06:42 PM PDT 24
Finished Jul 22 06:16:36 PM PDT 24
Peak memory 201880 kb
Host smart-52532824-8606-4658-94ca-689f86a801e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099144751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3099144751
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1561977245
Short name T403
Test name
Test status
Simulation time 26223287578 ps
CPU time 31.92 seconds
Started Jul 22 06:06:42 PM PDT 24
Finished Jul 22 06:07:14 PM PDT 24
Peak memory 201040 kb
Host smart-8eb7253d-649f-440a-b76e-f59fa6c8fd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561977245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1561977245
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1950584432
Short name T154
Test name
Test status
Simulation time 4947247968 ps
CPU time 12.71 seconds
Started Jul 22 06:08:24 PM PDT 24
Finished Jul 22 06:08:38 PM PDT 24
Peak memory 201000 kb
Host smart-803decee-829e-4392-aaa8-7947afba06f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950584432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1950584432
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2140105500
Short name T619
Test name
Test status
Simulation time 5957238329 ps
CPU time 9.32 seconds
Started Jul 22 06:08:25 PM PDT 24
Finished Jul 22 06:08:35 PM PDT 24
Peak memory 201016 kb
Host smart-243c483e-aa49-48c3-95a2-c9c5797559b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140105500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2140105500
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2509381195
Short name T131
Test name
Test status
Simulation time 339633650915 ps
CPU time 270.62 seconds
Started Jul 22 06:06:55 PM PDT 24
Finished Jul 22 06:11:26 PM PDT 24
Peak memory 201312 kb
Host smart-60ff86d8-4e79-46a6-96fb-4d81cb63602f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509381195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2509381195
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.247006698
Short name T355
Test name
Test status
Simulation time 181645531202 ps
CPU time 86.33 seconds
Started Jul 22 06:06:46 PM PDT 24
Finished Jul 22 06:08:13 PM PDT 24
Peak memory 201412 kb
Host smart-2300690d-8bb6-4b7f-8bef-a73efe62f2e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247006698 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.247006698
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.588214228
Short name T752
Test name
Test status
Simulation time 459407740 ps
CPU time 0.83 seconds
Started Jul 22 06:06:54 PM PDT 24
Finished Jul 22 06:06:55 PM PDT 24
Peak memory 201132 kb
Host smart-2c154fb0-a510-4e1b-a937-576bb35c5f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588214228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.588214228
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3743381429
Short name T5
Test name
Test status
Simulation time 372336521581 ps
CPU time 828.35 seconds
Started Jul 22 06:06:54 PM PDT 24
Finished Jul 22 06:20:44 PM PDT 24
Peak memory 201244 kb
Host smart-2b42141d-6a2e-4d91-90fb-f9127bac67f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743381429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3743381429
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.4109523157
Short name T558
Test name
Test status
Simulation time 165640368264 ps
CPU time 195.62 seconds
Started Jul 22 06:06:56 PM PDT 24
Finished Jul 22 06:10:12 PM PDT 24
Peak memory 201204 kb
Host smart-d36dc137-b29c-442f-bdf3-d782ec86f31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109523157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.4109523157
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1931527128
Short name T465
Test name
Test status
Simulation time 506708205549 ps
CPU time 322.82 seconds
Started Jul 22 06:06:54 PM PDT 24
Finished Jul 22 06:12:18 PM PDT 24
Peak memory 201184 kb
Host smart-2b6c72b6-8a80-485b-a437-613af015f3ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931527128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1931527128
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.392868886
Short name T588
Test name
Test status
Simulation time 330413905115 ps
CPU time 331.58 seconds
Started Jul 22 06:06:53 PM PDT 24
Finished Jul 22 06:12:25 PM PDT 24
Peak memory 201160 kb
Host smart-38761a82-ef92-4ad2-8571-1f78b59b8153
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=392868886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.392868886
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.132928807
Short name T167
Test name
Test status
Simulation time 567578380036 ps
CPU time 1199.53 seconds
Started Jul 22 06:06:55 PM PDT 24
Finished Jul 22 06:26:55 PM PDT 24
Peak memory 201180 kb
Host smart-da11c48e-b86c-42c3-aa59-e6e3b1026f17
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132928807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.132928807
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.511719967
Short name T360
Test name
Test status
Simulation time 389418864236 ps
CPU time 837.65 seconds
Started Jul 22 06:08:42 PM PDT 24
Finished Jul 22 06:22:40 PM PDT 24
Peak memory 201216 kb
Host smart-0dd54aca-57fe-44f3-bec1-d752b0b299d8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511719967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.511719967
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2797869986
Short name T354
Test name
Test status
Simulation time 125033981678 ps
CPU time 709.85 seconds
Started Jul 22 06:06:54 PM PDT 24
Finished Jul 22 06:18:44 PM PDT 24
Peak memory 201656 kb
Host smart-efbf8f9e-8aaf-4b5d-aff4-5082f2b147b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797869986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2797869986
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2244149737
Short name T566
Test name
Test status
Simulation time 37170549125 ps
CPU time 21.32 seconds
Started Jul 22 06:06:53 PM PDT 24
Finished Jul 22 06:07:15 PM PDT 24
Peak memory 201056 kb
Host smart-394397b7-d865-4e4f-84c6-17b18e0a8efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244149737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2244149737
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3041575366
Short name T536
Test name
Test status
Simulation time 3868247682 ps
CPU time 9.33 seconds
Started Jul 22 06:08:16 PM PDT 24
Finished Jul 22 06:08:26 PM PDT 24
Peak memory 200980 kb
Host smart-cd7a074f-e7d5-4190-93df-c2321f18ab2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041575366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3041575366
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3498186535
Short name T554
Test name
Test status
Simulation time 5913407683 ps
CPU time 7.99 seconds
Started Jul 22 06:06:54 PM PDT 24
Finished Jul 22 06:07:03 PM PDT 24
Peak memory 201036 kb
Host smart-89e5f49f-8ea0-42e2-88d4-c5367f15189d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498186535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3498186535
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2254498083
Short name T260
Test name
Test status
Simulation time 438122346457 ps
CPU time 875.95 seconds
Started Jul 22 06:08:16 PM PDT 24
Finished Jul 22 06:22:52 PM PDT 24
Peak memory 201584 kb
Host smart-d4f5de92-5648-4105-a616-0e0ff5bc90ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254498083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2254498083
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.281681370
Short name T712
Test name
Test status
Simulation time 49960389895 ps
CPU time 149.9 seconds
Started Jul 22 06:06:55 PM PDT 24
Finished Jul 22 06:09:25 PM PDT 24
Peak memory 210024 kb
Host smart-0eb939ad-6957-4baa-9918-7c920cbde807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281681370 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.281681370
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3549093173
Short name T414
Test name
Test status
Simulation time 483075405 ps
CPU time 1.73 seconds
Started Jul 22 06:07:06 PM PDT 24
Finished Jul 22 06:07:09 PM PDT 24
Peak memory 200920 kb
Host smart-2f9882fd-e96f-47b5-a787-bba93b0fc9c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549093173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3549093173
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2177353977
Short name T130
Test name
Test status
Simulation time 323940142586 ps
CPU time 117.21 seconds
Started Jul 22 06:07:06 PM PDT 24
Finished Jul 22 06:09:04 PM PDT 24
Peak memory 201160 kb
Host smart-a3323b0b-9a80-46cf-aa6d-00af8f09c7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177353977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2177353977
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2873310697
Short name T572
Test name
Test status
Simulation time 165821363212 ps
CPU time 96.69 seconds
Started Jul 22 06:07:04 PM PDT 24
Finished Jul 22 06:08:41 PM PDT 24
Peak memory 201176 kb
Host smart-6c257c79-7fa1-4193-b4a1-1d841a3bab84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873310697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2873310697
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3501094382
Short name T548
Test name
Test status
Simulation time 498453788148 ps
CPU time 1163.72 seconds
Started Jul 22 06:07:22 PM PDT 24
Finished Jul 22 06:26:47 PM PDT 24
Peak memory 201224 kb
Host smart-9ec24751-21b6-40e4-bed8-fbe54f4cba93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501094382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3501094382
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3264606316
Short name T766
Test name
Test status
Simulation time 334700749731 ps
CPU time 762.32 seconds
Started Jul 22 06:08:47 PM PDT 24
Finished Jul 22 06:21:31 PM PDT 24
Peak memory 201216 kb
Host smart-97dfbea6-ee99-4f52-a4a9-30230b90cb67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264606316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3264606316
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3660303956
Short name T571
Test name
Test status
Simulation time 230244225589 ps
CPU time 516.66 seconds
Started Jul 22 06:07:03 PM PDT 24
Finished Jul 22 06:15:41 PM PDT 24
Peak memory 201276 kb
Host smart-f50961ba-2b5e-42e1-ab38-3b011cb2d11d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660303956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3660303956
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3388430599
Short name T422
Test name
Test status
Simulation time 582847100304 ps
CPU time 1303.21 seconds
Started Jul 22 06:08:47 PM PDT 24
Finished Jul 22 06:30:30 PM PDT 24
Peak memory 201192 kb
Host smart-552afe83-9293-4643-855e-84f059f1c859
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388430599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3388430599
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2623090694
Short name T221
Test name
Test status
Simulation time 126734843689 ps
CPU time 408.8 seconds
Started Jul 22 06:07:26 PM PDT 24
Finished Jul 22 06:14:15 PM PDT 24
Peak memory 201668 kb
Host smart-e3ad0273-fd66-4e58-acda-adcaca6392b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623090694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2623090694
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.964406558
Short name T500
Test name
Test status
Simulation time 23137525978 ps
CPU time 47.33 seconds
Started Jul 22 06:07:03 PM PDT 24
Finished Jul 22 06:07:51 PM PDT 24
Peak memory 201012 kb
Host smart-eb720230-3367-48cb-898c-2e39e8f39eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964406558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.964406558
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.881231873
Short name T484
Test name
Test status
Simulation time 5102835209 ps
CPU time 3.44 seconds
Started Jul 22 06:07:04 PM PDT 24
Finished Jul 22 06:07:08 PM PDT 24
Peak memory 201032 kb
Host smart-93935a8a-fcfd-4ed3-9b75-c6b9d7a335b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881231873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.881231873
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3337030337
Short name T421
Test name
Test status
Simulation time 5732343183 ps
CPU time 2.09 seconds
Started Jul 22 06:08:47 PM PDT 24
Finished Jul 22 06:08:50 PM PDT 24
Peak memory 201076 kb
Host smart-7d0bc27f-e96c-4659-81f4-e0165c2df0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337030337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3337030337
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.486499026
Short name T156
Test name
Test status
Simulation time 34187019590 ps
CPU time 7.18 seconds
Started Jul 22 06:07:05 PM PDT 24
Finished Jul 22 06:07:13 PM PDT 24
Peak memory 201032 kb
Host smart-3b9d42c6-9a13-46c3-a65d-d1ae324c21da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486499026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
486499026
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1246581367
Short name T557
Test name
Test status
Simulation time 85974657759 ps
CPU time 57.19 seconds
Started Jul 22 06:08:47 PM PDT 24
Finished Jul 22 06:09:44 PM PDT 24
Peak memory 209648 kb
Host smart-095f8bfc-8e7f-4412-86ca-21ec61934d0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246581367 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1246581367
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3317335930
Short name T24
Test name
Test status
Simulation time 354184695 ps
CPU time 0.8 seconds
Started Jul 22 06:07:13 PM PDT 24
Finished Jul 22 06:07:14 PM PDT 24
Peak memory 200988 kb
Host smart-c5d9d40c-6845-496e-9209-111d2ae44e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317335930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3317335930
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1541936335
Short name T307
Test name
Test status
Simulation time 324683566457 ps
CPU time 107.66 seconds
Started Jul 22 06:07:13 PM PDT 24
Finished Jul 22 06:09:01 PM PDT 24
Peak memory 201140 kb
Host smart-3b57f4bc-93bf-42ab-aefd-305845a38f64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541936335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1541936335
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1592322707
Short name T286
Test name
Test status
Simulation time 493767328602 ps
CPU time 587.48 seconds
Started Jul 22 06:07:04 PM PDT 24
Finished Jul 22 06:16:52 PM PDT 24
Peak memory 201276 kb
Host smart-b26123f1-5450-4fd1-af3f-42596a8a0066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592322707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1592322707
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.705271383
Short name T115
Test name
Test status
Simulation time 166919088710 ps
CPU time 193.93 seconds
Started Jul 22 06:08:48 PM PDT 24
Finished Jul 22 06:12:03 PM PDT 24
Peak memory 201212 kb
Host smart-cf6451e5-053c-470e-9b2c-c09849815cb2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=705271383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.705271383
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.4004106706
Short name T643
Test name
Test status
Simulation time 329102006476 ps
CPU time 768.01 seconds
Started Jul 22 06:07:04 PM PDT 24
Finished Jul 22 06:19:52 PM PDT 24
Peak memory 201208 kb
Host smart-d8ed9998-ffd5-400e-951d-abfe98df47ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004106706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.4004106706
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3260043720
Short name T535
Test name
Test status
Simulation time 325231609898 ps
CPU time 362.08 seconds
Started Jul 22 06:07:55 PM PDT 24
Finished Jul 22 06:13:57 PM PDT 24
Peak memory 201204 kb
Host smart-acc44d80-ac96-4870-910a-e2441e2fec55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260043720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3260043720
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2950918216
Short name T179
Test name
Test status
Simulation time 350280576653 ps
CPU time 100.18 seconds
Started Jul 22 06:07:04 PM PDT 24
Finished Jul 22 06:08:45 PM PDT 24
Peak memory 201252 kb
Host smart-a56f6225-c2c6-4c6b-a9fc-10912b2e5e97
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950918216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2950918216
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1067933803
Short name T714
Test name
Test status
Simulation time 393555867304 ps
CPU time 250.88 seconds
Started Jul 22 06:08:18 PM PDT 24
Finished Jul 22 06:12:29 PM PDT 24
Peak memory 201200 kb
Host smart-8c608eae-7b1b-4a94-9d6b-88054aa69271
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067933803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1067933803
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1895898378
Short name T796
Test name
Test status
Simulation time 41432549806 ps
CPU time 27.15 seconds
Started Jul 22 06:07:09 PM PDT 24
Finished Jul 22 06:07:37 PM PDT 24
Peak memory 201052 kb
Host smart-bced6e35-420b-4229-a576-766885464c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895898378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1895898378
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1171248244
Short name T502
Test name
Test status
Simulation time 3958061931 ps
CPU time 2.87 seconds
Started Jul 22 06:07:16 PM PDT 24
Finished Jul 22 06:07:19 PM PDT 24
Peak memory 201028 kb
Host smart-ccfe1c3f-5e00-4d16-9652-80560151cbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171248244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1171248244
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1978329611
Short name T358
Test name
Test status
Simulation time 5938495656 ps
CPU time 4.55 seconds
Started Jul 22 06:07:03 PM PDT 24
Finished Jul 22 06:07:08 PM PDT 24
Peak memory 201076 kb
Host smart-f64e112b-05a8-44cc-86db-672ce8de5c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978329611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1978329611
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1552078851
Short name T301
Test name
Test status
Simulation time 260680823054 ps
CPU time 614.1 seconds
Started Jul 22 06:07:11 PM PDT 24
Finished Jul 22 06:17:26 PM PDT 24
Peak memory 209900 kb
Host smart-e9786706-8da4-4422-a8e1-bd614191c7fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552078851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1552078851
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.4122941290
Short name T503
Test name
Test status
Simulation time 372853391 ps
CPU time 1.4 seconds
Started Jul 22 06:07:21 PM PDT 24
Finished Jul 22 06:07:23 PM PDT 24
Peak memory 201004 kb
Host smart-aac82c20-dde8-4dbf-ba01-34d6e67140dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122941290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.4122941290
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3054568853
Short name T583
Test name
Test status
Simulation time 163123561047 ps
CPU time 89.46 seconds
Started Jul 22 06:08:18 PM PDT 24
Finished Jul 22 06:09:47 PM PDT 24
Peak memory 201288 kb
Host smart-384aa284-a768-49d0-8bcc-4f50c19fcd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054568853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3054568853
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2360418079
Short name T133
Test name
Test status
Simulation time 166079757190 ps
CPU time 408.23 seconds
Started Jul 22 06:08:15 PM PDT 24
Finished Jul 22 06:15:04 PM PDT 24
Peak memory 201148 kb
Host smart-0592008e-54d7-4d31-a103-c0a11fb48279
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360418079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2360418079
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3205151885
Short name T330
Test name
Test status
Simulation time 161159994473 ps
CPU time 131.28 seconds
Started Jul 22 06:07:11 PM PDT 24
Finished Jul 22 06:09:23 PM PDT 24
Peak memory 201216 kb
Host smart-e99c6cf1-733c-4ef0-8af4-af2706ccf882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205151885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3205151885
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1896178370
Short name T622
Test name
Test status
Simulation time 502170028896 ps
CPU time 319.62 seconds
Started Jul 22 06:07:12 PM PDT 24
Finished Jul 22 06:12:32 PM PDT 24
Peak memory 201156 kb
Host smart-12c87580-b5d8-4479-ade7-7463195d7e0e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896178370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1896178370
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.839952837
Short name T511
Test name
Test status
Simulation time 364216676951 ps
CPU time 835.79 seconds
Started Jul 22 06:07:23 PM PDT 24
Finished Jul 22 06:21:19 PM PDT 24
Peak memory 201184 kb
Host smart-b23e0e14-69ad-4d04-bb3f-46709f96c560
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839952837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.839952837
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.4029178719
Short name T428
Test name
Test status
Simulation time 408849644813 ps
CPU time 459.71 seconds
Started Jul 22 06:07:21 PM PDT 24
Finished Jul 22 06:15:01 PM PDT 24
Peak memory 201168 kb
Host smart-bc24f3f7-d61d-44d8-a191-d164c9d65df4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029178719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.4029178719
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.338551040
Short name T473
Test name
Test status
Simulation time 89219246941 ps
CPU time 333.32 seconds
Started Jul 22 06:08:16 PM PDT 24
Finished Jul 22 06:13:50 PM PDT 24
Peak memory 201596 kb
Host smart-dcb273c2-cdf2-43f9-93b0-023bbcce541a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338551040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.338551040
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2430285249
Short name T743
Test name
Test status
Simulation time 45886453116 ps
CPU time 111.93 seconds
Started Jul 22 06:07:20 PM PDT 24
Finished Jul 22 06:09:12 PM PDT 24
Peak memory 201016 kb
Host smart-891a37a8-9821-4f4c-a71d-7f109e753e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430285249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2430285249
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2631558479
Short name T596
Test name
Test status
Simulation time 5232789639 ps
CPU time 4.73 seconds
Started Jul 22 06:07:19 PM PDT 24
Finished Jul 22 06:07:24 PM PDT 24
Peak memory 201072 kb
Host smart-95c8f626-07c1-444b-8697-b9a2288df04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631558479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2631558479
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.14983036
Short name T485
Test name
Test status
Simulation time 5595712579 ps
CPU time 13.73 seconds
Started Jul 22 06:07:12 PM PDT 24
Finished Jul 22 06:07:27 PM PDT 24
Peak memory 201040 kb
Host smart-2970c6d4-1523-4f5b-9a0d-3d0c6883a7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14983036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.14983036
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.4218786133
Short name T323
Test name
Test status
Simulation time 333050926385 ps
CPU time 657.32 seconds
Started Jul 22 06:07:21 PM PDT 24
Finished Jul 22 06:18:20 PM PDT 24
Peak memory 201228 kb
Host smart-6856c800-5dd5-47d5-81dd-52f294f48e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218786133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.4218786133
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.159895907
Short name T110
Test name
Test status
Simulation time 255303648567 ps
CPU time 220.42 seconds
Started Jul 22 06:07:21 PM PDT 24
Finished Jul 22 06:11:02 PM PDT 24
Peak memory 210296 kb
Host smart-fdbe3cb1-618e-4f5e-871b-6293bab49493
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159895907 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.159895907
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3762169385
Short name T412
Test name
Test status
Simulation time 334336677 ps
CPU time 1.29 seconds
Started Jul 22 06:07:43 PM PDT 24
Finished Jul 22 06:07:46 PM PDT 24
Peak memory 200996 kb
Host smart-99274ecf-875d-49f9-aaf0-39b5c0873d21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762169385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3762169385
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3371330201
Short name T581
Test name
Test status
Simulation time 165544445172 ps
CPU time 102.74 seconds
Started Jul 22 06:07:31 PM PDT 24
Finished Jul 22 06:09:15 PM PDT 24
Peak memory 201164 kb
Host smart-c2bc0599-5a5c-4103-8d7b-5673151cf222
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371330201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3371330201
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3982310781
Short name T534
Test name
Test status
Simulation time 164424329276 ps
CPU time 97.5 seconds
Started Jul 22 06:07:31 PM PDT 24
Finished Jul 22 06:09:09 PM PDT 24
Peak memory 201304 kb
Host smart-cf2436e1-051c-40e0-bcfb-890aa0a8ba2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982310781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3982310781
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.188993875
Short name T717
Test name
Test status
Simulation time 341066187095 ps
CPU time 831.79 seconds
Started Jul 22 06:07:43 PM PDT 24
Finished Jul 22 06:21:36 PM PDT 24
Peak memory 201212 kb
Host smart-74dd5c1e-ad22-4899-ab62-80c7fd2b166d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=188993875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.188993875
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1696382141
Short name T395
Test name
Test status
Simulation time 486829782615 ps
CPU time 294.66 seconds
Started Jul 22 06:07:21 PM PDT 24
Finished Jul 22 06:12:17 PM PDT 24
Peak memory 201232 kb
Host smart-8849df5c-a9e1-4d88-83ea-b49a3654a47d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696382141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1696382141
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1860852166
Short name T334
Test name
Test status
Simulation time 567455001920 ps
CPU time 230.1 seconds
Started Jul 22 06:07:30 PM PDT 24
Finished Jul 22 06:11:20 PM PDT 24
Peak memory 201180 kb
Host smart-c363a438-cccb-49d6-af1a-91f72983654c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860852166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1860852166
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.430848202
Short name T562
Test name
Test status
Simulation time 210240984965 ps
CPU time 436.25 seconds
Started Jul 22 06:07:32 PM PDT 24
Finished Jul 22 06:14:48 PM PDT 24
Peak memory 201200 kb
Host smart-98522309-2cc4-40b1-9948-7833bb46b352
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430848202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.430848202
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2831622563
Short name T654
Test name
Test status
Simulation time 90267093749 ps
CPU time 323.83 seconds
Started Jul 22 06:07:42 PM PDT 24
Finished Jul 22 06:13:08 PM PDT 24
Peak memory 201624 kb
Host smart-c8abcd1e-b61d-47df-aa9c-2456dc50d9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831622563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2831622563
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.281825469
Short name T630
Test name
Test status
Simulation time 31977679038 ps
CPU time 17.74 seconds
Started Jul 22 06:07:29 PM PDT 24
Finished Jul 22 06:07:47 PM PDT 24
Peak memory 201080 kb
Host smart-b8b6d27e-fdc4-492f-9141-6c103c739021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281825469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.281825469
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3857059865
Short name T404
Test name
Test status
Simulation time 2991144887 ps
CPU time 7.18 seconds
Started Jul 22 06:07:30 PM PDT 24
Finished Jul 22 06:07:38 PM PDT 24
Peak memory 201004 kb
Host smart-582282b0-0b37-4f48-899e-cec39dde6965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857059865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3857059865
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3881983620
Short name T668
Test name
Test status
Simulation time 5670074977 ps
CPU time 9.94 seconds
Started Jul 22 06:07:21 PM PDT 24
Finished Jul 22 06:07:32 PM PDT 24
Peak memory 201092 kb
Host smart-1383f444-f4e5-4ead-9636-ac366e6f3942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881983620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3881983620
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2188888239
Short name T773
Test name
Test status
Simulation time 360439887924 ps
CPU time 388.79 seconds
Started Jul 22 06:07:42 PM PDT 24
Finished Jul 22 06:14:13 PM PDT 24
Peak memory 201204 kb
Host smart-2db90287-8ed1-4ac2-9b21-673061a24af3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188888239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2188888239
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.841928948
Short name T22
Test name
Test status
Simulation time 295171261966 ps
CPU time 140.7 seconds
Started Jul 22 06:07:42 PM PDT 24
Finished Jul 22 06:10:04 PM PDT 24
Peak memory 201336 kb
Host smart-cf7463d9-fb48-4597-a95a-7d081069b170
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841928948 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.841928948
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.1098494437
Short name T788
Test name
Test status
Simulation time 354545887 ps
CPU time 0.82 seconds
Started Jul 22 06:07:52 PM PDT 24
Finished Jul 22 06:07:53 PM PDT 24
Peak memory 201008 kb
Host smart-86a6a636-9c5f-46b3-b136-e35a04275819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098494437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1098494437
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3672560152
Short name T233
Test name
Test status
Simulation time 163056006930 ps
CPU time 87.79 seconds
Started Jul 22 06:08:01 PM PDT 24
Finished Jul 22 06:09:29 PM PDT 24
Peak memory 201184 kb
Host smart-a67914e7-1e76-4f7a-b329-8c94a327298a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672560152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3672560152
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2787385
Short name T245
Test name
Test status
Simulation time 330261399804 ps
CPU time 374.08 seconds
Started Jul 22 06:07:43 PM PDT 24
Finished Jul 22 06:13:59 PM PDT 24
Peak memory 201208 kb
Host smart-3cb030dd-b013-4ab0-b050-63271185856a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2787385
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2101287977
Short name T198
Test name
Test status
Simulation time 492722895098 ps
CPU time 271 seconds
Started Jul 22 06:07:41 PM PDT 24
Finished Jul 22 06:12:13 PM PDT 24
Peak memory 201268 kb
Host smart-9d388cfc-518d-484e-8959-e7d7c303f304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101287977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2101287977
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.638026757
Short name T8
Test name
Test status
Simulation time 494236527075 ps
CPU time 611.24 seconds
Started Jul 22 06:07:42 PM PDT 24
Finished Jul 22 06:17:56 PM PDT 24
Peak memory 201224 kb
Host smart-b56250b6-dcae-4c21-9793-a785d60e914d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=638026757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.638026757
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.395632586
Short name T424
Test name
Test status
Simulation time 491860101670 ps
CPU time 923.27 seconds
Started Jul 22 06:07:53 PM PDT 24
Finished Jul 22 06:23:17 PM PDT 24
Peak memory 201280 kb
Host smart-a1769144-0401-4807-9511-3e87a7f2356d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395632586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.395632586
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.508311724
Short name T480
Test name
Test status
Simulation time 330815454919 ps
CPU time 747.19 seconds
Started Jul 22 06:07:41 PM PDT 24
Finished Jul 22 06:20:09 PM PDT 24
Peak memory 201216 kb
Host smart-8a946007-d70d-4998-8eb2-ac8b294ea1ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=508311724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.508311724
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.4138490037
Short name T236
Test name
Test status
Simulation time 554295537761 ps
CPU time 1303.03 seconds
Started Jul 22 06:07:41 PM PDT 24
Finished Jul 22 06:29:26 PM PDT 24
Peak memory 201268 kb
Host smart-169f3f95-ec34-4ae2-b89a-c69a0d6ffd32
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138490037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.4138490037
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.4253069454
Short name T11
Test name
Test status
Simulation time 197652097041 ps
CPU time 444.7 seconds
Started Jul 22 06:07:42 PM PDT 24
Finished Jul 22 06:15:08 PM PDT 24
Peak memory 201180 kb
Host smart-25a850e2-442e-451c-ad99-fff331c23dc3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253069454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.4253069454
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1347137472
Short name T216
Test name
Test status
Simulation time 80943841297 ps
CPU time 292.52 seconds
Started Jul 22 06:07:53 PM PDT 24
Finished Jul 22 06:12:46 PM PDT 24
Peak memory 201656 kb
Host smart-8b9e0bb9-a6d6-432d-aca1-d3269e4c8c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347137472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1347137472
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2234001032
Short name T495
Test name
Test status
Simulation time 22777118177 ps
CPU time 3.98 seconds
Started Jul 22 06:07:40 PM PDT 24
Finished Jul 22 06:07:45 PM PDT 24
Peak memory 201068 kb
Host smart-45c33fd1-5e1e-4049-b018-19d6022fc069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234001032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2234001032
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1297166637
Short name T682
Test name
Test status
Simulation time 4019237285 ps
CPU time 1.55 seconds
Started Jul 22 06:07:40 PM PDT 24
Finished Jul 22 06:07:42 PM PDT 24
Peak memory 201284 kb
Host smart-08f4cffa-92bf-4084-864f-fe9c9006eff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297166637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1297166637
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2354871954
Short name T504
Test name
Test status
Simulation time 6107063723 ps
CPU time 7.91 seconds
Started Jul 22 06:07:41 PM PDT 24
Finished Jul 22 06:07:50 PM PDT 24
Peak memory 201064 kb
Host smart-e510e7e2-3d41-4381-a8ac-06b299d80ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354871954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2354871954
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1589682174
Short name T43
Test name
Test status
Simulation time 210278654416 ps
CPU time 471.91 seconds
Started Jul 22 06:08:08 PM PDT 24
Finished Jul 22 06:16:00 PM PDT 24
Peak memory 201256 kb
Host smart-826f79a6-b088-4bc9-a644-a54a8ccac080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589682174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1589682174
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3017868790
Short name T123
Test name
Test status
Simulation time 63702741801 ps
CPU time 68.41 seconds
Started Jul 22 06:07:53 PM PDT 24
Finished Jul 22 06:09:02 PM PDT 24
Peak memory 209944 kb
Host smart-4c0da23e-71b3-4474-867d-e01bd0a58479
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017868790 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3017868790
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1039912463
Short name T745
Test name
Test status
Simulation time 525611108 ps
CPU time 0.89 seconds
Started Jul 22 06:08:00 PM PDT 24
Finished Jul 22 06:08:01 PM PDT 24
Peak memory 201012 kb
Host smart-98bd8645-7b46-4f0e-815e-f00ca9bc4850
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039912463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1039912463
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1152580827
Short name T698
Test name
Test status
Simulation time 495285627239 ps
CPU time 148.23 seconds
Started Jul 22 06:07:52 PM PDT 24
Finished Jul 22 06:10:20 PM PDT 24
Peak memory 201172 kb
Host smart-d39c2428-fc7b-464d-91fe-a539ea94670a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152580827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1152580827
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1811568971
Short name T249
Test name
Test status
Simulation time 566727699514 ps
CPU time 623.29 seconds
Started Jul 22 06:07:54 PM PDT 24
Finished Jul 22 06:18:18 PM PDT 24
Peak memory 201296 kb
Host smart-a1b80ce1-3f3c-47a4-a46b-1b84a9db53e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811568971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1811568971
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1686871800
Short name T256
Test name
Test status
Simulation time 486731538263 ps
CPU time 1160.6 seconds
Started Jul 22 06:07:55 PM PDT 24
Finished Jul 22 06:27:16 PM PDT 24
Peak memory 201172 kb
Host smart-203d2ecd-6214-4d11-984c-cc7a45b7102a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686871800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1686871800
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.10889184
Short name T721
Test name
Test status
Simulation time 162386608345 ps
CPU time 399.5 seconds
Started Jul 22 06:07:54 PM PDT 24
Finished Jul 22 06:14:34 PM PDT 24
Peak memory 201188 kb
Host smart-a96c1ad4-7bf3-451f-ac6a-ebb9def44fc8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=10889184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt
_fixed.10889184
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3402304741
Short name T239
Test name
Test status
Simulation time 163299017280 ps
CPU time 92.5 seconds
Started Jul 22 06:07:54 PM PDT 24
Finished Jul 22 06:09:27 PM PDT 24
Peak memory 201192 kb
Host smart-e3ba8a35-7ca1-4cf3-bdac-b30bb09ba50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402304741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3402304741
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2127360034
Short name T769
Test name
Test status
Simulation time 334019187302 ps
CPU time 220.68 seconds
Started Jul 22 06:07:52 PM PDT 24
Finished Jul 22 06:11:33 PM PDT 24
Peak memory 201156 kb
Host smart-10af5ad1-3dc0-49b6-ad50-b37c6976aebe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127360034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2127360034
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1388506169
Short name T279
Test name
Test status
Simulation time 186996533930 ps
CPU time 58.06 seconds
Started Jul 22 06:07:52 PM PDT 24
Finished Jul 22 06:08:51 PM PDT 24
Peak memory 201292 kb
Host smart-607deeeb-898e-4bc3-ad46-25d978ac1897
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388506169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1388506169
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.916253414
Short name T707
Test name
Test status
Simulation time 202939559086 ps
CPU time 115.64 seconds
Started Jul 22 06:08:09 PM PDT 24
Finished Jul 22 06:10:05 PM PDT 24
Peak memory 201204 kb
Host smart-faf50ed0-8a66-4660-9c92-d2fb92996f1c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916253414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.916253414
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3815400804
Short name T655
Test name
Test status
Simulation time 35383220070 ps
CPU time 74.12 seconds
Started Jul 22 06:07:52 PM PDT 24
Finished Jul 22 06:09:07 PM PDT 24
Peak memory 201052 kb
Host smart-8f357a2e-16d0-46b6-8a80-84a1407e4d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815400804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3815400804
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3012417138
Short name T683
Test name
Test status
Simulation time 5524946436 ps
CPU time 3.9 seconds
Started Jul 22 06:07:55 PM PDT 24
Finished Jul 22 06:07:59 PM PDT 24
Peak memory 201024 kb
Host smart-a523bbdf-37b7-469b-a705-490acb1985ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012417138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3012417138
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3241147622
Short name T772
Test name
Test status
Simulation time 5879133090 ps
CPU time 1.51 seconds
Started Jul 22 06:07:52 PM PDT 24
Finished Jul 22 06:07:54 PM PDT 24
Peak memory 201088 kb
Host smart-55affd14-78f5-4a3d-9c66-bc6c5a78229e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241147622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3241147622
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3080005821
Short name T232
Test name
Test status
Simulation time 177583680877 ps
CPU time 113.44 seconds
Started Jul 22 06:08:04 PM PDT 24
Finished Jul 22 06:09:58 PM PDT 24
Peak memory 201220 kb
Host smart-9b7fe82e-d769-4d69-8133-5f4a44fb2f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080005821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3080005821
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2746324275
Short name T757
Test name
Test status
Simulation time 40960519347 ps
CPU time 72.72 seconds
Started Jul 22 06:08:06 PM PDT 24
Finished Jul 22 06:09:19 PM PDT 24
Peak memory 209964 kb
Host smart-2af86171-da60-46e7-95a5-79db7ec44d2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746324275 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2746324275
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.800454847
Short name T371
Test name
Test status
Simulation time 333226847 ps
CPU time 0.83 seconds
Started Jul 22 06:08:26 PM PDT 24
Finished Jul 22 06:08:27 PM PDT 24
Peak memory 200956 kb
Host smart-0966d133-a5dd-45dc-bc20-ba99efea8ec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800454847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.800454847
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.491346833
Short name T306
Test name
Test status
Simulation time 561905930507 ps
CPU time 323.41 seconds
Started Jul 22 06:08:16 PM PDT 24
Finished Jul 22 06:13:40 PM PDT 24
Peak memory 201280 kb
Host smart-6902c70d-951a-4ad5-af26-b231790d7ced
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491346833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.491346833
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2919601767
Short name T573
Test name
Test status
Simulation time 162800024564 ps
CPU time 351.19 seconds
Started Jul 22 06:08:04 PM PDT 24
Finished Jul 22 06:13:56 PM PDT 24
Peak memory 201212 kb
Host smart-d37fffc1-9d71-44e0-a50c-b5f034ad29e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919601767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2919601767
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3348053884
Short name T674
Test name
Test status
Simulation time 334914512731 ps
CPU time 733.36 seconds
Started Jul 22 06:08:03 PM PDT 24
Finished Jul 22 06:20:16 PM PDT 24
Peak memory 201288 kb
Host smart-432452f0-ea96-432e-9d5c-a669f98d386b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348053884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3348053884
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.4204430075
Short name T438
Test name
Test status
Simulation time 495630094597 ps
CPU time 313.68 seconds
Started Jul 22 06:08:03 PM PDT 24
Finished Jul 22 06:13:17 PM PDT 24
Peak memory 201228 kb
Host smart-762d9d41-2686-4bcd-8a98-0f2b7c893b65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204430075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.4204430075
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2987830629
Short name T620
Test name
Test status
Simulation time 204064373944 ps
CPU time 68.53 seconds
Started Jul 22 06:08:03 PM PDT 24
Finished Jul 22 06:09:12 PM PDT 24
Peak memory 201216 kb
Host smart-f6369531-f77f-4374-ab48-fb82c9b721be
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987830629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2987830629
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3845212343
Short name T460
Test name
Test status
Simulation time 25926267505 ps
CPU time 58.55 seconds
Started Jul 22 06:08:14 PM PDT 24
Finished Jul 22 06:09:13 PM PDT 24
Peak memory 201048 kb
Host smart-40e7a916-1597-4bd7-ae3a-badfdf7353f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845212343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3845212343
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1408882255
Short name T390
Test name
Test status
Simulation time 5360492587 ps
CPU time 11.66 seconds
Started Jul 22 06:08:11 PM PDT 24
Finished Jul 22 06:08:23 PM PDT 24
Peak memory 200952 kb
Host smart-fbfe8c26-04c9-4e48-87f5-ab6168cbda8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408882255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1408882255
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1969265881
Short name T420
Test name
Test status
Simulation time 5713538727 ps
CPU time 3.71 seconds
Started Jul 22 06:08:04 PM PDT 24
Finished Jul 22 06:08:08 PM PDT 24
Peak memory 201040 kb
Host smart-88b28003-0f38-4d19-8aec-a9dbf0b785da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969265881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1969265881
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.4066398827
Short name T206
Test name
Test status
Simulation time 46034935049 ps
CPU time 113.04 seconds
Started Jul 22 06:08:14 PM PDT 24
Finished Jul 22 06:10:07 PM PDT 24
Peak memory 217472 kb
Host smart-43716161-bbbb-4359-aa25-2025b075548f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066398827 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.4066398827
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1743269213
Short name T607
Test name
Test status
Simulation time 286265145 ps
CPU time 1.22 seconds
Started Jul 22 06:04:46 PM PDT 24
Finished Jul 22 06:04:48 PM PDT 24
Peak memory 201012 kb
Host smart-bd129c4f-f959-4e0d-b166-24c8fde66bd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743269213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1743269213
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.213851330
Short name T349
Test name
Test status
Simulation time 190701169788 ps
CPU time 407.28 seconds
Started Jul 22 06:04:31 PM PDT 24
Finished Jul 22 06:11:19 PM PDT 24
Peak memory 201212 kb
Host smart-dcaf6fa3-eae8-486f-b6ea-6eb3369e2a7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213851330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.213851330
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.4045308813
Short name T267
Test name
Test status
Simulation time 342968904977 ps
CPU time 760.08 seconds
Started Jul 22 06:04:38 PM PDT 24
Finished Jul 22 06:17:19 PM PDT 24
Peak memory 201172 kb
Host smart-bb7e8727-f42e-4599-8b8c-766f4668dab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045308813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.4045308813
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3025069968
Short name T749
Test name
Test status
Simulation time 493538747839 ps
CPU time 1188.86 seconds
Started Jul 22 06:04:39 PM PDT 24
Finished Jul 22 06:24:29 PM PDT 24
Peak memory 201244 kb
Host smart-c9567cc2-a2c5-4e10-9bad-e7af3d1cb4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025069968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3025069968
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1456416891
Short name T542
Test name
Test status
Simulation time 159742791485 ps
CPU time 168.83 seconds
Started Jul 22 06:05:03 PM PDT 24
Finished Jul 22 06:07:53 PM PDT 24
Peak memory 201188 kb
Host smart-98e98014-ab25-4b3f-8c08-2ed0a175a86e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456416891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1456416891
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3564469496
Short name T124
Test name
Test status
Simulation time 329788233734 ps
CPU time 190.11 seconds
Started Jul 22 06:04:43 PM PDT 24
Finished Jul 22 06:07:54 PM PDT 24
Peak memory 201268 kb
Host smart-69c8b0a3-2229-4002-98a5-5ae22240390b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564469496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3564469496
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3273931949
Short name T478
Test name
Test status
Simulation time 162455176952 ps
CPU time 95.05 seconds
Started Jul 22 06:04:32 PM PDT 24
Finished Jul 22 06:06:08 PM PDT 24
Peak memory 201220 kb
Host smart-06666076-7768-49f5-acab-0df570f67d1f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273931949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3273931949
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1129545853
Short name T475
Test name
Test status
Simulation time 180470912521 ps
CPU time 280.3 seconds
Started Jul 22 06:04:43 PM PDT 24
Finished Jul 22 06:09:24 PM PDT 24
Peak memory 201328 kb
Host smart-216daf7a-b54b-4aef-a602-b7ba3c54c573
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129545853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1129545853
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2117965126
Short name T790
Test name
Test status
Simulation time 588737150538 ps
CPU time 623.08 seconds
Started Jul 22 06:04:37 PM PDT 24
Finished Jul 22 06:15:01 PM PDT 24
Peak memory 201164 kb
Host smart-7622c2d5-b713-410b-8e15-3e1c93808e18
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117965126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2117965126
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.15283227
Short name T353
Test name
Test status
Simulation time 81771090300 ps
CPU time 385.49 seconds
Started Jul 22 06:04:39 PM PDT 24
Finished Jul 22 06:11:05 PM PDT 24
Peak memory 201640 kb
Host smart-274e3a40-2752-4c2e-b436-70f3cfec729a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15283227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.15283227
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.604044802
Short name T549
Test name
Test status
Simulation time 35597880688 ps
CPU time 10.3 seconds
Started Jul 22 06:04:42 PM PDT 24
Finished Jul 22 06:04:52 PM PDT 24
Peak memory 201080 kb
Host smart-9c28130a-61bf-4801-a23e-02721cff07e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604044802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.604044802
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3226380456
Short name T756
Test name
Test status
Simulation time 3186002683 ps
CPU time 4.14 seconds
Started Jul 22 06:04:32 PM PDT 24
Finished Jul 22 06:04:36 PM PDT 24
Peak memory 201064 kb
Host smart-ff8c6e52-825d-422f-9089-3aa38f0df8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226380456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3226380456
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.530899230
Short name T389
Test name
Test status
Simulation time 5788111037 ps
CPU time 13.77 seconds
Started Jul 22 06:07:42 PM PDT 24
Finished Jul 22 06:07:57 PM PDT 24
Peak memory 201044 kb
Host smart-d587793d-042e-4db0-b082-a30d5541b2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530899230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.530899230
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.23965025
Short name T259
Test name
Test status
Simulation time 491514763698 ps
CPU time 294 seconds
Started Jul 22 06:04:47 PM PDT 24
Finished Jul 22 06:09:42 PM PDT 24
Peak memory 201208 kb
Host smart-a0174436-e1d7-4d8a-91e5-b8ad31a81549
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23965025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.23965025
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1116814611
Short name T652
Test name
Test status
Simulation time 38230269445 ps
CPU time 45.6 seconds
Started Jul 22 06:04:40 PM PDT 24
Finished Jul 22 06:05:27 PM PDT 24
Peak memory 201360 kb
Host smart-221beff3-e6fa-460f-b095-469b42b2bf2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116814611 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1116814611
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2109130003
Short name T99
Test name
Test status
Simulation time 383357685 ps
CPU time 1.06 seconds
Started Jul 22 06:04:44 PM PDT 24
Finished Jul 22 06:04:46 PM PDT 24
Peak memory 201020 kb
Host smart-e965cf64-759c-48e4-9993-c2a0e89c13de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109130003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2109130003
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3285176704
Short name T202
Test name
Test status
Simulation time 321863068725 ps
CPU time 196.78 seconds
Started Jul 22 06:04:39 PM PDT 24
Finished Jul 22 06:07:57 PM PDT 24
Peak memory 201200 kb
Host smart-bad89555-8c95-4ee9-956b-f3d5b1b1d5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285176704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3285176704
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2955433354
Short name T710
Test name
Test status
Simulation time 168171996108 ps
CPU time 398.51 seconds
Started Jul 22 06:04:45 PM PDT 24
Finished Jul 22 06:11:24 PM PDT 24
Peak memory 201236 kb
Host smart-851fbe7b-f17a-4c5b-b537-f8ed0d2cd6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955433354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2955433354
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2259838951
Short name T194
Test name
Test status
Simulation time 483652777962 ps
CPU time 243.38 seconds
Started Jul 22 06:04:30 PM PDT 24
Finished Jul 22 06:08:34 PM PDT 24
Peak memory 201132 kb
Host smart-2d2b1ac6-ee62-4115-9bd5-0527363899c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259838951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2259838951
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.424240090
Short name T493
Test name
Test status
Simulation time 162930899863 ps
CPU time 108.95 seconds
Started Jul 22 06:04:41 PM PDT 24
Finished Jul 22 06:06:31 PM PDT 24
Peak memory 201208 kb
Host smart-832e5162-69af-4bc4-8386-00fa34ad013c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424240090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.424240090
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3538130758
Short name T398
Test name
Test status
Simulation time 323433729115 ps
CPU time 743.75 seconds
Started Jul 22 06:04:30 PM PDT 24
Finished Jul 22 06:16:54 PM PDT 24
Peak memory 201216 kb
Host smart-56fa145c-8bc8-4e34-a730-c9d7ccd1bb31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538130758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3538130758
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2018298563
Short name T605
Test name
Test status
Simulation time 342429827127 ps
CPU time 219.82 seconds
Started Jul 22 06:04:39 PM PDT 24
Finished Jul 22 06:08:20 PM PDT 24
Peak memory 201244 kb
Host smart-23247ed6-7108-4239-acfe-70cd5c5feec6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018298563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2018298563
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.965077664
Short name T506
Test name
Test status
Simulation time 395105116849 ps
CPU time 854.34 seconds
Started Jul 22 06:05:54 PM PDT 24
Finished Jul 22 06:20:09 PM PDT 24
Peak memory 201204 kb
Host smart-a2067850-dc46-4263-ba49-327477b8d266
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965077664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.965077664
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1040714007
Short name T373
Test name
Test status
Simulation time 101061690992 ps
CPU time 355.04 seconds
Started Jul 22 06:04:39 PM PDT 24
Finished Jul 22 06:10:35 PM PDT 24
Peak memory 201664 kb
Host smart-22808265-f7da-43e0-beeb-749f7449de69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040714007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1040714007
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2638055902
Short name T530
Test name
Test status
Simulation time 32329790289 ps
CPU time 19.15 seconds
Started Jul 22 06:04:31 PM PDT 24
Finished Jul 22 06:04:50 PM PDT 24
Peak memory 201120 kb
Host smart-ac533c24-0e5c-4d1b-b46a-383fd9736f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638055902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2638055902
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2851850916
Short name T454
Test name
Test status
Simulation time 2957856372 ps
CPU time 2.46 seconds
Started Jul 22 06:04:31 PM PDT 24
Finished Jul 22 06:04:34 PM PDT 24
Peak memory 201040 kb
Host smart-9e25e40a-40dc-4575-8c9a-0b861a08a668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851850916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2851850916
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3075464962
Short name T785
Test name
Test status
Simulation time 5775394217 ps
CPU time 4.11 seconds
Started Jul 22 06:04:40 PM PDT 24
Finished Jul 22 06:04:45 PM PDT 24
Peak memory 201088 kb
Host smart-252003f5-09a2-4cfd-aa4b-f16b657517c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075464962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3075464962
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2640591614
Short name T18
Test name
Test status
Simulation time 72394983102 ps
CPU time 48.9 seconds
Started Jul 22 06:04:40 PM PDT 24
Finished Jul 22 06:05:30 PM PDT 24
Peak memory 209540 kb
Host smart-9d895159-694d-410e-8221-74a7906de49e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640591614 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2640591614
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3111207879
Short name T492
Test name
Test status
Simulation time 338465937 ps
CPU time 1.39 seconds
Started Jul 22 06:04:43 PM PDT 24
Finished Jul 22 06:04:45 PM PDT 24
Peak memory 201060 kb
Host smart-13bc9198-9491-4854-ac7d-b8004f9ba5cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111207879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3111207879
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1863959437
Short name T165
Test name
Test status
Simulation time 194339649639 ps
CPU time 229.93 seconds
Started Jul 22 06:04:40 PM PDT 24
Finished Jul 22 06:08:31 PM PDT 24
Peak memory 201252 kb
Host smart-1c82333c-744f-4e0e-bf35-958fb67f64ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863959437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1863959437
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.473847640
Short name T499
Test name
Test status
Simulation time 164472885044 ps
CPU time 287.51 seconds
Started Jul 22 06:04:39 PM PDT 24
Finished Jul 22 06:09:28 PM PDT 24
Peak memory 201204 kb
Host smart-a7cc885c-4059-4860-8348-9f64ec68d6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473847640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.473847640
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1439675863
Short name T586
Test name
Test status
Simulation time 480866405096 ps
CPU time 1079.18 seconds
Started Jul 22 06:04:31 PM PDT 24
Finished Jul 22 06:22:31 PM PDT 24
Peak memory 201256 kb
Host smart-29bdce04-79f7-44c6-8ffd-9f3f4c23ba7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439675863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1439675863
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.672000774
Short name T309
Test name
Test status
Simulation time 324115472392 ps
CPU time 789.44 seconds
Started Jul 22 06:04:38 PM PDT 24
Finished Jul 22 06:17:49 PM PDT 24
Peak memory 201216 kb
Host smart-b990ee56-3aba-4077-a969-6ca2d72e09e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672000774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.672000774
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.908780873
Short name T779
Test name
Test status
Simulation time 320855256999 ps
CPU time 324.19 seconds
Started Jul 22 06:04:38 PM PDT 24
Finished Jul 22 06:10:03 PM PDT 24
Peak memory 201156 kb
Host smart-cae1256a-8d75-4a14-9e3e-fa3a05211d21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=908780873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.908780873
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.801781463
Short name T576
Test name
Test status
Simulation time 174932296986 ps
CPU time 50.08 seconds
Started Jul 22 06:04:45 PM PDT 24
Finished Jul 22 06:05:35 PM PDT 24
Peak memory 201272 kb
Host smart-931de223-4e43-4111-98a4-b8fe528fe92f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801781463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.801781463
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2164954423
Short name T6
Test name
Test status
Simulation time 583818172913 ps
CPU time 80.43 seconds
Started Jul 22 06:04:40 PM PDT 24
Finished Jul 22 06:06:01 PM PDT 24
Peak memory 201192 kb
Host smart-48e00787-b294-4362-9022-c3bccfece4c1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164954423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2164954423
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3838636104
Short name T163
Test name
Test status
Simulation time 38089665198 ps
CPU time 82.12 seconds
Started Jul 22 06:04:40 PM PDT 24
Finished Jul 22 06:06:03 PM PDT 24
Peak memory 201036 kb
Host smart-ae389e0e-cbad-4ef1-9bb7-5679c6d66c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838636104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3838636104
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.778496427
Short name T646
Test name
Test status
Simulation time 5116574473 ps
CPU time 1.84 seconds
Started Jul 22 06:04:40 PM PDT 24
Finished Jul 22 06:04:43 PM PDT 24
Peak memory 201044 kb
Host smart-6793bbf1-66a1-4fab-960d-514c3bff0aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778496427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.778496427
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.4024907076
Short name T744
Test name
Test status
Simulation time 5769998966 ps
CPU time 4.03 seconds
Started Jul 22 06:04:38 PM PDT 24
Finished Jul 22 06:04:42 PM PDT 24
Peak memory 201024 kb
Host smart-2e416322-527d-4459-900c-31493b84630b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024907076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.4024907076
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3303488545
Short name T598
Test name
Test status
Simulation time 334211992964 ps
CPU time 180.06 seconds
Started Jul 22 06:04:31 PM PDT 24
Finished Jul 22 06:07:32 PM PDT 24
Peak memory 201200 kb
Host smart-6bc5584f-29e7-48ae-a4f4-fdf2df3578dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303488545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3303488545
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2453593389
Short name T341
Test name
Test status
Simulation time 21184154143 ps
CPU time 43.62 seconds
Started Jul 22 06:04:32 PM PDT 24
Finished Jul 22 06:05:16 PM PDT 24
Peak memory 209440 kb
Host smart-bdc5f1a3-cff7-437b-94f1-b9e43e829ef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453593389 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2453593389
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1327024372
Short name T763
Test name
Test status
Simulation time 383785936 ps
CPU time 1.35 seconds
Started Jul 22 06:04:51 PM PDT 24
Finished Jul 22 06:04:53 PM PDT 24
Peak memory 200888 kb
Host smart-b5f287aa-7edd-465c-899a-b7e3dfa2eab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327024372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1327024372
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2169958494
Short name T282
Test name
Test status
Simulation time 498781849374 ps
CPU time 383.82 seconds
Started Jul 22 06:04:47 PM PDT 24
Finished Jul 22 06:11:11 PM PDT 24
Peak memory 201192 kb
Host smart-39ac8818-ffc9-4842-984e-379b9ee3f586
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169958494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2169958494
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.3546101475
Short name T337
Test name
Test status
Simulation time 368536398051 ps
CPU time 858.33 seconds
Started Jul 22 06:04:55 PM PDT 24
Finished Jul 22 06:19:14 PM PDT 24
Peak memory 201204 kb
Host smart-c0ccaf72-12f5-454f-9609-e64b2725be78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546101475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3546101475
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3676839379
Short name T614
Test name
Test status
Simulation time 327098574089 ps
CPU time 174.09 seconds
Started Jul 22 06:04:46 PM PDT 24
Finished Jul 22 06:07:41 PM PDT 24
Peak memory 201204 kb
Host smart-fcc35adc-edfa-440b-b42f-4fe996a99f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676839379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3676839379
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.340112782
Short name T38
Test name
Test status
Simulation time 490708129261 ps
CPU time 792.3 seconds
Started Jul 22 06:04:47 PM PDT 24
Finished Jul 22 06:18:00 PM PDT 24
Peak memory 201208 kb
Host smart-d4ce650c-5f98-4bd9-9f7b-c6732463a3a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=340112782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.340112782
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3062529123
Short name T624
Test name
Test status
Simulation time 160915554689 ps
CPU time 92.21 seconds
Started Jul 22 06:04:48 PM PDT 24
Finished Jul 22 06:06:21 PM PDT 24
Peak memory 201276 kb
Host smart-63d9a835-2287-40e3-923f-0f1138b089b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062529123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3062529123
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.624693471
Short name T529
Test name
Test status
Simulation time 492854351153 ps
CPU time 310.32 seconds
Started Jul 22 06:04:42 PM PDT 24
Finished Jul 22 06:09:54 PM PDT 24
Peak memory 201220 kb
Host smart-5e6de308-c933-400d-bf15-1b4306d172ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=624693471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.624693471
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2985954982
Short name T429
Test name
Test status
Simulation time 580375246365 ps
CPU time 396.28 seconds
Started Jul 22 06:04:45 PM PDT 24
Finished Jul 22 06:11:22 PM PDT 24
Peak memory 201132 kb
Host smart-4094eccd-e76c-4353-a6f2-b79967ca231f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985954982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2985954982
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2588208013
Short name T73
Test name
Test status
Simulation time 75237333922 ps
CPU time 388.39 seconds
Started Jul 22 06:04:50 PM PDT 24
Finished Jul 22 06:11:20 PM PDT 24
Peak memory 201736 kb
Host smart-d067be7b-6824-4d66-ab9d-d51b7631893b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588208013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2588208013
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1762929284
Short name T443
Test name
Test status
Simulation time 42509662894 ps
CPU time 101.43 seconds
Started Jul 22 06:04:50 PM PDT 24
Finished Jul 22 06:06:33 PM PDT 24
Peak memory 201036 kb
Host smart-b204e1b0-764a-4759-9b5f-a139298a62a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762929284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1762929284
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.723209974
Short name T671
Test name
Test status
Simulation time 4167420350 ps
CPU time 9.38 seconds
Started Jul 22 06:05:54 PM PDT 24
Finished Jul 22 06:06:04 PM PDT 24
Peak memory 201068 kb
Host smart-cd3f226c-7b49-42b0-a026-07ee52b24793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723209974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.723209974
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1632677059
Short name T31
Test name
Test status
Simulation time 5934680440 ps
CPU time 4.75 seconds
Started Jul 22 06:04:40 PM PDT 24
Finished Jul 22 06:04:46 PM PDT 24
Peak memory 201068 kb
Host smart-875b20dd-5748-4f6d-aeb6-2f16b24ad3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632677059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1632677059
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.488417467
Short name T298
Test name
Test status
Simulation time 332883382168 ps
CPU time 818.41 seconds
Started Jul 22 06:04:48 PM PDT 24
Finished Jul 22 06:18:27 PM PDT 24
Peak memory 201172 kb
Host smart-0633eb89-035c-4742-833c-c8ab9cc653ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488417467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.488417467
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1760069297
Short name T20
Test name
Test status
Simulation time 176365226510 ps
CPU time 73.53 seconds
Started Jul 22 06:04:51 PM PDT 24
Finished Jul 22 06:06:06 PM PDT 24
Peak memory 210732 kb
Host smart-8a3d67bc-d3c9-4225-bb6a-3115124c5bbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760069297 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1760069297
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2842983373
Short name T615
Test name
Test status
Simulation time 290452995 ps
CPU time 0.82 seconds
Started Jul 22 06:04:53 PM PDT 24
Finished Jul 22 06:04:55 PM PDT 24
Peak memory 200960 kb
Host smart-27150db4-97cb-4aee-819a-59dbc9e8b5b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842983373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2842983373
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3306133815
Short name T200
Test name
Test status
Simulation time 346510672286 ps
CPU time 155.8 seconds
Started Jul 22 06:04:53 PM PDT 24
Finished Jul 22 06:07:30 PM PDT 24
Peak memory 201304 kb
Host smart-789b0b6a-6bf2-4932-968c-60a9c1796e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306133815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3306133815
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.4113527302
Short name T720
Test name
Test status
Simulation time 492763152076 ps
CPU time 547.75 seconds
Started Jul 22 06:04:55 PM PDT 24
Finished Jul 22 06:14:03 PM PDT 24
Peak memory 201264 kb
Host smart-d6e533b3-5fbe-43d2-8621-aea76dae4f01
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113527302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.4113527302
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1360489009
Short name T293
Test name
Test status
Simulation time 168112380368 ps
CPU time 380.72 seconds
Started Jul 22 06:04:49 PM PDT 24
Finished Jul 22 06:11:10 PM PDT 24
Peak memory 201236 kb
Host smart-1ec79050-785b-44da-95a1-46d48b1220a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360489009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1360489009
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.46315556
Short name T705
Test name
Test status
Simulation time 333919452152 ps
CPU time 798.98 seconds
Started Jul 22 06:04:54 PM PDT 24
Finished Jul 22 06:18:14 PM PDT 24
Peak memory 201204 kb
Host smart-499cf45f-3f85-475a-ac8c-ffbf270bca9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=46315556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed.46315556
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2198153626
Short name T348
Test name
Test status
Simulation time 371156028426 ps
CPU time 215.17 seconds
Started Jul 22 06:05:43 PM PDT 24
Finished Jul 22 06:09:19 PM PDT 24
Peak memory 201292 kb
Host smart-e4b51cea-c08f-44aa-8ffb-bba7b9974841
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198153626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2198153626
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1251896877
Short name T589
Test name
Test status
Simulation time 600193912456 ps
CPU time 1378.96 seconds
Started Jul 22 06:04:44 PM PDT 24
Finished Jul 22 06:27:44 PM PDT 24
Peak memory 201164 kb
Host smart-3592deb5-5dc6-43e8-9c08-5e4cf3da2687
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251896877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1251896877
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1566631494
Short name T220
Test name
Test status
Simulation time 98046328892 ps
CPU time 538.51 seconds
Started Jul 22 06:04:51 PM PDT 24
Finished Jul 22 06:13:50 PM PDT 24
Peak memory 201660 kb
Host smart-45adfecb-5bb9-4464-9fb3-0c1cae03db47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566631494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1566631494
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2877684808
Short name T448
Test name
Test status
Simulation time 38398652410 ps
CPU time 49.04 seconds
Started Jul 22 06:04:42 PM PDT 24
Finished Jul 22 06:05:31 PM PDT 24
Peak memory 201048 kb
Host smart-164ea59f-9774-4cda-a87e-684a3327a533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877684808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2877684808
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3127874523
Short name T23
Test name
Test status
Simulation time 3951643954 ps
CPU time 9.03 seconds
Started Jul 22 06:04:53 PM PDT 24
Finished Jul 22 06:05:03 PM PDT 24
Peak memory 201052 kb
Host smart-2d34a879-51e0-4461-973f-76e8d11eb89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127874523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3127874523
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.18625958
Short name T102
Test name
Test status
Simulation time 5807058490 ps
CPU time 4.4 seconds
Started Jul 22 06:04:47 PM PDT 24
Finished Jul 22 06:04:52 PM PDT 24
Peak memory 201076 kb
Host smart-d02f60eb-385e-4020-8eb8-0ca5564b10ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18625958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.18625958
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.176145674
Short name T789
Test name
Test status
Simulation time 1340697131304 ps
CPU time 1394.93 seconds
Started Jul 22 06:04:50 PM PDT 24
Finished Jul 22 06:28:06 PM PDT 24
Peak memory 209816 kb
Host smart-86b09065-13e2-44ee-b0d2-c1bc5f521c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176145674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.176145674
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2845999434
Short name T21
Test name
Test status
Simulation time 261198971689 ps
CPU time 209.83 seconds
Started Jul 22 06:04:50 PM PDT 24
Finished Jul 22 06:08:21 PM PDT 24
Peak memory 209460 kb
Host smart-59669293-b265-4314-b3f6-7e2c5dac73b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845999434 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2845999434
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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