Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1215440	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1185162

1

T1

1757

T2

6223

T3

4337

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2108747	1			T1	2852		T2	11944		T3	8252
values[0x0]	145510	1			T1	277		T2	374		T3	250
values[0x1]	146345	1			T1	254		T2	370		T3	220

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	974306	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1426296

1

T1

2090

T2

7473

T3

5221

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10046	1			T1	5		T2	75		T3	34
valid_sources[0x01]	11870	1			T1	11		T2	35		T3	20
valid_sources[0x02]	7032	1			T1	7		T2	32		T3	22
valid_sources[0x03]	21903	1			T1	17		T2	45		T3	27
valid_sources[0x04]	11538	1			T1	11		T2	16		T3	22
valid_sources[0x05]	9211	1			T1	6		T2	61		T3	27
valid_sources[0x06]	9800	1			T1	8		T2	47		T3	12
valid_sources[0x07]	11435	1			T1	4		T2	35		T3	23
valid_sources[0x08]	6804	1			T1	3		T2	48		T3	58
valid_sources[0x09]	6987	1			T1	1		T2	47		T3	38
valid_sources[0x0a]	8891	1			T1	26		T2	48		T3	18
valid_sources[0x0b]	13925	1			T1	6		T2	48		T3	40
valid_sources[0x0c]	10089	1			T1	21		T2	78		T3	29
valid_sources[0x0d]	6997	1			T1	13		T2	48		T3	20
valid_sources[0x0e]	18115	1			T1	16		T2	62		T3	35
valid_sources[0x0f]	7000	1			T1	11		T2	56		T3	35
valid_sources[0x10]	7177	1			T1	9		T2	48		T3	38
valid_sources[0x11]	6788	1			T1	7		T2	34		T3	24
valid_sources[0x12]	7187	1			T1	6		T2	20		T3	49
valid_sources[0x13]	7045	1			T1	8		T2	80		T3	26
valid_sources[0x14]	8004	1			T1	17		T2	66		T3	46
valid_sources[0x15]	7149	1			T1	9		T2	46		T3	43
valid_sources[0x16]	10960	1			T2	62		T3	29		T4	11
valid_sources[0x17]	6722	1			T1	6		T2	62		T3	40
valid_sources[0x18]	6832	1			T1	16		T2	72		T3	16
valid_sources[0x19]	7636	1			T1	2		T2	69		T3	38
valid_sources[0x1a]	9830	1			T1	11		T2	44		T3	47
valid_sources[0x1b]	9677	1			T1	10		T2	39		T3	49
valid_sources[0x1c]	15481	1			T1	5		T2	38		T3	26
valid_sources[0x1d]	7380	1			T1	18		T2	53		T3	21
valid_sources[0x1e]	7568	1			T1	14		T2	51		T3	39
valid_sources[0x1f]	6839	1			T1	12		T2	60		T3	45
valid_sources[0x20]	7111	1			T1	2		T2	32		T3	43
valid_sources[0x21]	7199	1			T1	10		T2	42		T3	25
valid_sources[0x22]	7753	1			T1	3		T2	24		T3	29
valid_sources[0x23]	20067	1			T1	6		T2	47		T3	77
valid_sources[0x24]	7083	1			T1	30		T2	57		T3	17
valid_sources[0x25]	13735	1			T1	14		T2	35		T3	42
valid_sources[0x26]	14424	1			T1	6		T2	73		T3	40
valid_sources[0x27]	7008	1			T1	8		T2	36		T3	18
valid_sources[0x28]	7166	1			T1	5		T2	41		T3	44
valid_sources[0x29]	9551	1			T1	7		T2	29		T3	27
valid_sources[0x2a]	7212	1			T1	11		T2	45		T3	36
valid_sources[0x2b]	7683	1			T1	12		T2	46		T3	42
valid_sources[0x2c]	11434	1			T1	191		T2	43		T3	39
valid_sources[0x2d]	8008	1			T1	11		T2	36		T3	34
valid_sources[0x2e]	19806	1			T1	8		T2	52		T3	34
valid_sources[0x2f]	7366	1			T1	15		T2	40		T3	32
valid_sources[0x30]	15452	1			T1	7		T2	48		T3	18
valid_sources[0x31]	11967	1			T1	6		T2	89		T3	32
valid_sources[0x32]	7000	1			T1	9		T2	54		T3	26
valid_sources[0x33]	10161	1			T1	309		T2	35		T3	35
valid_sources[0x34]	7182	1			T1	17		T2	48		T3	47
valid_sources[0x35]	7116	1			T1	4		T2	55		T3	47
valid_sources[0x36]	6987	1			T1	6		T2	34		T3	22
valid_sources[0x37]	6933	1			T1	16		T2	59		T3	24
valid_sources[0x38]	8045	1			T1	17		T2	37		T3	51
valid_sources[0x39]	7034	1			T1	9		T2	54		T3	21
valid_sources[0x3a]	6925	1			T1	11		T2	37		T3	23
valid_sources[0x3b]	9740	1			T1	12		T2	37		T3	23
valid_sources[0x3c]	7210	1			T1	2		T2	71		T3	74
valid_sources[0x3d]	8185	1			T1	5		T2	52		T3	19
valid_sources[0x3e]	7037	1			T1	13		T2	39		T3	28
valid_sources[0x3f]	7160	1			T1	18		T2	51		T3	23
valid_sources[0x40]	7567	1			T1	5		T2	51		T3	31
valid_sources[0x41]	10924	1			T1	6		T2	55		T3	50
valid_sources[0x42]	7439	1			T1	13		T2	44		T3	51
valid_sources[0x43]	13952	1			T1	3		T2	79		T3	66
valid_sources[0x44]	7194	1			T1	5		T2	41		T3	26
valid_sources[0x45]	9701	1			T1	9		T2	49		T3	31
valid_sources[0x46]	9143	1			T1	9		T2	57		T3	35
valid_sources[0x47]	11346	1			T1	8		T2	51		T3	35
valid_sources[0x48]	8120	1			T1	12		T2	49		T3	12
valid_sources[0x49]	7142	1			T1	12		T2	59		T3	43
valid_sources[0x4a]	10033	1			T1	10		T2	54		T3	43
valid_sources[0x4b]	7124	1			T1	2		T2	66		T3	33
valid_sources[0x4c]	12886	1			T1	8		T2	50		T3	25
valid_sources[0x4d]	7253	1			T1	547		T2	22		T3	12
valid_sources[0x4e]	6834	1			T1	8		T2	29		T3	30
valid_sources[0x4f]	10026	1			T1	3		T2	69		T3	84
valid_sources[0x50]	8080	1			T1	6		T2	28		T3	33
valid_sources[0x51]	9810	1			T1	10		T2	53		T3	25
valid_sources[0x52]	6811	1			T1	14		T2	69		T3	24
valid_sources[0x53]	7985	1			T1	6		T2	45		T3	30
valid_sources[0x54]	7294	1			T1	6		T2	67		T3	38
valid_sources[0x55]	11180	1			T1	10		T2	33		T3	34
valid_sources[0x56]	10787	1			T1	20		T2	51		T3	31
valid_sources[0x57]	6977	1			T1	3		T2	67		T3	16
valid_sources[0x58]	19957	1			T1	7		T2	58		T3	37
valid_sources[0x59]	6934	1			T1	9		T2	52		T3	39
valid_sources[0x5a]	13111	1			T1	2		T2	58		T3	18
valid_sources[0x5b]	11839	1			T1	7		T2	65		T3	25
valid_sources[0x5c]	13744	1			T1	5		T2	41		T3	36
valid_sources[0x5d]	9972	1			T1	8		T2	37		T3	30
valid_sources[0x5e]	7390	1			T1	19		T2	32		T3	65
valid_sources[0x5f]	6991	1			T1	10		T2	59		T3	25
valid_sources[0x60]	7955	1			T1	11		T2	55		T3	84
valid_sources[0x61]	15886	1			T1	6		T2	37		T3	51
valid_sources[0x62]	11533	1			T1	8		T2	68		T3	22
valid_sources[0x63]	13310	1			T1	3		T2	50		T3	11
valid_sources[0x64]	11384	1			T1	5		T2	60		T3	41
valid_sources[0x65]	9621	1			T1	12		T2	47		T3	41
valid_sources[0x66]	7167	1			T1	6		T2	62		T3	47
valid_sources[0x67]	10355	1			T1	6		T2	50		T3	18
valid_sources[0x68]	7745	1			T1	3		T2	54		T3	17
valid_sources[0x69]	7536	1			T1	4		T2	52		T3	28
valid_sources[0x6a]	9857	1			T1	4		T2	39		T3	21
valid_sources[0x6b]	7324	1			T1	13		T2	69		T3	21
valid_sources[0x6c]	9370	1			T1	9		T2	40		T3	34
valid_sources[0x6d]	11002	1			T1	10		T2	45		T3	30
valid_sources[0x6e]	6886	1			T1	16		T2	50		T3	22
valid_sources[0x6f]	11817	1			T1	10		T2	60		T3	22
valid_sources[0x70]	10914	1			T1	10		T2	24		T3	33
valid_sources[0x71]	7747	1			T1	6		T2	47		T3	20
valid_sources[0x72]	11372	1			T1	10		T2	51		T3	33
valid_sources[0x73]	9453	1			T1	5		T2	49		T3	25
valid_sources[0x74]	11486	1			T1	8		T2	57		T3	14
valid_sources[0x75]	7066	1			T1	7		T2	47		T3	36
valid_sources[0x76]	7306	1			T1	6		T2	67		T3	26
valid_sources[0x77]	11879	1			T1	10		T2	50		T3	51
valid_sources[0x78]	6980	1			T1	8		T2	57		T3	28
valid_sources[0x79]	8057	1			T1	8		T2	47		T3	20
valid_sources[0x7a]	6937	1			T1	6		T2	48		T3	30
valid_sources[0x7b]	10990	1			T1	12		T2	62		T3	10
valid_sources[0x7c]	7480	1			T1	7		T2	56		T3	53
valid_sources[0x7d]	11381	1			T1	6		T2	42		T3	24
valid_sources[0x7e]	8981	1			T1	20		T2	82		T3	39
valid_sources[0x7f]	6918	1			T1	2		T2	53		T3	41
valid_sources[0x80]	11431	1			T1	7		T2	39		T3	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1049735

1

T1

1486

T2

5925

T3

4168

values[0x0]

all_enables

biggest_size

78686

1

T1

161

T2

187

T3

108

values[0x1]

all_enables

biggest_size

56741

1

T1

110

T2

111

T3

61