Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	2	15	88.24	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	2	15	88.24

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[ONEST_DONE]	0	1	1
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27342	1			T2	17		T3	13		T4	15
auto[PWRUP]	100	1			T39	1		T41	2		T23	1
auto[ONEST_0]	63	1			T39	1		T40	1		T41	1
auto[ONEST_021]	10	1			T45	1		T23	1		T203	1
auto[ONEST_1]	85	1			T39	3		T41	1		T45	2
auto[LP_0]	118	1			T40	2		T41	2		T45	3
auto[LP_021]	20	1			T40	1		T41	1		T204	1
auto[LP_1]	123	1			T40	3		T41	5		T45	2
auto[LP_EVAL]	44	1			T12	1		T30	1		T41	2
auto[LP_SLP]	477	1			T39	5		T40	9		T30	1
auto[LP_PWRUP]	33	1			T39	1		T41	1		T23	1
auto[NP_0]	150	1			T39	2		T40	4		T41	1
auto[NP_021]	28	1			T39	1		T40	1		T41	1
auto[NP_1]	139	1			T39	2		T40	1		T41	1
auto[NP_EVAL]	33	1			T40	1		T205	1		T206	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T31

1

T207

1

T44

1

min

26802

1

T2

17

T3

13

T4

15

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26808	1			T2	17		T3	13		T4	15
pow[0x1]	6	1			T208	1		T209	1		T210	2
pow[0x2]	13	1			T211	2		T212	1		T213	2
pow[0x3]	24	1			T23	1		T214	2		T204	2
pow[0x4]	53	1			T39	1		T40	2		T41	1
pow[0x5]	137	1			T39	1		T40	3		T45	3
pow[0x6]	238	1			T9	1		T39	4		T40	2
pow[0x7]	489	1			T39	9		T40	7		T41	9

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

191

1

T39

5

T40

1

T41

3

min

26353

1

T2

17

T3

13

T4

15

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26353	1			T2	17		T3	13		T4	15
pow[0x4]	1	1			T215	1		-	-		-	-
pow[0x5]	1	1			T216	1		-	-		-	-
pow[0x6]	3	1			T213	1		T217	1		T218	1
pow[0x7]	2	1			T207	1		T219	1		-	-
pow[0x8]	5	1			T213	1		T220	1		T221	1
pow[0x9]	8	1			T214	1		T208	2		T14	1
pow[0xa]	16	1			T39	1		T40	1		T208	1
pow[0xb]	39	1			T40	1		T205	1		T155	2
pow[0xc]	57	1			T39	1		T40	1		T41	1
pow[0xd]	127	1			T39	1		T40	2		T41	1
pow[0xe]	301	1			T9	1		T39	2		T40	6
pow[0xf]	550	1			T39	5		T40	9		T41	9