Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2334	1			T1	15		T8	4		T9	17
auto[PWRUP]	130	1			T1	1		T39	1		T40	1
auto[ONEST_0]	65	1			T39	2		T40	1		T45	1
auto[ONEST_021]	13	1			T41	1		T211	1		T212	1
auto[ONEST_1]	76	1			T39	1		T40	1		T45	1
auto[ONEST_DONE]	2	1			T350	1		T351	1		-	-
auto[LP_0]	126	1			T39	1		T30	1		T41	1
auto[LP_021]	27	1			T39	1		T40	1		T214	1
auto[LP_1]	152	1			T1	2		T9	1		T39	4
auto[LP_EVAL]	52	1			T9	2		T40	1		T30	1
auto[LP_SLP]	485	1			T9	1		T39	10		T27	1
auto[LP_PWRUP]	32	1			T40	1		T41	1		T205	1
auto[NP_0]	213	1			T1	1		T9	3		T39	3
auto[NP_021]	63	1			T41	1		T214	3		T204	2
auto[NP_1]	230	1			T1	2		T9	2		T39	1
auto[NP_EVAL]	37	1			T1	1		T9	1		T12	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

13

1

T213

1

T352

2

T42

1

min

1959

1

T1

19

T8

4

T9

22

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1973	1			T1	19		T8	4		T9	22
pow[0x1]	10	1			T1	1		T33	1		T208	1
pow[0x2]	12	1			T9	1		T23	1		T206	1
pow[0x3]	34	1			T45	1		T23	1		T204	1
pow[0x4]	60	1			T45	1		T214	2		T211	1
pow[0x5]	131	1			T39	5		T40	1		T41	1
pow[0x6]	272	1			T9	1		T39	4		T40	1
pow[0x7]	526	1			T9	1		T39	3		T40	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

209

1

T39

2

T40

3

T41

7

min

1388

1

T1

16

T8

4

T9

17

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1398	1			T1	16		T8	4		T9	17
pow[0x1]	15	1			T12	7		T30	1		T13	1
pow[0x2]	27	1			T27	1		T32	1		T33	1
pow[0x3]	44	1			T1	2		T9	6		T27	1
pow[0x4]	51	1			T1	2		T30	1		T32	1
pow[0x5]	2	1			T353	1		T219	1		-	-
pow[0x6]	1	1			T220	1		-	-		-	-
pow[0x7]	2	1			T354	1		T221	1		-	-
pow[0x8]	5	1			T354	1		T355	1		T356	1
pow[0x9]	5	1			T206	1		T352	1		T354	1
pow[0xa]	16	1			T155	1		T33	1		T212	1
pow[0xb]	41	1			T205	1		T206	1		T214	1
pow[0xc]	58	1			T39	1		T41	1		T45	2
pow[0xd]	169	1			T39	1		T40	1		T41	2
pow[0xe]	299	1			T1	1		T39	4		T40	4
pow[0xf]	584	1			T39	13		T40	6		T12	1