Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2318	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2358	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2574	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2673	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2618	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2617	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2572	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2598	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2490	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2658	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2514	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2680	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2475	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2600	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2648	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2440	0	0
adc_en_ctl_rd_A	2147483647	2002	0	0
adc_fsm_rst_rd_A	2147483647	2067	0	0
adc_intr_ctl_rd_A	2147483647	2722	0	0
adc_lp_sample_ctl_rd_A	2147483647	1881	0	0
adc_pd_ctl_rd_A	2147483647	2558	0	0
adc_sample_ctl_rd_A	2147483647	1804	0	0
adc_wakeup_ctl_rd_A	2147483647	2265	0	0
intr_enable_rd_A	2147483647	3006	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2318	0	0
T1	445043	35	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	15	0	0
T13	0	4	0	0
T14	0	25	0	0
T15	0	16	0	0
T16	0	28	0	0
T17	0	20	0	0
T18	0	25	0	0
T19	0	17	0	0
T20	0	4	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2358	0	0
T1	445043	28	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	27	0	0
T13	0	8	0	0
T14	0	32	0	0
T15	0	24	0	0
T16	0	14	0	0
T17	0	15	0	0
T18	0	12	0	0
T19	0	15	0	0
T20	0	3	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2574	0	0
T1	445043	22	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	30	0	0
T13	0	8	0	0
T14	0	21	0	0
T15	0	27	0	0
T16	0	14	0	0
T17	0	9	0	0
T18	0	20	0	0
T19	0	20	0	0
T20	0	9	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2673	0	0
T1	445043	23	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	25	0	0
T13	0	13	0	0
T14	0	23	0	0
T15	0	17	0	0
T16	0	35	0	0
T17	0	12	0	0
T18	0	26	0	0
T19	0	17	0	0
T20	0	12	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2618	0	0
T1	445043	37	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	31	0	0
T13	0	16	0	0
T14	0	46	0	0
T15	0	23	0	0
T16	0	31	0	0
T17	0	31	0	0
T18	0	10	0	0
T19	0	11	0	0
T20	0	6	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2617	0	0
T1	445043	24	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	31	0	0
T13	0	18	0	0
T14	0	21	0	0
T15	0	51	0	0
T16	0	28	0	0
T17	0	17	0	0
T18	0	11	0	0
T19	0	16	0	0
T20	0	11	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2572	0	0
T1	445043	30	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	25	0	0
T13	0	16	0	0
T14	0	41	0	0
T15	0	21	0	0
T16	0	31	0	0
T17	0	19	0	0
T18	0	11	0	0
T19	0	12	0	0
T20	0	4	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2598	0	0
T1	445043	11	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	37	0	0
T13	0	5	0	0
T14	0	33	0	0
T15	0	28	0	0
T16	0	27	0	0
T17	0	24	0	0
T18	0	23	0	0
T19	0	11	0	0
T20	0	30	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2490	0	0
T1	445043	16	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	22	0	0
T14	0	25	0	0
T15	0	34	0	0
T16	0	16	0	0
T17	0	20	0	0
T18	0	18	0	0
T19	0	19	0	0
T21	0	19	0	0
T22	0	11	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2658	0	0
T1	445043	18	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	18	0	0
T14	0	40	0	0
T15	0	33	0	0
T16	0	39	0	0
T17	0	13	0	0
T18	0	19	0	0
T19	0	25	0	0
T20	0	20	0	0
T21	0	23	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2514	0	0
T1	445043	28	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	14	0	0
T13	0	12	0	0
T14	0	25	0	0
T15	0	33	0	0
T16	0	31	0	0
T17	0	21	0	0
T18	0	18	0	0
T19	0	6	0	0
T20	0	13	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2680	0	0
T1	445043	15	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	14	0	0
T13	0	13	0	0
T14	0	28	0	0
T15	0	21	0	0
T16	0	40	0	0
T17	0	19	0	0
T18	0	17	0	0
T19	0	7	0	0
T20	0	7	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2475	0	0
T1	445043	17	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	34	0	0
T13	0	2	0	0
T14	0	27	0	0
T15	0	34	0	0
T16	0	26	0	0
T17	0	21	0	0
T18	0	10	0	0
T19	0	16	0	0
T20	0	5	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2600	0	0
T1	445043	17	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	36	0	0
T13	0	10	0	0
T14	0	21	0	0
T15	0	36	0	0
T16	0	25	0	0
T17	0	21	0	0
T18	0	20	0	0
T19	0	18	0	0
T20	0	16	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2648	0	0
T1	445043	16	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	43	0	0
T13	0	3	0	0
T14	0	37	0	0
T15	0	28	0	0
T16	0	33	0	0
T17	0	16	0	0
T18	0	23	0	0
T19	0	16	0	0
T20	0	7	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2440	0	0
T1	445043	26	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	27	0	0
T13	0	5	0	0
T14	0	45	0	0
T15	0	31	0	0
T16	0	10	0	0
T17	0	6	0	0
T18	0	11	0	0
T19	0	10	0	0
T20	0	12	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2002	0	0
T1	445043	18	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	8	0	0
T13	0	3	0	0
T14	0	34	0	0
T15	0	27	0	0
T16	0	23	0	0
T17	0	31	0	0
T18	0	21	0	0
T19	0	14	0	0
T20	0	5	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2067	0	0
T1	445043	36	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	27	0	0
T13	0	10	0	0
T14	0	25	0	0
T15	0	51	0	0
T16	0	29	0	0
T17	0	24	0	0
T18	0	14	0	0
T19	0	8	0	0
T20	0	14	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2722	0	0
T1	445043	22	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	40	0	0
T13	0	11	0	0
T14	0	18	0	0
T15	0	37	0	0
T16	0	16	0	0
T17	0	4	0	0
T18	0	12	0	0
T19	0	22	0	0
T20	0	2	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1881	0	0
T1	445043	27	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	20	0	0
T13	0	18	0	0
T14	0	37	0	0
T15	0	37	0	0
T16	0	9	0	0
T17	0	9	0	0
T18	0	16	0	0
T19	0	12	0	0
T20	0	7	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2558	0	0
T1	445043	23	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	22	0	0
T13	0	15	0	0
T14	0	20	0	0
T15	0	48	0	0
T16	0	29	0	0
T17	0	9	0	0
T18	0	21	0	0
T19	0	12	0	0
T20	0	6	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1804	0	0
T1	445043	20	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	37	0	0
T13	0	7	0	0
T14	0	35	0	0
T15	0	24	0	0
T16	0	25	0	0
T17	0	18	0	0
T18	0	15	0	0
T19	0	10	0	0
T20	0	7	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2265	0	0
T1	445043	28	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	25	0	0
T13	0	9	0	0
T14	0	49	0	0
T15	0	39	0	0
T16	0	38	0	0
T17	0	23	0	0
T18	0	23	0	0
T19	0	13	0	0
T20	0	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3006	0	0
T1	445043	56	0	0
T2	242076	0	0	0
T3	935958	0	0	0
T4	161708	0	0	0
T5	241997	0	0	0
T6	284499	0	0	0
T7	504593	0	0	0
T8	175307	0	0	0
T9	557355	0	0	0
T10	217060	0	0	0
T12	0	34	0	0
T13	0	18	0	0
T14	0	58	0	0
T15	0	66	0	0
T16	0	28	0	0
T23	0	28	0	0
T24	0	8	0	0
T25	0	7	0	0
T26	0	26	0	0