Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7190	1			T1	61		T4	20		T7	55
testmodes[AdcCtrlTestmodeNormal]	5849	1			T1	27		T3	1		T7	44
testmodes[AdcCtrlTestmodeLowpower]	5930	1			T1	11		T2	1		T5	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3874	1			T1	50		T4	19		T7	23
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1820	1			T1	6		T7	10		T43	18
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1387	1			T1	4		T7	21		T43	19
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1834	1			T1	9		T7	16		T43	20
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2251	1			T1	12		T7	18		T47	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1441	1			T1	6		T7	10		T43	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1373	1			T1	2		T7	16		T43	16
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1436	1			T1	8		T7	16		T43	20
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2856	1			T1	1		T5	1		T6	2