Design Hierarchy
dashboard | hierarchy | modlist | groups | tests | asserts

NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb 98.81 99.07 96.62 100.00 100.00 98.83 98.33
dut 98.81 99.07 96.62 100.00 100.00 98.83 98.33
adc_ctrl_csr_assert 96.00 96.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_adc_ctrl_core 99.83 100.00 99.76 100.00 99.37 100.00
u_adc_ctrl_fsm 99.75 100.00 100.00 100.00 98.73 100.00
u_adc_ctrl_fsm_sva 100.00 100.00
u_adc_ctrl_intr 99.00 100.00 96.00 100.00 100.00
i_adc_ctrl_intr_o 100.00 100.00 100.00 100.00 100.00
u_match_sync 93.75 100.00 75.00 100.00 100.00
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_oneshot_done_sync 100.00 100.00 100.00 100.00 100.00
prim_flop_2sync 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_reg 97.95 98.97 95.97 100.00 98.76 96.05
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