Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27194

1

T1

101

T2

27

T3

5

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23648

1

T1

96

T4

20

T5

33

auto[ADC_CTRL_FILTER_COND_OUT]

3546

1

T1

5

T2

27

T3

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20772

1

T1

96

T2

27

T3

5

auto[1]

6422

1

T1

5

T5

33

T6

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23099

1

T1

100

T2

13

T3

1

auto[1]

4095

1

T1

1

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	507	1			T1	5		T7	1		T43	6
values[0]	69	1			T199	13		T200	1		T156	28
values[1]	504	1			T1	5		T10	22		T13	17
values[2]	2969	1			T5	33		T108	1		T42	14
values[3]	788	1			T6	29		T12	3		T47	1
values[4]	889	1			T47	1		T13	11		T37	2
values[5]	601	1			T9	21		T29	1		T145	14
values[6]	698	1			T8	14		T11	3		T35	6
values[7]	810	1			T2	27		T3	5		T12	10
values[8]	634	1			T8	9		T37	1		T174	1
values[9]	1163	1			T6	6		T9	21		T11	14
minimum	17562	1			T1	91		T4	20		T7	141

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	741	1			T1	5		T10	22		T201	1
values[1]	2941	1			T5	33		T6	29		T12	3
values[2]	753	1			T53	19		T13	11		T28	23
values[3]	951	1			T47	1		T54	14		T145	14
values[4]	634	1			T9	21		T35	6		T13	4
values[5]	664	1			T8	14		T11	3		T29	1
values[6]	804	1			T2	27		T3	5		T8	9
values[7]	600	1			T174	1		T143	15		T202	1
values[8]	878	1			T6	6		T9	21		T11	14
values[9]	178	1			T28	7		T203	1		T180	1
minimum	18050	1			T1	96		T4	20		T7	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

4130

1

T1

1

T2

12

T5

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T37	2		T38	1		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	4		T10	11		T201	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1493	1			T5	33		T6	29		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	3		T47	1		T36	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T28	1		T37	1		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T53	9		T13	7		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T47	1		T54	6		T39	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T145	14		T204	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	21		T205	1		T176	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T35	5		T13	2		T23	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T29	1		T131	1		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T8	14		T11	3		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T8	5		T30	1		T132	38
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	13		T3	1		T8	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T174	1		T202	1		T206	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T143	8		T207	6		T189	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T6	6		T9	6		T11	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	15		T11	9		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T28	1		T180	1		T208	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T203	1		T209	2		T210	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17924	1			T1	96		T4	20		T7	142
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T37	1		T133	2		T211	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	1		T10	11		T41	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T13	9		T181	6		T212	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T36	1		T213	9		T214	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T28	11		T37	1		T33	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T53	10		T13	4		T28	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T54	8		T39	3		T214	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T135	12		T215	8		T216	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T205	3		T217	11		T148	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T35	1		T13	2		T23	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T216	9		T218	3		T74	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T219	9		T220	10		T217	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T30	8		T132	22		T221	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	14		T3	4		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T172	2		T222	9		T223	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T143	7		T207	11		T189	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T26	2		T186	4		T132	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T213	10		T54	8		T207	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T28	6		T208	13		T224	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T209	1		T210	7		T225	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T35	1		T13	5		T26	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	504	1			T1	5		T7	1		T43	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T226	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T199	1		T200	1		T156	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	8		T37	2		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T1	4		T10	11		T201	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1520	1			T5	33		T108	1		T42	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T36	5		T213	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T6	29		T28	1		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	3		T47	1		T53	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T47	1		T37	1		T54	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	7		T174	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	21		T29	1		T227	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T145	14		T202	1		T204	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T131	1		T205	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T8	14		T11	3		T35	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T30	1		T132	38		T214	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	13		T3	1		T12	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	5		T37	1		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	4		T143	8		T189	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	371	1			T6	6		T9	6		T11	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T9	15		T11	9		T108	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17437	1			T1	91		T4	20		T7	141
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T226	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T199	12		T156	13		T166	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	9		T37	1		T133	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T1	1		T10	11		T172	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T181	6		T212	23		T151	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T36	1		T213	9		T41	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T28	11		T33	2		T228	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T53	10		T28	10		T229	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T37	1		T54	8		T39	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	4		T135	12		T215	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T147	12		T148	11		T230	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T231	9		T232	3		T233	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T205	3		T217	11		T234	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T35	1		T13	2		T23	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T30	8		T132	22		T214	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	14		T3	4		T207	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T221	2		T172	2		T235	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T143	7		T189	6		T219	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T26	2		T28	6		T186	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T213	10		T54	8		T207	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T13	5		T26	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T37	2		T38	1		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	4		T10	12		T201	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T5	2		T6	2		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	1		T47	1		T36	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T28	12		T37	2		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T53	11		T13	5		T28	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T47	1		T54	9		T39	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T145	1		T204	1		T135	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	1		T205	4		T176	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T35	5		T13	3		T23	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T29	1		T131	1		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	1		T11	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	1		T30	9		T132	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	15		T3	5		T8	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T174	1		T202	1		T206	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T143	8		T207	13		T189	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T6	1		T9	1		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	1		T11	1		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T28	7		T180	1		T208	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T203	1		T209	2		T210	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18050	1			T1	96		T4	20		T7	142
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T37	1		T227	20		T146	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	1		T10	10		T236	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1161	1			T5	31		T6	27		T42	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	2		T36	1		T214	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T143	13		T177	8		T200	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T53	8		T13	6		T172	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T54	5		T39	2		T214	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T145	13		T136	7		T215	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T9	20		T217	8		T148	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T35	1		T13	1		T23	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T237	17		T218	2		T74	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	13		T11	2		T238	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	4		T132	36		T214	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	12		T8	3		T12	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T172	2		T227	1		T177	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T143	7		T207	4		T189	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T6	5		T9	5		T11	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	14		T11	8		T207	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T208	13		T224	13		T239	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T209	1		T210	8		T225	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	487	1			T1	5		T7	1		T43	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T226	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T199	13		T200	1		T156	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	12		T37	2		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T1	4		T10	12		T201	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T5	2		T108	1		T42	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T36	5		T213	10		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	2		T28	12		T33	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T12	1		T47	1		T53	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T47	1		T37	2		T54	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T13	5		T174	1		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T9	1		T29	1		T227	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T145	1		T202	1		T204	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T131	1		T205	4		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T8	1		T11	1		T35	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T30	9		T132	24		T214	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	15		T3	5		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T8	1		T37	1		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	1		T143	8		T189	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	385	1			T6	1		T9	1		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T9	1		T11	1		T108	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17562	1			T1	91		T4	20		T7	141
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T239	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T156	14		T166	2		T240	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T13	5		T37	1		T146	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T1	1		T10	10		T172	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T5	31		T42	12		T134	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T36	1		T236	13		T41	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	27		T143	13		T177	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	2		T53	8		T214	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T54	5		T39	2		T214	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	6		T136	7		T215	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	20		T227	14		T147	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T145	13		T231	10		T238	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T237	17		T217	8		T17	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	13		T11	2		T35	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T132	36		T214	1		T176	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	12		T12	9		T27	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T8	4		T172	2		T227	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T8	3		T143	7		T189	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T6	5		T9	5		T11	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	14		T11	8		T207	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

auto[0]

4130

1

T1

1

T2

12

T5

31

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27194

1

T1

101

T2

27

T3

5

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21243

1

T1

101

T3

5

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

5951

1

T2

27

T5

33

T6

35

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20882

1

T1

96

T4

20

T6

22

auto[1]

6312

1

T1

5

T2

27

T3

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23099

1

T1

100

T2

13

T3

1

auto[1]

4095

1

T1

1

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T142	1		T207	1		-	-
values[0]	25	1			T241	1		T242	24		-	-
values[1]	515	1			T11	12		T108	1		T130	9
values[2]	738	1			T6	6		T8	4		T47	1
values[3]	869	1			T13	17		T37	3		T54	14
values[4]	751	1			T1	5		T6	13		T10	22
values[5]	750	1			T2	27		T8	14		T26	8
values[6]	714	1			T3	5		T9	15		T108	1
values[7]	745	1			T9	21		T35	6		T133	3
values[8]	641	1			T11	5		T108	1		T37	1
values[9]	3396	1			T5	33		T6	16		T8	5
minimum	18048	1			T1	96		T4	20		T7	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	795	1			T11	12		T108	1		T27	3
values[1]	3025	1			T5	33		T6	6		T8	4
values[2]	689	1			T6	13		T12	10		T53	19
values[3]	871	1			T1	5		T2	27		T10	22
values[4]	673	1			T8	14		T29	1		T38	1
values[5]	699	1			T3	5		T9	15		T108	1
values[6]	700	1			T9	21		T142	1		T133	3
values[7]	635	1			T6	16		T11	5		T108	1
values[8]	921	1			T8	5		T9	6		T13	11
values[9]	129	1			T13	4		T23	14		T30	9
minimum	18057	1			T1	96		T4	20		T7	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

4130

1

T1

1

T2

12

T5

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	9		T108	1		T137	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T11	3		T27	3		T130	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T8	4		T47	1		T37	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1542	1			T5	33		T6	6		T42	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T39	5		T153	1		T139	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T6	13		T12	10		T53	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	4		T12	3		T26	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T2	13		T10	11		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T132	10		T243	17		T177	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T8	14		T29	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	1		T35	5		T213	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	15		T108	1		T14	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	21		T142	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T206	1		T171	13		T244	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	5		T37	1		T214	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	16		T108	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T8	5		T9	6		T13	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T28	1		T213	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T13	2		T23	8		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T30	1		T138	1		T245	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17923	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T146	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T137	1		T216	9		T232	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T229	17		T41	6		T207	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	2		T233	15		T149	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1091	1			T181	6		T212	23		T151	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T39	3		T139	13		T220	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T53	10		T246	12		T41	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	1		T26	2		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	14		T10	11		T13	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T132	8		T247	12		T232	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T248	2		T249	11		T149	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	4		T35	1		T213	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T14	3		T135	9		T250	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T133	2		T135	12		T251	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T171	10		T148	15		T199	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T214	7		T189	3		T199	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T74	10		T252	11		T253	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	4		T28	6		T186	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T28	10		T213	9		T33	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T13	2		T23	6		T189	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T30	8		T253	18		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T13	5		T26	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T142	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T207	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T241	1		T242	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	9		T108	1		T137	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	3		T130	9		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	4		T47	1		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T6	6		T27	3		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T37	2		T54	6		T132	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T13	8		T246	1		T41	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	4		T12	3		T172	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T6	13		T10	11		T12	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T26	6		T36	5		T132	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	13		T8	14		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	1		T213	1		T214	31
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	15		T108	1		T204	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	21		T35	5		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T206	1		T254	3		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	5		T37	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T108	1		T171	13		T175	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T8	5		T9	6		T13	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1630	1			T5	33		T6	16		T42	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17923	1			T1	96		T4	20		T7	142
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T242	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T137	1		T216	9		T155	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T229	17		T41	6		T207	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T37	1		T232	16		T233	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T132	10		T172	14		T215	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T37	1		T54	8		T132	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T13	9		T246	12		T41	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T172	7		T228	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T10	11		T53	10		T28	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T26	2		T36	1		T132	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T2	14		T14	3		T33	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	4		T213	10		T214	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T135	9		T255	14		T256	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T35	1		T133	2		T135	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T148	15		T199	12		T250	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T205	3		T214	7		T199	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T171	10		T209	1		T74	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	6		T23	6		T28	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1169	1			T28	10		T30	8		T181	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T13	5		T26	2