Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27194

1

T1

101

T2

27

T3

5

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23595

1

T1

96

T2

27

T3

5

auto[ADC_CTRL_FILTER_COND_OUT]

3599

1

T1

5

T6

35

T8

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21254

1

T1

101

T3

5

T4

20

auto[1]

5940

1

T2

27

T5

33

T6

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23099

1

T1

100

T2

13

T3

1

auto[1]

4095

1

T1

1

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	11	1			T142	1		T320	1		T321	9
values[0]	63	1			T39	1		T136	11		T232	10
values[1]	523	1			T1	5		T11	5		T108	1
values[2]	587	1			T26	8		T28	12		T201	1
values[3]	763	1			T6	13		T13	21		T28	18
values[4]	845	1			T8	5		T108	1		T202	1
values[5]	731	1			T2	27		T6	6		T47	1
values[6]	605	1			T3	5		T8	14		T10	22
values[7]	783	1			T6	16		T13	11		T30	9
values[8]	2885	1			T5	33		T8	4		T9	15
values[9]	1350	1			T9	27		T11	12		T12	3
minimum	18048	1			T1	96		T4	20		T7	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	645	1			T1	5		T11	5		T108	1
values[1]	728	1			T6	13		T13	21		T26	8
values[2]	839	1			T8	5		T28	7		T37	1
values[3]	755	1			T2	27		T108	1		T53	19
values[4]	756	1			T6	6		T47	1		T108	1
values[5]	601	1			T3	5		T6	16		T8	14
values[6]	2989	1			T5	33		T9	15		T12	10
values[7]	626	1			T8	4		T9	6		T229	18
values[8]	974	1			T9	21		T11	3		T12	3
values[9]	226	1			T11	9		T130	9		T36	6
minimum	18055	1			T1	96		T4	20		T7	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

4130

1

T1

1

T2

12

T5

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T11	5		T108	1		T37	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	4		T201	1		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	2		T28	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T6	13		T13	8		T26	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T28	1		T213	1		T221	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T8	5		T37	1		T214	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T2	13		T108	1		T27	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T53	9		T39	5		T236	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T47	1		T108	1		T37	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T6	6		T131	1		T132	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	1		T29	1		T186	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	16		T8	14		T10	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1484	1			T5	33		T9	15		T42	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	10		T13	7		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T8	4		T9	6		T204	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T229	1		T145	14		T202	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T9	21		T12	3		T35	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	3		T47	1		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T130	9		T36	5		T322	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T11	9		T246	1		T214	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17926	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T206	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T37	1		T232	3		T217	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T1	1		T135	12		T278	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	2		T28	10		T33	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	9		T26	2		T28	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T28	6		T213	10		T221	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T214	14		T147	12		T217	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	14		T189	6		T216	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T53	10		T39	3		T139	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T37	1		T54	8		T135	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T132	12		T41	6		T231	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T3	4		T186	4		T14	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T10	11		T213	9		T132	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1108	1			T181	6		T212	23		T151	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	4		T30	8		T143	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T219	9		T232	7		T148	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T229	17		T221	2		T172	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T35	1		T23	6		T132	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T41	1		T215	29		T216	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T36	1		T309	16		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T246	12		T214	7		T199	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T35	1		T13	5		T26	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T320	1		T321	5		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T142	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T39	1		T232	7		T218	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T136	11		T299	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	5		T108	1		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	4		T33	13		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T213	1		T174	1		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T26	6		T28	1		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	2		T28	2		T54	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T6	13		T13	8		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T108	1		T171	13		T189	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T8	5		T202	1		T236	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T2	13		T47	1		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	6		T53	9		T132	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	1		T29	1		T186	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	14		T10	11		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T205	1		T207	5		T146	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	16		T13	7		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1434	1			T5	33		T8	4		T9	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T12	10		T174	1		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	460	1			T9	27		T12	3		T23	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T11	12		T47	1		T246	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17923	1			T1	96		T4	20		T7	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T321	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T232	3		T218	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T299	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T37	1		T217	11		T233	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T1	1		T33	5		T278	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T213	10		T33	2		T152	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T26	2		T28	11		T135	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	2		T28	16		T54	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	9		T214	14		T147	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T171	10		T189	6		T216	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T251	13		T199	12		T77	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T2	14		T37	1		T135	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T53	10		T132	12		T39	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	4		T186	4		T14	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T10	11		T213	9		T41	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T205	3		T207	11		T260	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	4		T30	8		T143	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T35	1		T181	6		T212	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T229	17		T214	15		T215	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T23	6		T36	1		T132	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T246	12		T221	2		T214	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T13	5		T26	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	1		T108	1		T37	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	4		T201	1		T206	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	3		T28	11		T33	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	1		T13	12		T26	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T28	7		T213	11		T221	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T8	1		T37	1		T214	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T2	15		T108	1		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T53	11		T39	6		T236	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T47	1		T108	1		T37	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	1		T131	1		T132	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	5		T29	1		T186	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	1		T8	1		T10	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T5	2		T9	1		T42	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	1		T13	5		T30	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T8	1		T9	1		T204	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T229	18		T145	1		T202	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T9	1		T12	1		T35	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	1		T47	1		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T130	1		T36	5		T322	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T11	1		T246	13		T214	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18052	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T206	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	4		T145	11		T301	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	1		T136	10		T278	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	1		T172	5		T233	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	12		T13	5		T26	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T221	9		T152	5		T171	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	4		T214	15		T136	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T2	12		T27	2		T189	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T53	8		T39	2		T236	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T37	1		T54	5		T137	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	5		T132	16		T231	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T186	10		T14	2		T171	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	15		T8	13		T10	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1155	1			T5	31		T9	14		T42	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	9		T13	6		T143	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T8	3		T9	5		T136	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T145	13		T243	16		T172	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T9	20		T12	2		T35	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	2		T41	2		T215	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T130	8		T36	1		T322	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T11	8		T214	1		T264	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T218	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T320	1		T321	5		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T142	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T39	1		T232	6		T218	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T136	1		T299	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	1		T108	1		T37	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T1	4		T33	6		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T213	11		T174	1		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T26	7		T28	12		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	3		T28	18		T54	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T6	1		T13	12		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T108	1		T171	11		T189	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	1		T202	1		T236	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	15		T47	1		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T6	1		T53	11		T132	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	5		T29	1		T186	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	1		T10	12		T213	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T205	4		T207	12		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	1		T13	5		T30	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T5	2		T8	1		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	1		T174	1		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T9	2		T12	1		T23	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T11	2		T47	1		T246	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18048	1			T1	96		T4	20		T7	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T321	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T232	4		T218	2		T323	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T136	10		T299	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	4		T145	11		T301	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	1		T33	12		T278	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T152	5		T172	2		T233	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T26	1		T143	13		T177	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T13	1		T221	9		T172	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	12		T13	5		T214	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T171	12		T189	2		T238	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T8	4		T236	13		T136	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T2	12		T27	2		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	5		T53	8		T132	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T186	10		T14	2		T54	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	13		T10	10		T215	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T207	4		T146	17		T260	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	15		T13	6		T143	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1111	1			T5	31		T8	3		T9	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	9		T145	13		T243	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	389	1			T9	25		T12	2		T23	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	10		T214	1		T41	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

auto[0]

4130

1

T1

1

T2

12

T5

31