Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27194

1

T1

101

T2

27

T3

5

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23303

1

T1

96

T2

27

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3891

1

T1

5

T3

5

T6

22

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21153

1

T1

96

T3

5

T4

20

auto[1]

6041

1

T1

5

T2

27

T5

33

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23099

1

T1

100

T2

13

T3

1

auto[1]

4095

1

T1

1

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T200	1		T258	11		T95	4
values[0]	87	1			T178	1		T324	19		T292	11
values[1]	1011	1			T9	15		T10	22		T47	1
values[2]	2763	1			T5	33		T6	13		T11	3
values[3]	749	1			T12	10		T47	1		T108	1
values[4]	608	1			T3	5		T11	5		T108	1
values[5]	568	1			T8	5		T35	6		T28	12
values[6]	783	1			T1	5		T8	4		T11	9
values[7]	612	1			T6	16		T9	21		T13	21
values[8]	769	1			T2	27		T8	14		T27	3
values[9]	1166	1			T6	6		T9	6		T12	3
minimum	18048	1			T1	96		T4	20		T7	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1171	1			T9	15		T10	22		T11	3
values[1]	2921	1			T5	33		T6	13		T108	1
values[2]	593	1			T12	10		T47	1		T108	1
values[3]	618	1			T3	5		T11	5		T108	1
values[4]	680	1			T8	5		T53	19		T28	7
values[5]	683	1			T1	5		T8	4		T9	21
values[6]	676	1			T6	16		T13	17		T27	3
values[7]	792	1			T2	27		T8	14		T29	1
values[8]	822	1			T9	6		T37	3		T14	2
values[9]	173	1			T6	6		T12	3		T28	11
minimum	18065	1			T1	96		T4	20		T7	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

4130

1

T1

1

T2

12

T5

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T9	15		T11	3		T14	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T10	11		T47	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1492	1			T5	33		T6	13		T42	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T108	1		T213	1		T39	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T131	1		T145	12		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	10		T47	1		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	5		T35	5		T23	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	1		T108	1		T13	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	5		T53	9		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T143	14		T171	15		T215	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	4		T11	9		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	4		T9	21		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	8		T37	1		T246	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	16		T27	3		T36	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T2	13		T8	14		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T201	1		T33	1		T214	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	6		T37	2		T14	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T202	1		T243	17		T214	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T12	3		T142	1		T202	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T6	6		T28	1		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17923	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T325	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T14	3		T54	8		T135	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T10	11		T137	1		T171	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1091	1			T181	6		T212	23		T213	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T213	10		T39	3		T214	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T15	1		T216	9		T155	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T143	7		T132	10		T211	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T35	1		T23	6		T26	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	4		T13	4		T28	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T53	10		T28	6		T33	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T171	13		T215	8		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T30	8		T186	4		T199	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T1	1		T13	2		T132	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	9		T37	1		T246	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T36	1		T54	8		T217	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	14		T231	12		T237	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T33	2		T214	15		T215	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T37	1		T229	17		T207	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T214	14		T207	11		T172	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T326	5		T327	12		T95	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T28	10		T135	12		T278	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T13	5		T26	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T325	7		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T95	1		T313	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T200	1		T258	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T178	1		T324	10		T292	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T96	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	15		T54	6		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T10	11		T47	1		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1414	1			T5	33		T6	13		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T108	1		T39	5		T214	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T131	1		T145	12		T206	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	10		T47	1		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	5		T23	8		T26	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T108	1		T13	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	5		T35	5		T175	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T28	1		T133	1		T171	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T8	4		T11	9		T53	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	4		T143	14		T132	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	8		T30	1		T246	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	16		T9	21		T13	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T2	13		T8	14		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T27	3		T33	1		T317	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	6		T12	3		T130	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	395	1			T6	6		T28	1		T201	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17923	1			T1	96		T4	20		T7	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T95	3		T313	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T324	9		T292	8		T296	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T96	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T54	8		T135	9		T219	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T10	11		T137	1		T171	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T181	6		T212	23		T213	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T39	3		T214	7		T231	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T15	1		T155	4		T78	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T213	10		T143	7		T132	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T23	6		T26	2		T172	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	4		T13	4		T132	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T35	1		T189	4		T250	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T28	11		T133	2		T171	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T53	10		T28	6		T186	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	1		T132	8		T221	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	9		T30	8		T246	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T13	2		T36	1		T54	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T2	14		T37	1		T205	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T33	2		T251	13		T249	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T37	1		T229	17		T207	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T28	10		T135	12		T214	29
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T13	5		T26	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T9	1		T11	1		T14	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T10	12		T47	1		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1421	1			T5	2		T6	1		T42	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T108	1		T213	11		T39	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T131	1		T145	1		T206	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T47	1		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	1		T35	5		T23	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T3	5		T108	1		T13	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T8	1		T53	11		T28	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T143	1		T171	14		T215	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T8	1		T11	1		T30	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	4		T9	1		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	12		T37	2		T246	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	1		T27	1		T36	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	15		T8	1		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T201	1		T33	3		T214	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	1		T37	2		T14	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T202	1		T243	1		T214	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T12	1		T142	1		T202	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T6	1		T28	11		T135	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18048	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T325	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	14		T11	2		T14	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T10	10		T254	2		T137	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1162	1			T5	31		T6	12		T42	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T39	2		T214	1		T231	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T145	11		T136	7		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	9		T143	7		T132	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T11	4		T35	1		T23	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	6		T132	16		T238	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T8	4		T53	8		T33	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T143	13		T171	14		T215	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	3		T11	8		T186	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	1		T9	20		T13	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	5		T221	9		T152	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T6	15		T27	2		T36	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T2	12		T8	13		T130	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T214	14		T136	11		T215	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T9	5		T37	1		T207	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T243	16		T214	15		T207	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T12	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T6	5		T136	10		T278	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T325	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T95	4		T313	14		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T200	1		T258	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T178	1		T324	10		T292	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T96	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T9	1		T54	9		T135	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T10	12		T47	1		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T5	2		T6	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T108	1		T39	6		T214	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T131	1		T145	1		T206	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	1		T47	1		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	1		T23	10		T26	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	5		T108	1		T13	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T8	1		T35	5		T175	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T28	12		T133	3		T171	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	1		T11	1		T53	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	4		T143	1		T132	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	12		T30	9		T246	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	1		T9	1		T13	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	15		T8	1		T29	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T27	1		T33	3		T317	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T9	1		T12	1		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	395	1			T6	1		T28	11		T201	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18048	1			T1	96		T4	20		T7	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T258	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T324	9		T292	2		T296	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T96	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	14		T54	5		T219	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T10	10		T254	2		T137	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1088	1			T5	31		T6	12		T11	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T39	2		T214	1		T231	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T145	11		T236	13		T15	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	9		T143	7		T132	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T11	4		T23	4		T26	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	6		T132	16		T238	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T8	4		T35	1		T189	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T171	14		T215	8		T301	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	3		T11	8		T53	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	1		T143	13		T132	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	5		T152	5		T148	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	15		T9	20		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T2	12		T8	13		T221	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T27	2		T251	14		T249	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	5		T12	2		T130	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T6	5		T243	16		T214	29

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

auto[0]

4130

1

T1

1

T2

12

T5

31