Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27194

1

T1

101

T2

27

T3

5

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23705

1

T1

96

T4

20

T5

33

auto[ADC_CTRL_FILTER_COND_OUT]

3489

1

T1

5

T2

27

T3

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21135

1

T1

96

T2

27

T3

5

auto[1]

6059

1

T1

5

T5

33

T6

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23099

1

T1

100

T2

13

T3

1

auto[1]

4095

1

T1

1

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	279	1			T11	9		T28	12		T297	1
values[0]	23	1			T299	11		T295	12		-	-
values[1]	592	1			T108	1		T26	8		T27	3
values[2]	773	1			T1	5		T9	21		T10	22
values[3]	753	1			T6	13		T11	5		T13	17
values[4]	726	1			T3	5		T6	6		T12	3
values[5]	2929	1			T5	33		T42	14		T134	10
values[6]	628	1			T8	4		T9	6		T29	1
values[7]	797	1			T2	27		T9	15		T12	10
values[8]	732	1			T8	14		T11	3		T35	6
values[9]	914	1			T6	16		T8	5		T201	1
minimum	18048	1			T1	96		T4	20		T7	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	718	1			T1	5		T9	21		T47	1
values[1]	762	1			T10	22		T108	1		T13	21
values[2]	647	1			T6	13		T11	5		T174	1
values[3]	2920	1			T3	5		T5	33		T6	6
values[4]	770	1			T8	4		T28	11		T37	3
values[5]	544	1			T9	21		T12	10		T108	1
values[6]	918	1			T2	27		T8	14		T11	3
values[7]	696	1			T35	6		T130	9		T37	2
values[8]	774	1			T6	16		T8	5		T11	9
values[9]	227	1			T28	12		T36	6		T257	9
minimum	18218	1			T1	96		T4	20		T7	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

4130

1

T1

1

T2

12

T5

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T47	1		T108	1		T27	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	4		T9	21		T33	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	10		T213	1		T146	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T10	11		T108	1		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	5		T174	1		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	13		T14	2		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1493	1			T5	33		T6	6		T42	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	1		T12	3		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T54	6		T132	10		T171	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	4		T28	1		T37	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T9	21		T29	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	10		T108	1		T298	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T13	7		T186	11		T143	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T2	13		T8	14		T11	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T35	5		T130	9		T14	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T37	1		T133	1		T39	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T6	16		T8	5		T11	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T142	1		T41	2		T297	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T257	9		T298	2		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T28	1		T36	5		T79	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17971	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T33	1		T278	5		T163	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T135	12		T247	12		T217	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T1	1		T33	5		T205	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T13	11		T213	9		T273	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T10	11		T246	12		T221	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T221	2		T250	14		T209	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T215	29		T217	11		T250	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T53	10		T23	6		T181	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	4		T54	8		T229	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T54	8		T132	8		T171	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T28	10		T37	1		T33	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T132	12		T137	1		T215	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T234	1		T208	13		T271	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	4		T186	4		T143	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	14		T28	6		T30	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T35	1		T14	3		T132	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T37	1		T133	2		T39	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T152	5		T231	9		T189	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T189	6		T260	4		T16	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T298	1		T199	12		T303	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T28	11		T36	1		T79	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T35	1		T13	5		T26	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T278	3		T328	2		T299	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T11	9		T175	1		T259	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T28	1		T297	1		T329	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T295	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T299	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T108	1		T26	6		T27	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T33	14		T205	1		T41	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T47	1		T13	2		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T1	4		T9	21		T10	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	5		T13	8		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T6	13		T14	2		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	6		T53	9		T174	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	1		T12	3		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1532	1			T5	33		T42	14		T134	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T28	1		T37	2		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	6		T29	1		T132	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	4		T33	1		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	15		T13	7		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	13		T12	10		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T35	5		T186	11		T130	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	14		T11	3		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T6	16		T8	5		T201	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T36	5		T37	1		T133	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17923	1			T1	96		T4	20		T7	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T259	15		T232	7		T233	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T28	11		T268	2		T79	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T295	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T299	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T26	2		T135	12		T247	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T33	5		T205	3		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T13	2		T218	3		T256	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T1	1		T10	11		T221	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	9		T213	9		T221	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T246	12		T215	21		T216	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T53	10		T171	10		T251	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	4		T54	8		T229	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1083	1			T23	6		T181	6		T212	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T28	10		T37	1		T135	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T132	12		T137	1		T215	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T33	2		T17	1		T234	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	4		T147	12		T249	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	14		T30	8		T214	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T35	1		T186	4		T14	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T28	6		T39	3		T149	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T152	5		T172	14		T231	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T36	1		T37	1		T133	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T13	5		T26	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T47	1		T108	1		T27	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	4		T9	1		T33	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	15		T213	10		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T10	12		T108	1		T246	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	1		T174	1		T221	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	1		T14	2		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T5	2		T6	1		T42	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	5		T12	1		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T54	9		T132	9		T171	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	1		T28	11		T37	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	2		T29	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	1		T108	1		T298	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T13	5		T186	5		T143	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T2	15		T8	1		T11	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T35	5		T130	1		T14	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T37	2		T133	3		T39	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T6	1		T8	1		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T142	1		T41	2		T297	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T257	1		T298	3		T199	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T28	12		T36	5		T79	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18095	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T33	1		T278	4		T163	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T27	2		T147	2		T247	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	1		T9	20		T33	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	6		T146	8		T273	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	10		T221	9		T214	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	4		T177	11		T209	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	12		T243	16		T215	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1168	1			T5	31		T6	5		T42	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	2		T236	13		T207	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T54	5		T132	9		T171	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T8	3		T37	1		T254	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	19		T132	16		T137	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T12	9		T264	9		T208	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	6		T186	10		T143	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	12		T8	13		T11	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T35	1		T130	8		T14	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T39	2		T227	1		T235	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T6	15		T8	4		T11	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T189	2		T176	3		T260	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T257	8		T303	17		T330	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T36	1		T79	2		T331	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T26	1		T301	17		T324	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T278	4		T332	12		T328	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T11	1		T175	1		T259	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T28	12		T297	1		T329	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T295	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T299	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T108	1		T26	7		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T33	7		T205	4		T41	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T47	1		T13	3		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T1	4		T9	1		T10	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	1		T13	12		T213	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	1		T14	2		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	1		T53	11		T174	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	5		T12	1		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T5	2		T42	2		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T28	11		T37	2		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	1		T29	1		T132	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	1		T33	3		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	1		T13	5		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	15		T12	1		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T35	5		T186	5		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	1		T11	1		T28	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	1		T8	1		T201	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T36	5		T37	2		T133	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18048	1			T1	96		T4	20		T7	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T11	8		T259	8		T232	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T17	3		T279	13		T268	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T295	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T26	1		T27	2		T301	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T33	12		T41	2		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T13	1		T146	8		T147	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T1	1		T9	20		T10	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	4		T13	5		T177	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	12		T215	15		T237	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	5		T53	8		T171	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	2		T243	16		T236	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T5	31		T42	12		T134	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T37	1		T254	2		T207	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	5		T132	16		T137	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T8	3		T17	1		T264	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	14		T13	6		T147	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	12		T12	9		T214	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T35	1		T186	10		T130	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T8	13		T11	2		T39	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	15		T8	4		T143	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T36	1		T189	2		T176	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

auto[0]

4130

1

T1

1

T2

12

T5

31