Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27194

1

T1

101

T2

27

T3

5

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23724

1

T1

96

T3

5

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3470

1

T1

5

T2

27

T6

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20598

1

T1

96

T2

27

T4

20

auto[1]

6596

1

T1

5

T3

5

T5

33

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23099

1

T1

100

T2

13

T3

1

auto[1]

4095

1

T1

1

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	632	1			T1	5		T6	6		T7	1
values[0]	53	1			T200	1		T156	28		T166	8
values[1]	521	1			T1	5		T13	17		T201	1
values[2]	3009	1			T5	33		T10	22		T12	3
values[3]	696	1			T6	29		T47	1		T108	1
values[4]	914	1			T47	1		T37	2		T174	1
values[5]	638	1			T9	21		T145	14		T205	4
values[6]	695	1			T8	14		T11	3		T35	6
values[7]	824	1			T2	27		T3	5		T8	5
values[8]	628	1			T8	4		T37	1		T174	1
values[9]	1022	1			T9	21		T11	14		T108	2
minimum	17562	1			T1	91		T4	20		T7	141

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	509	1			T10	22		T13	17		T201	1
values[1]	2966	1			T5	33		T6	29		T12	3
values[2]	737	1			T53	19		T13	11		T28	23
values[3]	941	1			T47	1		T54	14		T145	14
values[4]	663	1			T9	21		T35	6		T13	4
values[5]	635	1			T8	14		T11	3		T23	14
values[6]	819	1			T2	27		T3	5		T8	9
values[7]	592	1			T174	1		T143	15		T202	1
values[8]	958	1			T6	6		T9	21		T11	14
values[9]	109	1			T203	1		T180	1		T208	27
minimum	18265	1			T1	101		T4	20		T7	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

4130

1

T1

1

T2

12

T5

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	8		T201	1		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T10	11		T133	1		T137	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1542	1			T5	33		T47	1		T42	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	29		T12	3		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T37	1		T174	1		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T53	9		T13	7		T28	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T47	1		T54	6		T39	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T145	14		T135	1		T136	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	21		T35	5		T13	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	5		T33	13		T205	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	14		T11	3		T137	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T23	8		T29	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	1		T8	5		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T2	13		T8	4		T12	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T174	1		T143	8		T207	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T202	1		T206	1		T207	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	6		T9	6		T11	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T9	15		T11	9		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T208	14		T209	2		T81	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T203	1		T180	1		T226	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18017	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T1	4		T277	1		T138	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	9		T41	1		T211	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T10	11		T133	2		T137	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1105	1			T36	1		T37	1		T181	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T213	9		T215	8		T216	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T37	1		T33	2		T172	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T53	10		T13	4		T28	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T54	8		T39	3		T214	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T135	12		T215	8		T216	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T35	1		T13	2		T217	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	3		T33	5		T205	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T220	10		T218	3		T276	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T23	6		T219	9		T234	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	4		T30	8		T132	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	14		T221	2		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T143	7		T207	11		T189	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T172	2		T219	10		T260	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T26	2		T28	6		T246	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T186	4		T213	10		T54	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T208	13		T209	1		T224	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T226	2		T185	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T35	1		T13	5		T26	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T1	1		T17	1		T34	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	524	1			T1	5		T6	6		T7	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T213	1		T204	1		T237	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T200	1		T156	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T166	3		T333	16		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	8		T201	1		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T1	4		T133	1		T277	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T5	33		T42	14		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	11		T12	3		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T47	1		T33	1		T143	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	29		T108	1		T53	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T47	1		T37	1		T174	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T135	1		T136	8		T215	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	21		T204	1		T147	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T145	14		T205	1		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	14		T11	3		T35	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T23	8		T29	1		T14	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	1		T8	5		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T2	13		T12	10		T27	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T37	1		T174	1		T143	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	4		T202	1		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T9	6		T11	5		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T9	15		T11	9		T108	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17437	1			T1	91		T4	20		T7	141
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T224	3		T334	3		T335	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T213	10		T237	1		T336	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T156	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T166	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	9		T172	14		T211	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T1	1		T133	2		T199	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1112	1			T36	1		T37	1		T181	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T10	11		T213	9		T137	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T33	2		T172	7		T154	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T53	10		T13	4		T28	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T37	1		T54	8		T39	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T135	12		T215	8		T216	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T147	12		T217	11		T148	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T205	3		T231	9		T273	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T35	1		T13	2		T220	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T23	6		T14	3		T33	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	4		T30	8		T132	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	14		T171	10		T260	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T143	7		T207	11		T189	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T221	2		T172	2		T219	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T26	2		T28	6		T246	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T186	4		T54	8		T132	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T13	5		T26	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	12		T201	1		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T10	12		T133	3		T137	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1452	1			T5	2		T47	1		T42	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	2		T12	1		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T37	2		T174	1		T33	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T53	11		T13	5		T28	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T47	1		T54	9		T39	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T145	1		T135	13		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	1		T35	5		T13	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T14	6		T33	6		T205	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T8	1		T11	1		T137	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T23	10		T29	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T3	5		T8	1		T30	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T2	15		T8	1		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T174	1		T143	8		T207	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T202	1		T206	1		T207	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T6	1		T9	1		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T9	1		T11	1		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T208	14		T209	2		T81	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T203	1		T180	1		T226	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18151	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T1	4		T277	1		T138	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	5		T41	2		T227	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T10	10		T137	2		T260	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T5	31		T42	12		T134	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	27		T12	2		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T143	13		T172	3		T147	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T53	8		T13	6		T177	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T54	5		T39	2		T214	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T145	13		T136	7		T215	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T9	20		T35	1		T13	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	2		T33	12		T146	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T8	13		T11	2		T177	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T23	4		T219	13		T237	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	4		T132	36		T214	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T2	12		T8	3		T12	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T143	7		T207	4		T227	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T172	2		T219	11		T260	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	5		T9	5		T11	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T9	14		T11	8		T186	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T208	13		T209	1		T224	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T185	16		T282	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T172	10		T156	26		T337	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T1	1		T17	1		T240	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	512	1			T1	5		T6	1		T7	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T213	11		T204	1		T237	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T200	1		T156	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T166	6		T333	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T13	12		T201	1		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T1	4		T133	3		T277	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1459	1			T5	2		T42	2		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T10	12		T12	1		T213	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T47	1		T33	3		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	2		T108	1		T53	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T47	1		T37	2		T174	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T135	13		T136	1		T215	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T9	1		T204	1		T147	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T145	1		T205	4		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	1		T11	1		T35	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T23	10		T29	1		T14	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	5		T8	1		T30	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	15		T12	1		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T37	1		T174	1		T143	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	1		T202	1		T221	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T9	1		T11	1		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T9	1		T11	1		T108	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17562	1			T1	91		T4	20		T7	141
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T6	5		T224	13		T338	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T336	8		T282	4		T309	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T156	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T166	2		T333	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	5		T172	10		T146	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T1	1		T260	3		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T5	31		T42	12		T134	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	10		T12	2		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T143	13		T172	3		T301	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T6	27		T53	8		T13	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T54	5		T39	2		T214	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T136	7		T215	8		T232	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T9	20		T147	12		T238	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T145	13		T227	14		T146	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T8	13		T11	2		T35	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T23	4		T14	2		T33	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	4		T132	36		T214	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T2	12		T12	9		T27	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T143	7		T207	4		T227	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T8	3		T172	2		T219	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	5		T11	4		T26	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T9	14		T11	8		T186	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

auto[0]

4130

1

T1

1

T2

12

T5

31