Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27194

1

T1

101

T2

27

T3

5

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23920

1

T1

96

T2

27

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3274

1

T1

5

T3

5

T6

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21348

1

T1

96

T4

20

T6

13

auto[1]

5846

1

T1

5

T2

27

T3

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23099

1

T1

100

T2

13

T3

1

auto[1]

4095

1

T1

1

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	214	1			T37	1		T213	11		T172	1
values[0]	52	1			T267	1		T157	1		T284	11
values[1]	730	1			T8	4		T11	9		T47	1
values[2]	781	1			T9	15		T11	5		T13	17
values[3]	717	1			T3	5		T8	5		T9	21
values[4]	2888	1			T5	33		T6	16		T9	6
values[5]	655	1			T1	5		T10	22		T108	1
values[6]	664	1			T6	19		T47	1		T53	19
values[7]	708	1			T12	10		T108	1		T174	1
values[8]	775	1			T8	14		T186	15		T145	14
values[9]	962	1			T2	27		T11	3		T12	3
minimum	18048	1			T1	96		T4	20		T7	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	625	1			T37	2		T131	1		T204	1
values[1]	948	1			T3	5		T9	15		T11	5
values[2]	514	1			T8	5		T9	6		T108	1
values[3]	3042	1			T5	33		T6	16		T9	21
values[4]	559	1			T1	5		T10	22		T53	19
values[5]	715	1			T6	19		T47	1		T13	11
values[6]	659	1			T12	10		T108	1		T174	1
values[7]	831	1			T8	14		T11	3		T186	15
values[8]	851	1			T2	27		T12	3		T28	11
values[9]	123	1			T213	11		T172	1		T216	10
minimum	18327	1			T1	96		T4	20		T7	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

4130

1

T1

1

T2

12

T5

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T131	1		T204	1		T172	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T37	1		T214	2		T267	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T9	15		T11	5		T132	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T3	1		T13	8		T23	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	5		T9	6		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T213	1		T133	1		T205	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1569	1			T5	33		T9	21		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	16		T28	1		T14	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T10	11		T53	9		T36	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	4		T38	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T6	6		T47	1		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	13		T13	7		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	10		T108	1		T14	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T174	1		T132	21		T145	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T11	3		T174	1		T145	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T8	14		T186	11		T227	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T2	13		T12	3		T39	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T28	1		T29	1		T201	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T200	15		T339	1		T287	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T213	1		T172	1		T216	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18020	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T8	4		T11	9		T35	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T172	14		T189	6		T237	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T37	1		T214	7		T259	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T132	8		T221	2		T135	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T3	4		T13	9		T23	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T33	5		T246	12		T137	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T213	9		T205	3		T152	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1118	1			T30	8		T181	6		T212	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T28	11		T14	3		T234	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T10	11		T53	10		T36	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	1		T135	12		T248	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T133	2		T231	12		T219	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	4		T28	6		T132	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T33	2		T215	8		T189	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T132	10		T41	6		T268	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T41	1		T147	12		T286	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T186	4		T17	1		T150	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	14		T39	3		T171	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T28	10		T260	4		T16	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T200	12		T287	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T213	10		T216	9		T230	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T35	1		T13	7		T26	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T35	1		T54	8		T221	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T200	15		T264	10		T75	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T37	1		T213	1		T172	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T284	1		T288	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T267	1		T157	1		T290	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T47	1		T13	2		T214	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	4		T11	9		T35	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	15		T11	5		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T13	8		T23	8		T26	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T8	5		T9	21		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	1		T213	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1506	1			T5	33		T9	6		T42	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	16		T28	1		T14	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	11		T108	1		T36	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	4		T38	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T6	6		T47	1		T53	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	13		T13	7		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T12	10		T108	1		T14	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T174	1		T132	21		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T145	14		T243	17		T41	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T8	14		T186	11		T227	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T2	13		T11	3		T12	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T28	1		T29	1		T201	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17923	1			T1	96		T4	20		T7	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T200	12		T285	1		T304	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T213	10		T260	4		T216	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T284	10		T288	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T290	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	2		T214	15		T171	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T35	1		T37	1		T54	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T135	9		T216	21		T247	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	9		T23	6		T26	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T33	5		T132	8		T246	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	4		T213	9		T205	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T30	8		T181	6		T212	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T28	11		T14	3		T155	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T10	11		T36	1		T54	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	1		T248	2		T251	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T53	10		T37	1		T231	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	4		T28	6		T132	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T33	2		T133	2		T215	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T132	10		T41	6		T149	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T41	1		T147	12		T286	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T186	4		T17	1		T150	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T2	14		T39	3		T171	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T28	10		T155	4		T234	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T13	5		T26	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T131	1		T204	1		T172	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T37	2		T214	8		T267	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T9	1		T11	1		T132	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T3	5		T13	12		T23	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T8	1		T9	1		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T213	10		T133	1		T205	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1453	1			T5	2		T9	1		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	1		T28	12		T14	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T10	12		T53	11		T36	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	4		T38	1		T135	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	1		T47	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	1		T13	5		T28	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T12	1		T108	1		T14	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T174	1		T132	11		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	1		T174	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	1		T186	5		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T2	15		T12	1		T39	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T28	11		T29	1		T201	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T200	13		T339	1		T287	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T213	11		T172	1		T216	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18119	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T8	1		T11	1		T35	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T172	10		T189	3		T247	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T214	1		T259	8		T232	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	14		T11	4		T132	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	5		T23	4		T26	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T8	4		T9	5		T27	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T152	5		T136	10		T291	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T5	31		T9	20		T42	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	15		T14	2		T236	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T10	10		T53	8		T36	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T1	1		T248	2		T251	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T6	5		T143	13		T146	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T6	12		T13	6		T132	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	9		T215	9		T147	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T132	20		T145	11		T268	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	2		T145	13		T243	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T8	13		T186	10		T227	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	12		T12	2		T39	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T136	18		T177	7		T260	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T200	14		T287	12		T333	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T261	9		T292	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T13	1		T214	14		T171	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T8	3		T11	8		T35	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T200	13		T264	1		T75	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T37	1		T213	11		T172	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T284	11		T288	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T267	1		T157	1		T290	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T47	1		T13	3		T214	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	1		T11	1		T35	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	1		T11	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T13	12		T23	10		T26	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	1		T9	1		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	5		T213	10		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T5	2		T9	1		T42	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	1		T28	12		T14	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T10	12		T108	1		T36	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	4		T38	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T6	1		T47	1		T53	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	1		T13	5		T28	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	1		T108	1		T14	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T174	1		T132	11		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T145	1		T243	1		T41	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	1		T186	5		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T2	15		T11	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T28	11		T29	1		T201	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18048	1			T1	96		T4	20		T7	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T200	14		T264	9		T75	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T260	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T288	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T290	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	1		T214	14		T171	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	3		T11	8		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T9	14		T11	4		T247	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	5		T23	4		T26	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T8	4		T9	20		T33	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T152	5		T136	10		T231	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T5	31		T9	5		T42	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	15		T14	2		T236	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T10	10		T36	1		T214	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T1	1		T248	2		T251	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	5		T53	8		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T6	12		T13	6		T132	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	9		T215	9		T147	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T132	20		T145	11		T268	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T145	13		T243	16		T41	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T8	13		T186	10		T227	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T2	12		T11	2		T12	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T136	18		T177	7		T260	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

auto[0]

4130

1

T1

1

T2

12

T5

31