Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	1		T108	1		T137	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T11	1		T27	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	1		T47	1		T37	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1426	1			T5	2		T6	1		T42	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T39	6		T153	1		T139	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	1		T12	1		T53	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	4		T12	1		T26	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	15		T10	12		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T132	9		T243	1		T177	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	1		T29	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	5		T35	5		T213	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T9	1		T108	1		T14	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	1		T142	1		T133	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T206	1		T171	11		T244	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	1		T37	1		T214	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	1		T108	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	1		T9	1		T13	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T28	11		T213	10		T33	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T13	3		T23	10		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T30	9		T138	1		T245	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18048	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T146	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	8		T137	2		T176	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	2		T27	2		T130	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	3		T37	1		T227	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1207	1			T5	31		T6	5		T42	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T39	2		T139	10		T209	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	12		T12	9		T53	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	1		T12	2		T26	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	12		T10	10		T13	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T132	9		T243	16		T177	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T8	13		T248	2		T249	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T35	1		T214	29		T218	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T9	14		T14	2		T254	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	20		T251	14		T211	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T171	12		T244	21		T148	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	4		T214	1		T146	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	15		T136	7		T74	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T8	4		T9	5		T13	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T145	13		T152	5		T207	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T13	1		T23	4		T189	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T146	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T142	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T207	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T241	1		T242	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	1		T108	1		T137	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	1		T130	1		T229	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	1		T47	1		T37	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	1		T27	1		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T37	2		T54	9		T132	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T13	12		T246	13		T41	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	4		T12	1		T172	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	1		T10	12		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T26	7		T36	5		T132	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	15		T8	1		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	5		T213	11		T214	31
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T9	1		T108	1		T204	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	1		T35	5		T133	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T206	1		T254	1		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	1		T37	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T108	1		T171	11		T175	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T8	1		T9	1		T13	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1532	1			T5	2		T6	1		T42	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18048	1			T1	96		T4	20		T7	142
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T242	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T11	8		T137	2		T257	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	2		T130	8		T207	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	3		T147	2		T176	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	5		T27	2		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T37	1		T54	5		T132	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	5		T41	2		T171	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T12	2		T172	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	12		T10	10		T12	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T26	1		T36	1		T132	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	12		T8	13		T14	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T214	29		T247	9		T234	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T9	14		T255	14		T258	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	20		T35	1		T251	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T254	2		T244	21		T148	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	4		T236	13		T214	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T171	12		T209	1		T74	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T8	4		T9	5		T13	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1267	1			T5	31		T6	15		T42	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

auto[0]

4130

1

T1

1

T2

12

T5

31