Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27194

1

T1

101

T2

27

T3

5

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23463

1

T1

96

T4

20

T5

33

auto[ADC_CTRL_FILTER_COND_OUT]

3731

1

T1

5

T2

27

T3

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20948

1

T1

96

T2

27

T3

5

auto[1]

6246

1

T1

5

T5

33

T6

35

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23099

1

T1

100

T2

13

T3

1

auto[1]

4095

1

T1

1

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	44	1			T36	6		T15	4		T259	24
values[1]	613	1			T10	22		T13	17		T26	8
values[2]	691	1			T6	16		T11	5		T47	1
values[3]	1001	1			T3	5		T201	1		T213	10
values[4]	562	1			T9	21		T12	10		T108	1
values[5]	757	1			T8	4		T9	15		T12	3
values[6]	564	1			T2	27		T6	13		T47	1
values[7]	532	1			T1	5		T6	6		T28	23
values[8]	841	1			T8	5		T11	9		T29	1
values[9]	3541	1			T5	33		T8	14		T9	6
minimum	18048	1			T1	96		T4	20		T7	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	842	1			T10	22		T13	17		T26	8
values[1]	767	1			T3	5		T6	16		T11	5
values[2]	879	1			T108	1		T201	1		T33	3
values[3]	649	1			T9	21		T12	13		T23	14
values[4]	703	1			T2	27		T9	15		T53	19
values[5]	497	1			T6	13		T8	4		T47	1
values[6]	2907	1			T1	5		T5	33		T6	6
values[7]	773	1			T8	5		T11	9		T27	3
values[8]	842	1			T8	14		T9	6		T11	3
values[9]	281	1			T108	1		T37	3		T14	8
minimum	18054	1			T1	96		T4	20		T7	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

4130

1

T1

1

T2

12

T5

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	8		T26	6		T204	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T10	11		T143	8		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T108	1		T131	1		T172	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T3	1		T6	16		T11	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T201	1		T33	1		T54	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T108	1		T54	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	13		T28	1		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	21		T23	8		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T53	9		T35	5		T229	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	13		T9	15		T152	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T47	1		T28	1		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	13		T8	4		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1506	1			T5	33		T42	14		T134	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	4		T6	6		T135	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T11	9		T29	1		T174	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	5		T27	3		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T9	6		T11	3		T186	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	14		T13	9		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T108	1		T33	13		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T37	2		T14	5		T221	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17923	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T36	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	9		T26	2		T260	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T10	11		T143	7		T246	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T215	21		T216	21		T235	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	4		T213	9		T207	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T33	2		T54	8		T132	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T54	8		T171	10		T247	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T28	6		T37	1		T249	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T23	6		T132	8		T39	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T53	10		T35	1		T229	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	14		T152	5		T41	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T28	10		T133	2		T137	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T221	2		T189	4		T139	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T28	11		T181	6		T212	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	1		T135	12		T172	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T214	15		T171	13		T251	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T132	10		T135	9		T189	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T186	4		T205	3		T207	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	6		T30	8		T231	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T33	5		T261	9		T262	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T37	1		T14	3		T221	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T13	5		T26	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T36	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T259	9		T263	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T36	5		T15	3		T21	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	8		T26	6		T204	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T10	11		T143	8		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T108	1		T131	1		T214	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T6	16		T11	5		T47	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T201	1		T33	1		T54	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T3	1		T213	1		T174	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T12	10		T28	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T9	21		T108	1		T23	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T12	3		T53	9		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	4		T9	15		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T47	1		T35	5		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	13		T6	13		T41	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T28	2		T213	1		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T1	4		T6	6		T221	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T11	9		T29	1		T130	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T8	5		T142	1		T132	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1645	1			T5	33		T9	6		T11	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T8	14		T13	9		T27	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17923	1			T1	96		T4	20		T7	142
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T259	15		T263	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T36	1		T15	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	9		T26	2		T260	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T10	11		T143	7		T41	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T214	7		T216	12		T235	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T246	12		T214	14		T207	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T33	2		T54	8		T132	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T3	4		T213	9		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T28	6		T199	4		T74	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T23	6		T54	8		T132	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T53	10		T37	1		T229	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T152	5		T189	4		T139	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T35	1		T133	2		T137	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	14		T41	1		T148	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T28	21		T213	10		T215	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T1	1		T221	2		T219	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T214	15		T251	13		T217	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T132	10		T135	12		T172	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1186	1			T186	4		T181	6		T212	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T13	6		T30	8		T37	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T13	5		T26	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	12		T26	7		T204	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T10	12		T143	8		T246	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T108	1		T131	1		T172	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	5		T6	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T201	1		T33	3		T54	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T108	1		T54	9		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	2		T28	7		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	1		T23	10		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T53	11		T35	5		T229	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T2	15		T9	1		T152	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T47	1		T28	11		T133	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T6	1		T8	1		T221	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1398	1			T5	2		T42	2		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	4		T6	1		T135	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T11	1		T29	1		T174	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	1		T27	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T9	1		T11	1		T186	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T8	1		T13	8		T30	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T108	1		T33	6		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T37	2		T14	6		T221	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18048	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T36	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	5		T26	1		T146	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	10		T143	7		T214	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T215	15		T238	2		T264	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T6	15		T11	4		T145	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T54	5		T132	16		T214	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T143	13		T145	11		T136	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	11		T146	17		T249	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	20		T23	4		T132	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T53	8		T35	1		T227	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	12		T9	14		T152	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T236	13		T136	10		T137	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T6	12		T8	3		T189	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1166	1			T5	31		T42	12		T134	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	1		T6	5		T172	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	8		T214	14		T171	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	4		T27	2		T132	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	5		T11	2		T186	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	13		T13	7		T231	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T33	12		T261	9		T262	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T37	1		T14	2		T221	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T36	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T259	16		T263	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T36	5		T15	3		T21	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	12		T26	7		T204	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	12		T143	8		T41	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T108	1		T131	1		T214	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T6	1		T11	1		T47	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T201	1		T33	3		T54	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T3	5		T213	10		T174	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T12	1		T28	7		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	1		T108	1		T23	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	1		T53	11		T37	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T8	1		T9	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T47	1		T35	5		T133	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	15		T6	1		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T28	23		T213	11		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	4		T6	1		T221	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T11	1		T29	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T8	1		T142	1		T132	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T5	2		T9	1		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T8	1		T13	8		T27	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18048	1			T1	96		T4	20		T7	142
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T259	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T36	1		T15	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	5		T26	1		T146	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T10	10		T143	7		T136	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T214	1		T238	2		T264	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T6	15		T11	4		T145	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T54	5		T132	16		T254	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T171	12		T257	12		T247	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T12	9		T265	12		T74	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	20		T23	4		T143	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	2		T53	8		T227	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	3		T9	14		T152	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T35	1		T236	13		T136	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T2	12		T6	12		T41	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T243	16		T215	9		T189	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T1	1		T6	5		T219	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T11	8		T130	8		T214	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T8	4		T132	20		T172	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T5	31		T9	5		T11	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T8	13		T13	7		T27	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

auto[0]

4130

1

T1

1

T2

12

T5

31