Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27194

1

T1

101

T2

27

T3

5

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23726

1

T1

96

T2

27

T3

5

auto[ADC_CTRL_FILTER_COND_OUT]

3468

1

T1

5

T6

16

T8

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21218

1

T1

101

T4

20

T6

22

auto[1]

5976

1

T2

27

T3

5

T5

33

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23099

1

T1

100

T2

13

T3

1

auto[1]

4095

1

T1

1

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	16	1			T264	16		-	-		-	-
values[0]	29	1			T178	1		T241	1		T266	2
values[1]	701	1			T3	5		T6	16		T8	4
values[2]	831	1			T1	5		T2	27		T12	3
values[3]	607	1			T9	21		T53	19		T35	6
values[4]	460	1			T38	1		T142	1		T205	4
values[5]	2836	1			T5	33		T42	14		T134	10
values[6]	702	1			T12	10		T47	1		T23	14
values[7]	758	1			T11	5		T13	11		T145	12
values[8]	665	1			T8	5		T9	21		T11	9
values[9]	1541	1			T6	19		T8	14		T47	1
minimum	18048	1			T1	96		T4	20		T7	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	881	1			T1	5		T2	27		T3	5
values[1]	793	1			T9	15		T12	3		T54	9
values[2]	581	1			T9	6		T53	19		T35	6
values[3]	2723	1			T5	33		T42	14		T134	10
values[4]	699	1			T12	10		T23	14		T28	11
values[5]	706	1			T11	5		T47	1		T13	11
values[6]	766	1			T29	1		T33	18		T221	3
values[7]	737	1			T6	6		T8	5		T9	21
values[8]	966	1			T6	13		T8	14		T47	1
values[9]	275	1			T174	1		T244	22		T219	22
minimum	18067	1			T1	96		T4	20		T7	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

4130

1

T1

1

T2

12

T5

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	13		T3	1		T14	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T1	4		T6	16		T8	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T9	15		T132	10		T202	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	3		T54	1		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T53	9		T28	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T9	6		T35	5		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1460	1			T5	33		T42	14		T134	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T54	6		T142	1		T172	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T28	1		T229	1		T267	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	10		T23	8		T14	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T131	1		T172	1		T15	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T11	5		T47	1		T13	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T33	13		T221	1		T137	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T29	1		T206	1		T236	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	6		T8	5		T9	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T108	1		T13	8		T186	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T6	13		T8	14		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T47	1		T27	3		T130	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T268	4		T269	18		T270	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T174	1		T244	22		T219	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17934	1			T1	96		T4	20		T7	142
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	14		T3	4		T14	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	1		T10	11		T13	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T132	8		T171	13		T231	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T54	8		T215	8		T247	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T53	10		T28	11		T30	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T35	1		T135	9		T231	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T26	2		T181	6		T212	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T54	8		T172	2		T149	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T28	10		T229	17		T248	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T23	6		T132	10		T39	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T215	8		T147	12		T219	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	4		T213	9		T246	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T33	5		T221	2		T137	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T172	7		T215	21		T156	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T28	6		T133	2		T221	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	9		T186	4		T37	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T143	7		T17	1		T208	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T213	10		T132	12		T172	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T268	1		T269	15		T270	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T219	10		T16	3		T271	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T35	1		T13	5		T26	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T264	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T178	1		T241	1		T266	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T272	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	1		T14	5		T214	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	16		T8	4		T10	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T2	13		T132	10		T202	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	4		T12	3		T54	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	15		T53	9		T26	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	6		T35	5		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T38	1		T205	1		T202	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T142	1		T172	3		T177	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1498	1			T5	33		T42	14		T134	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	2		T54	6		T132	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	1		T131	1		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	10		T47	1		T23	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T221	1		T137	4		T15	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	5		T13	7		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	5		T9	21		T11	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T108	1		T13	8		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	404	1			T6	19		T8	14		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	469	1			T47	1		T27	3		T186	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17923	1			T1	96		T4	20		T7	142
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T266	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T272	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	4		T14	3		T214	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T10	11		T13	2		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	14		T132	8		T171	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	1		T54	8		T41	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T53	10		T26	2		T28	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T35	1		T135	9		T231	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T205	3		T135	12		T41	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T172	2		T149	8		T273	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1113	1			T181	6		T212	23		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T54	8		T132	10		T39	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T28	10		T215	8		T147	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T23	6		T213	9		T246	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T221	2		T137	1		T139	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T13	4		T152	5		T171	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T33	5		T133	2		T189	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	9		T37	1		T215	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T28	6		T143	7		T221	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T186	4		T37	1		T213	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T13	5		T26	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	15		T3	5		T14	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T1	4		T6	1		T8	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T9	1		T132	9		T202	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T54	9		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T53	11		T28	12		T30	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T9	1		T35	5		T135	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T5	2		T42	2		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T54	9		T142	1		T172	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T28	11		T229	18		T267	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	1		T23	10		T14	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T131	1		T172	1		T15	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	1		T47	1		T13	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T33	6		T221	3		T137	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T29	1		T206	1		T236	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	1		T8	1		T9	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T108	1		T13	12		T186	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T6	1		T8	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T47	1		T27	1		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T268	4		T269	16		T270	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T174	1		T244	1		T219	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18057	1			T1	96		T4	20		T7	142
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	12		T14	2		T214	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	1		T6	15		T8	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	14		T132	9		T171	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	2		T254	2		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T53	8		T189	3		T148	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	5		T35	1		T231	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1127	1			T5	31		T42	12		T134	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T54	5		T172	2		T268	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T260	3		T248	2		T274	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	9		T23	4		T132	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T215	8		T147	12		T219	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	4		T13	6		T145	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T33	12		T137	2		T227	34
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T236	13		T136	11		T172	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	5		T8	4		T9	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	5		T186	10		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T6	12		T8	13		T143	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T27	2		T130	8		T132	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T268	1		T269	17		T275	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T244	21		T219	11		T264	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T235	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T264	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T178	1		T241	1		T266	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T272	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	5		T14	6		T214	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	1		T8	1		T10	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	15		T132	9		T202	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	4		T12	1		T54	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	1		T53	11		T26	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	1		T35	5		T135	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T38	1		T205	4		T202	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T142	1		T172	3		T177	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1446	1			T5	2		T42	2		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T14	2		T54	9		T132	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T28	11		T131	1		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	1		T47	1		T23	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T221	3		T137	3		T15	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	1		T13	5		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	1		T9	1		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T108	1		T13	12		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T6	2		T8	1		T28	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	436	1			T47	1		T27	1		T186	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18048	1			T1	96		T4	20		T7	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T264	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T272	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T14	2		T214	15		T207	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	15		T8	3		T10	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	12		T132	9		T171	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	1		T12	2		T254	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T9	14		T53	8		T26	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T9	5		T35	1		T231	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T189	3		T209	1		T276	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T172	2		T177	8		T273	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1165	1			T5	31		T42	12		T134	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T54	5		T132	20		T39	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T215	8		T147	12		T248	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	9		T23	4		T214	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T137	2		T227	20		T176	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	4		T13	6		T145	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T8	4		T9	20		T11	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	5		T37	1		T243	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T6	17		T8	13		T143	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	402	1			T27	2		T186	10		T130	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

auto[0]

4130

1

T1

1

T2

12

T5

31