Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27194

1

T1

101

T2

27

T3

5

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21272

1

T1

101

T3

5

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

5922

1

T2

27

T5

33

T6

35

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20870

1

T1

96

T4

20

T6

22

auto[1]

6324

1

T1

5

T2

27

T3

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23099

1

T1

100

T2

13

T3

1

auto[1]

4095

1

T1

1

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	317	1			T8	5		T9	6		T13	11
values[1]	592	1			T11	9		T108	1		T130	9
values[2]	799	1			T6	6		T8	4		T11	3
values[3]	686	1			T54	14		T246	13		T39	8
values[4]	838	1			T1	5		T6	13		T10	22
values[5]	738	1			T2	27		T8	14		T29	1
values[6]	751	1			T3	5		T9	15		T108	1
values[7]	648	1			T9	21		T35	6		T133	3
values[8]	659	1			T11	5		T108	1		T37	1
values[9]	3118	1			T5	33		T6	16		T42	14
minimum	18048	1			T1	96		T4	20		T7	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	704	1			T11	3		T108	1		T27	3
values[1]	3023	1			T5	33		T6	6		T8	4
values[2]	747	1			T6	13		T12	10		T53	19
values[3]	841	1			T1	5		T2	27		T10	22
values[4]	677	1			T3	5		T8	14		T29	1
values[5]	696	1			T9	15		T108	1		T35	6
values[6]	706	1			T9	21		T142	1		T133	3
values[7]	638	1			T6	16		T11	5		T108	1
values[8]	887	1			T8	5		T9	6		T13	11
values[9]	146	1			T13	4		T23	14		T30	9
minimum	18129	1			T1	96		T4	20		T7	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

4130

1

T1

1

T2

12

T5

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T108	1		T137	4		T277	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T11	3		T27	3		T130	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T8	4		T47	1		T37	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1536	1			T5	33		T6	6		T42	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T132	17		T39	5		T227	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T6	13		T12	10		T53	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	4		T12	3		T26	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T2	13		T10	11		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T3	1		T132	10		T243	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T8	14		T29	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	5		T213	1		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	15		T108	1		T14	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	21		T142	1		T133	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T206	1		T171	13		T244	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	5		T37	1		T205	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	16		T108	1		T145	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T8	5		T13	7		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T9	6		T28	1		T213	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T13	2		T23	8		T189	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T30	1		T138	1		T217	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17940	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T229	1		T207	5		T227	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T137	1		T219	9		T216	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T41	6		T231	9		T278	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T37	2		T233	15		T149	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1085	1			T181	6		T212	23		T151	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T132	12		T39	3		T139	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T53	10		T13	9		T246	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	1		T26	2		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T2	14		T10	11		T28	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	4		T132	8		T247	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T248	2		T149	8		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T213	10		T214	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	3		T135	9		T250	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T133	2		T135	12		T211	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T171	10		T148	15		T199	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T205	3		T189	3		T199	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T214	7		T74	10		T252	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	4		T28	6		T186	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T28	10		T213	9		T33	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T13	2		T23	6		T189	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T30	8		T217	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T13	5		T26	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T229	17		T207	11		T270	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T8	5		T13	7		T14	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T9	6		T30	1		T213	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	9		T108	1		T137	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T130	9		T229	1		T202	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T8	4		T47	1		T37	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	6		T11	3		T27	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T54	6		T39	5		T227	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T246	1		T41	3		T171	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	4		T12	3		T26	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T6	13		T10	11		T12	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T36	5		T132	10		T221	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	13		T8	14		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	1		T213	1		T214	31
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	15		T108	1		T14	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T9	21		T35	5		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T206	1		T254	3		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	5		T37	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T108	1		T214	2		T171	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T13	2		T23	8		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1571	1			T5	33		T6	16		T42	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17923	1			T1	96		T4	20		T7	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T13	4		T143	7		T155	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T30	8		T213	9		T215	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T137	1		T219	9		T216	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T229	17		T41	6		T207	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T37	2		T232	16		T233	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T132	10		T172	14		T215	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T54	8		T39	3		T220	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T246	12		T41	1		T171	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	1		T26	2		T132	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T10	11		T53	10		T13	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T36	1		T132	8		T221	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T2	14		T147	12		T248	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	4		T213	10		T214	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T14	3		T135	9		T234	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T35	1		T133	2		T135	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T148	15		T199	12		T250	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T205	3		T199	4		T77	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T214	7		T171	10		T209	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	2		T23	6		T28	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1114	1			T28	10		T181	6		T212	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T13	5		T26	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T108	1		T137	3		T277	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	1		T27	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	1		T47	1		T37	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1419	1			T5	2		T6	1		T42	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T132	13		T39	6		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	1		T12	1		T53	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	4		T12	1		T26	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T2	15		T10	12		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	5		T132	9		T243	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	1		T29	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T35	5		T213	11		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T9	1		T108	1		T14	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	1		T142	1		T133	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T206	1		T171	11		T244	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	1		T37	1		T205	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	1		T108	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	1		T13	5		T28	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T9	1		T28	11		T213	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T13	3		T23	10		T189	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T30	9		T138	1		T217	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18055	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T229	18		T207	12		T227	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T137	2		T147	2		T176	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	2		T27	2		T130	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	3		T37	1		T260	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1202	1			T5	31		T6	5		T42	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T132	16		T39	2		T227	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T6	12		T12	9		T53	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	1		T12	2		T26	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	12		T10	10		T33	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T132	9		T243	16		T177	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T8	13		T248	2		T279	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T35	1		T214	29		T251	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	14		T14	2		T254	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T9	20		T211	8		T273	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T171	12		T244	21		T148	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	4		T146	17		T189	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	15		T145	13		T214	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T8	4		T13	6		T186	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	5		T152	5		T207	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T13	1		T23	4		T189	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T217	15		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T11	8		T240	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T207	4		T227	1		T280	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T8	1		T13	5		T14	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T9	1		T30	9		T213	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T108	1		T137	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T130	1		T229	18		T202	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T8	1		T47	1		T37	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	1		T11	1		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T54	9		T39	6		T227	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T246	13		T41	2		T171	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	4		T12	1		T26	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	1		T10	12		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T36	5		T132	9		T221	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	15		T8	1		T29	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	5		T213	11		T214	31
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T9	1		T108	1		T14	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T9	1		T35	5		T133	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T206	1		T254	1		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	1		T37	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T108	1		T214	8		T171	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	3		T23	10		T28	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1461	1			T5	2		T6	1		T42	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18048	1			T1	96		T4	20		T7	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T8	4		T13	6		T143	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T9	5		T215	9		T217	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T11	8		T137	2		T219	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T130	8		T207	4		T227	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	3		T37	1		T147	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T6	5		T11	2		T27	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T54	5		T39	2		T227	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T41	2		T171	14		T189	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	1		T12	2		T26	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T6	12		T10	10		T12	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T36	1		T132	9		T221	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T2	12		T8	13		T145	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T214	29		T247	9		T274	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T9	14		T14	2		T234	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	20		T35	1		T251	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T254	2		T244	21		T148	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T11	4		T146	17		T281	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T214	1		T171	12		T209	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	1		T23	4		T186	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1224	1			T5	31		T6	15		T42	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

auto[0]

4130

1

T1

1

T2

12

T5

31