Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27194

1

T1

101

T2

27

T3

5

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23702

1

T1

96

T4

20

T5

33

auto[ADC_CTRL_FILTER_COND_OUT]

3492

1

T1

5

T2

27

T3

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21292

1

T1

96

T2

27

T3

5

auto[1]

5902

1

T1

5

T5

33

T6

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23099

1

T1

100

T2

13

T3

1

auto[1]

4095

1

T1

1

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	33	1			T104	24		T293	9		-	-
values[0]	36	1			T294	1		T295	12		T296	23
values[1]	640	1			T108	1		T26	8		T33	19
values[2]	763	1			T1	5		T9	21		T10	22
values[3]	736	1			T6	13		T11	5		T13	17
values[4]	660	1			T3	5		T6	6		T53	19
values[5]	2981	1			T5	33		T12	3		T42	14
values[6]	622	1			T8	4		T9	6		T13	11
values[7]	788	1			T2	27		T9	15		T12	10
values[8]	674	1			T8	14		T11	3		T28	7
values[9]	1213	1			T6	16		T8	5		T11	9
minimum	18048	1			T1	96		T4	20		T7	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	879	1			T1	5		T9	21		T47	1
values[1]	789	1			T10	22		T108	1		T13	21
values[2]	667	1			T6	13		T11	5		T174	1
values[3]	2880	1			T3	5		T5	33		T6	6
values[4]	726	1			T8	4		T53	19		T28	11
values[5]	627	1			T9	21		T12	10		T108	1
values[6]	863	1			T2	27		T8	14		T11	3
values[7]	703	1			T35	6		T130	9		T37	2
values[8]	766	1			T6	16		T8	5		T11	9
values[9]	233	1			T28	12		T36	6		T152	11
minimum	18061	1			T1	96		T4	20		T7	142

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

4130

1

T1

1

T2

12

T5

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T47	1		T108	1		T26	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T1	4		T9	21		T33	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	10		T213	1		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T10	11		T108	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	5		T174	1		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	13		T14	2		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1508	1			T5	33		T6	6		T42	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	1		T12	3		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	4		T53	9		T54	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T28	1		T37	2		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	21		T29	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	10		T108	1		T207	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	7		T186	11		T143	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T2	13		T8	14		T11	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T35	5		T130	9		T14	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T37	1		T142	1		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T6	16		T8	5		T11	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T297	1		T15	3		T189	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T152	6		T175	1		T298	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T28	1		T36	5		T41	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17923	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T33	1		T299	1		T300	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T26	2		T135	12		T247	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	1		T33	5		T205	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	11		T213	9		T246	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	11		T214	7		T216	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T221	2		T250	14		T209	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T221	11		T215	8		T217	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T23	6		T181	6		T212	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	4		T213	10		T54	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T53	10		T54	8		T132	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T28	10		T37	1		T33	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T132	12		T215	8		T231	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T207	17		T137	1		T237	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	4		T186	4		T143	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	14		T28	6		T30	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T35	1		T14	3		T132	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T37	1		T133	2		T39	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T231	9		T189	6		T260	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T189	6		T16	3		T233	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T152	5		T298	1		T233	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T28	11		T36	1		T79	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T13	5		T26	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T299	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T104	12		T293	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T295	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T294	1		T296	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T108	1		T26	6		T301	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T33	14		T205	1		T41	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T47	1		T13	2		T27	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T1	4		T9	21		T10	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	5		T13	8		T213	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	13		T14	2		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	6		T53	9		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	1		T174	1		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T5	33		T42	14		T134	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	3		T28	1		T37	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	4		T9	6		T13	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T137	4		T298	2		T200	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	15		T214	16		T302	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T2	13		T12	10		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T186	11		T130	9		T14	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	14		T11	3		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	379	1			T6	16		T8	5		T11	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T28	1		T36	5		T37	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17923	1			T1	96		T4	20		T7	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T104	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T295	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T296	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T26	2		T247	12		T217	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T33	5		T205	3		T41	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	2		T135	12		T218	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	1		T10	11		T221	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	9		T213	9		T246	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T216	9		T250	3		T235	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T53	10		T221	2		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	4		T54	8		T229	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1076	1			T23	6		T181	6		T212	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T28	10		T37	1		T213	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	4		T132	12		T215	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T137	1		T17	1		T234	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T214	14		T231	12		T147	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	14		T214	15		T207	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T186	4		T14	3		T143	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T28	6		T30	8		T39	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T35	1		T152	5		T172	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T28	11		T36	1		T37	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T13	5		T26	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T47	1		T108	1		T26	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	4		T9	1		T33	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	15		T213	10		T246	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T10	12		T108	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	1		T174	1		T221	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T6	1		T14	2		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T5	2		T6	1		T42	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	5		T12	1		T213	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T8	1		T53	11		T54	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T28	11		T37	2		T33	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	2		T29	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	1		T108	1		T207	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	5		T186	5		T143	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T2	15		T8	1		T11	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T35	5		T130	1		T14	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T37	2		T142	1		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	1		T8	1		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T297	1		T15	3		T189	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T152	6		T175	1		T298	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T28	12		T36	5		T41	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18048	1			T1	96		T4	20		T7	142
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T33	1		T299	11		T300	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T26	1		T27	2		T147	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	1		T9	20		T33	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	6		T215	15		T146	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	10		T214	1		T286	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	4		T177	11		T209	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	12		T221	9		T243	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T5	31		T6	5		T42	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	2		T207	4		T172	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	3		T53	8		T54	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T37	1		T254	2		T248	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T9	19		T132	16		T215	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	9		T207	17		T137	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	6		T186	10		T143	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	12		T8	13		T11	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T35	1		T130	8		T14	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T145	11		T39	2		T260	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	15		T8	4		T11	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T189	2		T176	3		T233	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T152	5		T233	7		T303	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T36	1		T257	8		T79	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T104	13		T293	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T295	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T294	1		T296	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T108	1		T26	7		T301	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T33	7		T205	4		T41	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T47	1		T13	3		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	4		T9	1		T10	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T11	1		T13	12		T213	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	1		T14	2		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	1		T53	11		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	5		T174	1		T54	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T5	2		T42	2		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	1		T28	11		T37	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	1		T9	1		T13	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T137	3		T298	2		T200	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	1		T214	15		T302	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	15		T12	1		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T186	5		T130	1		T14	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T8	1		T11	1		T28	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T6	1		T8	1		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T28	12		T36	5		T37	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18048	1			T1	96		T4	20		T7	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T104	11		T293	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T295	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T296	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T26	1		T301	17		T247	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T33	12		T41	2		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T13	1		T27	2		T146	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	1		T9	20		T10	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	4		T13	5		T215	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	12		T237	17		T156	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	5		T53	8		T171	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T243	16		T236	13		T172	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T5	31		T42	12		T134	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	2		T37	1		T254	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	3		T9	5		T13	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T137	2		T17	1		T264	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T9	14		T214	15		T231	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T2	12		T12	9		T214	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T186	10		T130	8		T14	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T8	13		T11	2		T145	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T6	15		T8	4		T11	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T36	1		T189	2		T176	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

auto[0]

4130

1

T1

1

T2

12

T5

31