Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27194

1

T1

101

T2

27

T3

5

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23726

1

T1

96

T2

27

T3

5

auto[ADC_CTRL_FILTER_COND_OUT]

3468

1

T1

5

T6

16

T8

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21218

1

T1

101

T4

20

T6

22

auto[1]

5976

1

T2

27

T3

5

T5

33

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23099

1

T1

100

T2

13

T3

1

auto[1]

4095

1

T1

1

T2

14

T3

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	260	1			T6	13		T8	14		T130	9
values[0]	3	1			T241	1		T266	2		-	-
values[1]	681	1			T2	27		T3	5		T6	16
values[2]	881	1			T1	5		T12	3		T54	9
values[3]	580	1			T9	15		T53	19		T35	6
values[4]	464	1			T9	6		T38	1		T142	1
values[5]	2863	1			T5	33		T42	14		T134	10
values[6]	704	1			T12	10		T47	1		T23	14
values[7]	771	1			T11	5		T13	11		T221	3
values[8]	732	1			T8	5		T9	21		T11	9
values[9]	1207	1			T6	6		T47	1		T27	3
minimum	18048	1			T1	96		T4	20		T7	142

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	811	1			T1	5		T2	27		T6	16
values[1]	786	1			T9	15		T54	9		T132	18
values[2]	541	1			T9	6		T53	19		T35	6
values[3]	2721	1			T5	33		T42	14		T134	10
values[4]	708	1			T12	10		T23	14		T28	11
values[5]	758	1			T11	5		T47	1		T13	11
values[6]	622	1			T29	1		T33	18		T221	3
values[7]	879	1			T6	6		T8	5		T9	21
values[8]	999	1			T6	13		T47	1		T27	3
values[9]	197	1			T8	14		T174	1		T244	22
minimum	18172	1			T1	96		T3	5		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

4130

1

T1

1

T2

12

T5

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	13		T14	5		T214	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T1	4		T6	16		T8	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T9	15		T132	10		T171	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T54	1		T254	3		T215	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T53	9		T28	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	6		T35	5		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1475	1			T5	33		T42	14		T134	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T54	6		T142	1		T172	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T28	1		T229	1		T267	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	10		T23	8		T14	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T131	1		T172	1		T15	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T11	5		T47	1		T13	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T33	13		T221	1		T137	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T29	1		T206	1		T236	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	6		T8	5		T9	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T108	1		T13	8		T186	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T6	13		T142	1		T143	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T47	1		T27	3		T130	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T8	14		T268	4		T269	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T174	1		T244	22		T219	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17943	1			T1	96		T3	1		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T108	1		T36	5		T33	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T2	14		T14	3		T214	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	1		T10	11		T13	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T132	8		T171	13		T231	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T54	8		T215	8		T260	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T53	10		T28	11		T30	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T35	1		T135	9		T231	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1039	1			T26	2		T181	6		T212	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T54	8		T172	2		T149	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T28	10		T229	17		T248	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T23	6		T132	10		T39	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T215	8		T147	12		T219	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	4		T213	9		T246	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T33	5		T221	2		T137	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T172	7		T156	13		T225	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T28	6		T133	2		T221	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	9		T186	4		T37	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T143	7		T17	1		T208	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T213	10		T172	14		T216	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T268	1		T269	15		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T219	10		T16	3		T271	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	4		T35	1		T13	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T36	1		T286	10		T303	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T6	13		T8	14		T142	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T130	9		T16	2		T264	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T241	1		T266	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T2	13		T3	1		T14	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T6	16		T8	4		T10	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T132	10		T202	1		T171	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T1	4		T12	3		T54	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	15		T53	9		T26	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T35	5		T135	1		T231	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T38	1		T205	1		T202	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T9	6		T142	1		T172	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1500	1			T5	33		T42	14		T134	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	2		T54	6		T132	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T28	1		T131	1		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	10		T47	1		T23	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T221	1		T137	4		T227	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	5		T13	7		T206	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	5		T9	21		T11	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T108	1		T13	8		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T6	6		T28	1		T143	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T47	1		T27	3		T186	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17923	1			T1	96		T4	20		T7	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T222	9		T269	15		T304	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T16	3		T224	3		T305	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T266	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T2	14		T3	4		T14	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T10	11		T13	2		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T132	8		T171	13		T199	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	1		T54	8		T41	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T53	10		T26	2		T28	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T35	1		T135	9		T231	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T205	3		T135	12		T41	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T172	2		T149	8		T268	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1126	1			T181	6		T212	23		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T54	8		T132	10		T39	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T28	10		T215	8		T147	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T23	6		T213	9		T246	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T221	2		T137	1		T139	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T13	4		T171	10		T172	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T33	5		T133	2		T189	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	9		T37	1		T215	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T28	6		T143	7		T221	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T186	4		T37	1		T213	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	1		T13	5		T26	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T2	15		T14	6		T214	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	4		T6	1		T8	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T9	1		T132	9		T171	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T54	9		T254	1		T215	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T53	11		T28	12		T30	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T9	1		T35	5		T135	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T5	2		T42	2		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T54	9		T142	1		T172	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T28	11		T229	18		T267	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	1		T23	10		T14	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T131	1		T172	1		T15	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	1		T47	1		T13	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T33	6		T221	3		T137	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T29	1		T206	1		T236	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T6	1		T8	1		T9	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T108	1		T13	12		T186	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	1		T142	1		T143	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T47	1		T27	1		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T8	1		T268	4		T269	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T174	1		T244	1		T219	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18082	1			T1	96		T3	5		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T108	1		T36	5		T33	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	12		T14	2		T214	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	1		T6	15		T8	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	14		T132	9		T171	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T254	2		T215	9		T260	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T53	8		T189	3		T148	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T9	5		T35	1		T231	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1138	1			T5	31		T42	12		T134	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T54	5		T172	2		T268	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T260	3		T248	2		T274	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	9		T23	4		T132	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T215	8		T147	12		T219	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	4		T13	6		T145	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T33	12		T137	2		T227	34
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T236	13		T172	3		T237	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	5		T8	4		T9	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T13	5		T186	10		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	12		T143	7		T177	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T27	2		T130	8		T145	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T8	13		T268	1		T269	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T244	21		T219	11		T305	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T257	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T36	1		T143	13		T286	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T6	1		T8	1		T142	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T130	1		T16	5		T264	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T241	1		T266	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	15		T3	5		T14	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	1		T8	1		T10	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T132	9		T202	1		T171	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T1	4		T12	1		T54	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	1		T53	11		T26	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T35	5		T135	10		T231	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T38	1		T205	4		T202	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T9	1		T142	1		T172	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1462	1			T5	2		T42	2		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T14	2		T54	9		T132	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T28	11		T131	1		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T12	1		T47	1		T23	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T221	3		T137	3		T227	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	1		T13	5		T206	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	1		T9	1		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T108	1		T13	12		T29	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T6	1		T28	7		T143	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	392	1			T47	1		T27	1		T186	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18048	1			T1	96		T4	20		T7	142
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T6	12		T8	13		T177	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T130	8		T264	15		T224	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T2	12		T14	2		T214	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	15		T8	3		T10	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T132	9		T171	14		T146	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	1		T12	2		T254	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T9	14		T53	8		T26	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T35	1		T231	13		T177	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T189	3		T209	1		T276	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T9	5		T172	2		T177	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1164	1			T5	31		T42	12		T134	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T54	5		T132	20		T39	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T215	8		T147	12		T248	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	9		T23	4		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T137	2		T227	20		T176	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	4		T13	6		T171	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	4		T9	20		T11	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	5		T37	1		T243	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T6	5		T143	7		T221	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T27	2		T186	10		T132	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23064

1

T1

100

T2

15

T3

5

auto[1]

auto[0]

4130

1

T1

1

T2

12

T5

31