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Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 27194 1 T1 101 T2 27 T3 5



Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[ADC_CTRL_FILTER_COND_IN] 23541 1 T1 96 T4 20 T5 33
auto[ADC_CTRL_FILTER_COND_OUT] 3653 1 T1 5 T2 27 T3 5



Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 20838 1 T1 96 T2 27 T3 5
auto[1] 6356 1 T1 5 T5 33 T6 35



Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 23099 1 T1 100 T2 13 T3 1
auto[1] 4095 1 T1 1 T2 14 T3 4



Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
maximum 479 1 T11 3 T30 9 T37 3
values[0] 10 1 T36 6 T15 4 - -
values[1] 640 1 T10 22 T13 17 T26 8
values[2] 688 1 T6 16 T11 5 T47 1
values[3] 1049 1 T3 5 T213 10 T174 1
values[4] 547 1 T9 21 T12 10 T108 1
values[5] 753 1 T8 4 T9 15 T12 3
values[6] 517 1 T2 27 T6 13 T47 1
values[7] 586 1 T1 5 T6 6 T28 23
values[8] 814 1 T8 5 T11 9 T29 1
values[9] 3063 1 T5 33 T8 14 T9 6
minimum 18048 1 T1 96 T4 20 T7 142



Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 707 1 T10 22 T13 17 T26 8
values[1] 751 1 T3 5 T6 16 T11 5
values[2] 937 1 T108 1 T201 1 T213 10
values[3] 595 1 T9 21 T12 13 T23 14
values[4] 723 1 T2 27 T8 4 T9 15
values[5] 502 1 T6 13 T47 1 T28 11
values[6] 2839 1 T1 5 T5 33 T6 6
values[7] 817 1 T8 5 T11 9 T27 3
values[8] 903 1 T8 14 T9 6 T11 3
values[9] 229 1 T108 1 T33 18 T221 21
minimum 18191 1 T1 96 T4 20 T7 142



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 23064 1 T1 100 T2 15 T3 5
auto[1] 4130 1 T1 1 T2 12 T5 31



Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 164 1 T13 8 T26 6 T204 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 242 1 T10 11 T246 1 T214 16
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 147 1 T108 1 T54 6 T131 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 281 1 T3 1 T6 16 T11 5
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 241 1 T201 1 T213 1 T33 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 308 1 T108 1 T54 1 T142 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 152 1 T12 13 T28 1 T37 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 190 1 T9 21 T23 8 T132 10
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 174 1 T53 9 T35 5 T229 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 199 1 T2 13 T8 4 T9 15
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 143 1 T47 1 T28 1 T133 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 131 1 T6 13 T221 1 T297 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 1453 1 T5 33 T42 14 T134 10
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 212 1 T1 4 T6 6 T135 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 320 1 T11 9 T29 1 T174 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 161 1 T8 5 T27 3 T38 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 220 1 T9 6 T11 3 T30 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 240 1 T8 14 T13 9 T37 2
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 69 1 T108 1 T33 13 T147 13
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 68 1 T221 10 T237 1 T211 9
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17948 1 T1 96 T4 20 T7 142
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 36 1 T36 5 T143 8 T136 8
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 154 1 T13 9 T26 2 T260 4
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 147 1 T10 11 T246 12 T214 14
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 118 1 T54 8 T215 21 T216 21
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 205 1 T3 4 T207 11 T172 7
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 198 1 T213 9 T33 2 T132 12
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 190 1 T54 8 T171 10 T247 12
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 123 1 T28 6 T37 1 T189 3
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 130 1 T23 6 T132 8 T231 12
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 169 1 T53 10 T35 1 T229 17
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 181 1 T2 14 T152 5 T41 1
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 99 1 T28 10 T133 2 T137 1
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 129 1 T221 2 T139 13 T148 15
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 1020 1 T28 11 T181 6 T212 23
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 154 1 T1 1 T135 12 T172 16
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 209 1 T214 15 T171 13 T251 13
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 127 1 T132 10 T135 9 T189 6
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 217 1 T30 8 T186 4 T14 3
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 226 1 T13 6 T37 1 T215 8
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 49 1 T33 5 T147 12 T261 9
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 43 1 T221 11 T237 1 T211 8
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 154 1 T35 1 T13 5 T26 2
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 53 1 T36 1 T143 7 T15 1



Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] -- -- 2
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 158 1 T11 3 T30 1 T14 5
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 99 1 T37 2 T215 9 T211 9
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 8 1 T36 5 T15 3 - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 175 1 T13 8 T26 6 T204 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 181 1 T10 11 T143 8 T41 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 110 1 T108 1 T131 1 T172 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 288 1 T6 16 T11 5 T47 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 256 1 T213 1 T33 1 T54 6
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 334 1 T3 1 T174 1 T14 2
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 116 1 T12 10 T28 1 T201 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 198 1 T9 21 T108 1 T54 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 207 1 T12 3 T53 9 T229 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 196 1 T8 4 T9 15 T23 8
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 125 1 T47 1 T35 5 T133 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 164 1 T2 13 T6 13 T41 3
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 145 1 T28 2 T213 1 T243 17
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 148 1 T1 4 T6 6 T221 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 300 1 T11 9 T29 1 T130 9
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 194 1 T8 5 T38 1 T142 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 1516 1 T5 33 T9 6 T108 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 258 1 T8 14 T13 9 T27 3
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17923 1 T1 96 T4 20 T7 142
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 155 1 T30 8 T14 3 T33 5
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 67 1 T37 1 T215 8 T211 8
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 2 1 T36 1 T15 1 - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 159 1 T13 9 T26 2 T260 4
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 125 1 T10 11 T143 7 T41 6
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 93 1 T216 12 T148 11 T235 1
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 197 1 T246 12 T214 14 T172 7
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 223 1 T213 9 T33 2 T54 8
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 236 1 T3 4 T207 11 T171 10
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 99 1 T28 6 T37 1 T39 3
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 134 1 T54 8 T132 8 T231 12
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 180 1 T53 10 T229 17 T249 11
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 170 1 T23 6 T152 5 T189 4
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 69 1 T35 1 T133 2 T137 1
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 159 1 T2 14 T41 1 T139 13
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 166 1 T28 21 T213 10 T215 8
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 127 1 T1 1 T221 2 T172 14
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 197 1 T214 15 T251 13 T217 10
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 123 1 T132 10 T135 12 T172 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 1044 1 T186 4 T181 6 T212 23
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 245 1 T13 6 T221 11 T135 9
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 125 1 T35 1 T13 5 T26 2



Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4


Covered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 193 1 T13 12 T26 7 T204 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 186 1 T10 12 T246 13 T214 15
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 146 1 T108 1 T54 9 T131 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 255 1 T3 5 T6 1 T11 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 243 1 T201 1 T213 10 T33 3
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 236 1 T108 1 T54 9 T142 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 160 1 T12 2 T28 7 T37 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 175 1 T9 1 T23 10 T132 9
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 202 1 T53 11 T35 5 T229 18
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 214 1 T2 15 T8 1 T9 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 135 1 T47 1 T28 11 T133 3
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 164 1 T6 1 T221 3 T297 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 1358 1 T5 2 T42 2 T134 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 196 1 T1 4 T6 1 T135 13
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 258 1 T11 1 T29 1 T174 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 157 1 T8 1 T27 1 T38 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 260 1 T9 1 T11 1 T30 9
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 267 1 T8 1 T13 8 T37 2
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 61 1 T108 1 T33 6 T147 13
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 52 1 T221 12 T237 2 T211 9
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 18080 1 T1 96 T4 20 T7 142
auto[0] minimum auto[ADC_CTRL_FILTER_COND_OUT] 66 1 T36 5 T143 8 T136 1
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 125 1 T13 5 T26 1 T260 3
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 203 1 T10 10 T214 15 T146 8
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 119 1 T54 5 T254 2 T215 15
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 231 1 T6 15 T11 4 T145 13
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 196 1 T143 13 T132 16 T39 2
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 262 1 T145 11 T136 11 T171 12
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 115 1 T12 11 T146 17 T189 11
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 145 1 T9 20 T23 4 T132 9
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 141 1 T53 8 T35 1 T227 20
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 166 1 T2 12 T8 3 T9 14
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 107 1 T243 16 T236 13 T136 10
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 96 1 T6 12 T139 10 T148 11
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 1115 1 T5 31 T42 12 T134 9
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 170 1 T1 1 T6 5 T172 12
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 271 1 T11 8 T214 14 T171 14
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 131 1 T8 4 T27 2 T132 20
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 177 1 T9 5 T11 2 T186 10
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 199 1 T8 13 T13 7 T37 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 57 1 T33 12 T147 12 T261 9
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 59 1 T221 9 T211 8 T286 8
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 22 1 T259 8 T306 8 T307 6
auto[1] minimum auto[ADC_CTRL_FILTER_COND_OUT] 23 1 T36 1 T143 7 T136 7



Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 5 43 89.58 5


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1


Covered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 180 1 T11 1 T30 9 T14 6
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 81 1 T37 2 T215 9 T211 9
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 8 1 T36 5 T15 3 - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 193 1 T13 12 T26 7 T204 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 161 1 T10 12 T143 8 T41 7
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 122 1 T108 1 T131 1 T172 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 243 1 T6 1 T11 1 T47 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 267 1 T213 10 T33 3 T54 9
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 287 1 T3 5 T174 1 T14 2
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 130 1 T12 1 T28 7 T201 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 173 1 T9 1 T108 1 T54 9
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 217 1 T12 1 T53 11 T229 18
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 211 1 T8 1 T9 1 T23 10
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 100 1 T47 1 T35 5 T133 3
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 195 1 T2 15 T6 1 T41 2
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 212 1 T28 23 T213 11 T243 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 156 1 T1 4 T6 1 T221 3
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 252 1 T11 1 T29 1 T130 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 164 1 T8 1 T38 1 T142 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 1375 1 T5 2 T9 1 T108 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 289 1 T8 1 T13 8 T27 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 18048 1 T1 96 T4 20 T7 142
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 133 1 T11 2 T14 2 T33 12
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 85 1 T37 1 T215 8 T211 8
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 2 1 T36 1 T15 1 - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 141 1 T13 5 T26 1 T260 3
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 145 1 T10 10 T143 7 T136 7
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 81 1 T238 2 T148 3 T264 16
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 242 1 T6 15 T11 4 T145 13
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 212 1 T54 5 T143 13 T132 16
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 283 1 T145 11 T207 4 T171 12
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 85 1 T12 9 T39 2 T189 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 159 1 T9 20 T132 9 T136 11
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 170 1 T12 2 T53 8 T227 20
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 155 1 T8 3 T9 14 T23 4
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 94 1 T35 1 T236 13 T136 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 128 1 T2 12 T6 12 T41 2
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 99 1 T243 16 T215 9 T189 2
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 119 1 T1 1 T6 5 T172 10
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 245 1 T11 8 T130 8 T214 14
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 153 1 T8 4 T132 20 T172 2
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 1185 1 T5 31 T9 5 T42 12
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 214 1 T8 13 T13 7 T27 2



Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cpclk_gate_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 23064 1 T1 100 T2 15 T3 5
auto[1] auto[0] 4130 1 T1 1 T2 12 T5 31

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