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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.66 99.07 96.62 100.00 100.00 98.83 98.33 90.77


Total test records in report: 917
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T323 /workspace/coverage/default/31.adc_ctrl_filters_wakeup.929931461 Jul 24 07:12:40 PM PDT 24 Jul 24 07:20:26 PM PDT 24 204072583427 ps
T793 /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2267521631 Jul 24 07:12:27 PM PDT 24 Jul 24 07:12:43 PM PDT 24 33029339748 ps
T49 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2906796389 Jul 24 05:22:33 PM PDT 24 Jul 24 05:22:37 PM PDT 24 2447388314 ps
T59 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3786554714 Jul 24 05:22:44 PM PDT 24 Jul 24 05:22:47 PM PDT 24 394894957 ps
T794 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.155070334 Jul 24 05:22:53 PM PDT 24 Jul 24 05:22:54 PM PDT 24 380216784 ps
T795 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3298728802 Jul 24 05:22:48 PM PDT 24 Jul 24 05:22:49 PM PDT 24 422226147 ps
T796 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3540374224 Jul 24 05:22:48 PM PDT 24 Jul 24 05:22:50 PM PDT 24 418740115 ps
T797 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1875084271 Jul 24 05:22:46 PM PDT 24 Jul 24 05:22:47 PM PDT 24 508577205 ps
T55 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.4270560045 Jul 24 05:22:47 PM PDT 24 Jul 24 05:23:00 PM PDT 24 8618410380 ps
T52 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.618912503 Jul 24 05:22:49 PM PDT 24 Jul 24 05:22:50 PM PDT 24 332137723 ps
T798 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3057558770 Jul 24 05:22:48 PM PDT 24 Jul 24 05:22:49 PM PDT 24 418010346 ps
T50 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1946344903 Jul 24 05:22:40 PM PDT 24 Jul 24 05:22:47 PM PDT 24 2661186463 ps
T129 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4219783147 Jul 24 05:22:25 PM PDT 24 Jul 24 05:22:28 PM PDT 24 769918301 ps
T63 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.583668627 Jul 24 05:22:35 PM PDT 24 Jul 24 05:22:38 PM PDT 24 994441495 ps
T56 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2596735096 Jul 24 05:22:41 PM PDT 24 Jul 24 05:22:48 PM PDT 24 8344822275 ps
T110 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.421494714 Jul 24 05:22:47 PM PDT 24 Jul 24 05:22:49 PM PDT 24 473995399 ps
T799 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1071960265 Jul 24 05:22:30 PM PDT 24 Jul 24 05:22:31 PM PDT 24 423894810 ps
T85 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1498497493 Jul 24 05:22:32 PM PDT 24 Jul 24 05:22:34 PM PDT 24 464597087 ps
T57 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1504814575 Jul 24 05:22:42 PM PDT 24 Jul 24 05:22:52 PM PDT 24 4198378816 ps
T800 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3283406378 Jul 24 05:22:51 PM PDT 24 Jul 24 05:22:52 PM PDT 24 521932120 ps
T801 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3484653445 Jul 24 05:22:51 PM PDT 24 Jul 24 05:22:53 PM PDT 24 446454568 ps
T51 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3989572150 Jul 24 05:22:44 PM PDT 24 Jul 24 05:22:47 PM PDT 24 4881084938 ps
T69 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1178233732 Jul 24 05:22:31 PM PDT 24 Jul 24 05:22:42 PM PDT 24 4290178583 ps
T111 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4209178020 Jul 24 05:22:30 PM PDT 24 Jul 24 05:22:31 PM PDT 24 1142412997 ps
T65 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3889909071 Jul 24 05:22:33 PM PDT 24 Jul 24 05:22:37 PM PDT 24 559340618 ps
T125 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1012512356 Jul 24 05:22:30 PM PDT 24 Jul 24 05:22:32 PM PDT 24 431761056 ps
T70 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3980176562 Jul 24 05:22:33 PM PDT 24 Jul 24 05:22:35 PM PDT 24 413072998 ps
T90 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2903628336 Jul 24 05:22:47 PM PDT 24 Jul 24 05:22:49 PM PDT 24 407709960 ps
T126 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2339021981 Jul 24 05:22:25 PM PDT 24 Jul 24 05:22:28 PM PDT 24 2272009450 ps
T802 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3661761476 Jul 24 05:22:38 PM PDT 24 Jul 24 05:22:40 PM PDT 24 473912680 ps
T342 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1385165560 Jul 24 05:22:50 PM PDT 24 Jul 24 05:22:53 PM PDT 24 4195359114 ps
T112 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1033438572 Jul 24 05:22:39 PM PDT 24 Jul 24 05:22:40 PM PDT 24 496714102 ps
T127 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.454543890 Jul 24 05:22:59 PM PDT 24 Jul 24 05:23:01 PM PDT 24 499383852 ps
T71 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1084045188 Jul 24 05:22:27 PM PDT 24 Jul 24 05:22:30 PM PDT 24 471627519 ps
T128 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.760865783 Jul 24 05:22:44 PM PDT 24 Jul 24 05:22:47 PM PDT 24 2112757889 ps
T803 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4265442142 Jul 24 05:22:43 PM PDT 24 Jul 24 05:22:45 PM PDT 24 449684713 ps
T340 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3343839047 Jul 24 05:22:29 PM PDT 24 Jul 24 05:22:36 PM PDT 24 8500438622 ps
T113 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.15744608 Jul 24 05:22:40 PM PDT 24 Jul 24 05:22:41 PM PDT 24 523060263 ps
T804 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.509566270 Jul 24 05:22:26 PM PDT 24 Jul 24 05:22:36 PM PDT 24 5337746453 ps
T805 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1825790297 Jul 24 05:22:32 PM PDT 24 Jul 24 05:22:44 PM PDT 24 4211630814 ps
T806 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3586018606 Jul 24 05:22:50 PM PDT 24 Jul 24 05:22:56 PM PDT 24 2923162905 ps
T114 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2748382670 Jul 24 05:22:49 PM PDT 24 Jul 24 05:22:50 PM PDT 24 365242173 ps
T807 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.976165196 Jul 24 05:22:37 PM PDT 24 Jul 24 05:22:39 PM PDT 24 2660858943 ps
T808 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1863061073 Jul 24 05:22:32 PM PDT 24 Jul 24 05:22:35 PM PDT 24 1094194910 ps
T115 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3874921775 Jul 24 05:22:27 PM PDT 24 Jul 24 05:22:33 PM PDT 24 1122834967 ps
T809 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3250796129 Jul 24 05:22:35 PM PDT 24 Jul 24 05:22:39 PM PDT 24 1862074778 ps
T810 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2075800045 Jul 24 05:22:25 PM PDT 24 Jul 24 05:22:26 PM PDT 24 498161715 ps
T341 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3457681373 Jul 24 05:22:28 PM PDT 24 Jul 24 05:22:49 PM PDT 24 8724324954 ps
T811 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3347846458 Jul 24 05:22:40 PM PDT 24 Jul 24 05:22:42 PM PDT 24 457866637 ps
T116 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.997011795 Jul 24 05:22:37 PM PDT 24 Jul 24 05:22:39 PM PDT 24 513642847 ps
T812 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2016311600 Jul 24 05:22:52 PM PDT 24 Jul 24 05:22:54 PM PDT 24 486983506 ps
T813 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3692244166 Jul 24 05:22:43 PM PDT 24 Jul 24 05:22:45 PM PDT 24 510543130 ps
T814 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1492960152 Jul 24 05:22:40 PM PDT 24 Jul 24 05:22:42 PM PDT 24 1992710609 ps
T815 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3621973921 Jul 24 05:22:50 PM PDT 24 Jul 24 05:22:51 PM PDT 24 353364826 ps
T816 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1268048229 Jul 24 05:22:32 PM PDT 24 Jul 24 05:23:32 PM PDT 24 52967046571 ps
T817 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.83824392 Jul 24 05:22:51 PM PDT 24 Jul 24 05:22:52 PM PDT 24 521190018 ps
T818 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2814099962 Jul 24 05:22:33 PM PDT 24 Jul 24 05:22:35 PM PDT 24 665425619 ps
T819 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2135155177 Jul 24 05:22:45 PM PDT 24 Jul 24 05:22:47 PM PDT 24 447142545 ps
T820 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2711053399 Jul 24 05:22:56 PM PDT 24 Jul 24 05:22:56 PM PDT 24 717168869 ps
T821 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3050770234 Jul 24 05:22:58 PM PDT 24 Jul 24 05:23:14 PM PDT 24 4730928267 ps
T822 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3109519931 Jul 24 05:22:45 PM PDT 24 Jul 24 05:22:46 PM PDT 24 476175419 ps
T823 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.727746818 Jul 24 05:22:39 PM PDT 24 Jul 24 05:22:41 PM PDT 24 477339900 ps
T824 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1292793590 Jul 24 05:22:43 PM PDT 24 Jul 24 05:22:49 PM PDT 24 4438868209 ps
T825 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2678633316 Jul 24 05:22:36 PM PDT 24 Jul 24 05:22:43 PM PDT 24 4558693618 ps
T117 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1063442903 Jul 24 05:22:27 PM PDT 24 Jul 24 05:22:39 PM PDT 24 14439737916 ps
T826 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3784459063 Jul 24 05:22:42 PM PDT 24 Jul 24 05:22:43 PM PDT 24 403130694 ps
T118 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.804424939 Jul 24 05:22:24 PM PDT 24 Jul 24 05:22:25 PM PDT 24 1107181614 ps
T119 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2904430771 Jul 24 05:22:44 PM PDT 24 Jul 24 05:22:45 PM PDT 24 457315892 ps
T827 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3512428407 Jul 24 05:22:37 PM PDT 24 Jul 24 05:22:39 PM PDT 24 2075469635 ps
T828 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3531481024 Jul 24 05:22:36 PM PDT 24 Jul 24 05:22:37 PM PDT 24 385649402 ps
T66 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3277584885 Jul 24 05:22:41 PM PDT 24 Jul 24 05:22:44 PM PDT 24 446949615 ps
T829 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3083856323 Jul 24 05:22:35 PM PDT 24 Jul 24 05:22:37 PM PDT 24 555516406 ps
T830 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2254350632 Jul 24 05:22:34 PM PDT 24 Jul 24 05:22:36 PM PDT 24 474872117 ps
T831 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.4243956029 Jul 24 05:22:56 PM PDT 24 Jul 24 05:22:58 PM PDT 24 290008871 ps
T832 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3192638197 Jul 24 05:22:39 PM PDT 24 Jul 24 05:22:40 PM PDT 24 469639152 ps
T833 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1773668497 Jul 24 05:22:36 PM PDT 24 Jul 24 05:22:40 PM PDT 24 528772110 ps
T834 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3612137577 Jul 24 05:22:51 PM PDT 24 Jul 24 05:22:52 PM PDT 24 540208224 ps
T835 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.712021405 Jul 24 05:22:48 PM PDT 24 Jul 24 05:22:50 PM PDT 24 445814854 ps
T836 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4043936611 Jul 24 05:22:37 PM PDT 24 Jul 24 05:22:39 PM PDT 24 428983273 ps
T837 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4157504411 Jul 24 05:22:28 PM PDT 24 Jul 24 05:22:31 PM PDT 24 665964906 ps
T120 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2796038872 Jul 24 05:22:37 PM PDT 24 Jul 24 05:22:42 PM PDT 24 963026079 ps
T838 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.417637354 Jul 24 05:22:43 PM PDT 24 Jul 24 05:22:45 PM PDT 24 556652664 ps
T839 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3501002217 Jul 24 05:22:36 PM PDT 24 Jul 24 05:22:39 PM PDT 24 490151270 ps
T123 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.201003936 Jul 24 05:22:38 PM PDT 24 Jul 24 05:22:39 PM PDT 24 542770976 ps
T343 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3493620767 Jul 24 05:22:42 PM PDT 24 Jul 24 05:22:53 PM PDT 24 4344929541 ps
T124 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2049654233 Jul 24 05:22:50 PM PDT 24 Jul 24 05:22:52 PM PDT 24 493807138 ps
T840 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3182974016 Jul 24 05:22:47 PM PDT 24 Jul 24 05:22:48 PM PDT 24 369332479 ps
T841 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.583902874 Jul 24 05:22:52 PM PDT 24 Jul 24 05:22:53 PM PDT 24 359856260 ps
T842 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.4189714871 Jul 24 05:22:54 PM PDT 24 Jul 24 05:22:58 PM PDT 24 4906023126 ps
T843 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3474438337 Jul 24 05:22:26 PM PDT 24 Jul 24 05:22:29 PM PDT 24 850616154 ps
T844 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4229228918 Jul 24 05:22:36 PM PDT 24 Jul 24 05:22:38 PM PDT 24 378312132 ps
T845 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3720134979 Jul 24 05:22:30 PM PDT 24 Jul 24 05:22:38 PM PDT 24 4082076303 ps
T846 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2192370805 Jul 24 05:22:33 PM PDT 24 Jul 24 05:22:35 PM PDT 24 432865860 ps
T847 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4225730709 Jul 24 05:22:49 PM PDT 24 Jul 24 05:22:50 PM PDT 24 479114019 ps
T121 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2257442943 Jul 24 05:22:37 PM PDT 24 Jul 24 05:22:55 PM PDT 24 29705718080 ps
T848 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1169927975 Jul 24 05:22:52 PM PDT 24 Jul 24 05:22:53 PM PDT 24 527458323 ps
T849 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3461055368 Jul 24 05:22:42 PM PDT 24 Jul 24 05:22:44 PM PDT 24 683148465 ps
T850 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2106052203 Jul 24 05:22:46 PM PDT 24 Jul 24 05:22:48 PM PDT 24 508570553 ps
T851 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3957324656 Jul 24 05:23:02 PM PDT 24 Jul 24 05:23:05 PM PDT 24 564158476 ps
T852 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1270736052 Jul 24 05:22:28 PM PDT 24 Jul 24 05:22:30 PM PDT 24 691456730 ps
T853 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1070424333 Jul 24 05:22:31 PM PDT 24 Jul 24 05:22:32 PM PDT 24 446787800 ps
T854 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1005171395 Jul 24 05:22:44 PM PDT 24 Jul 24 05:22:46 PM PDT 24 799855474 ps
T855 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2678872385 Jul 24 05:22:39 PM PDT 24 Jul 24 05:22:41 PM PDT 24 458591184 ps
T122 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.553942377 Jul 24 05:22:38 PM PDT 24 Jul 24 05:22:39 PM PDT 24 402905557 ps
T856 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1005378372 Jul 24 05:22:28 PM PDT 24 Jul 24 05:22:31 PM PDT 24 1133058799 ps
T857 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4142173989 Jul 24 05:22:37 PM PDT 24 Jul 24 05:22:39 PM PDT 24 532491306 ps
T858 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1182929948 Jul 24 05:22:27 PM PDT 24 Jul 24 05:22:29 PM PDT 24 1073273098 ps
T859 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2010777342 Jul 24 05:22:49 PM PDT 24 Jul 24 05:22:50 PM PDT 24 315740439 ps
T860 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2016327680 Jul 24 05:22:33 PM PDT 24 Jul 24 05:22:36 PM PDT 24 478236745 ps
T861 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.819532532 Jul 24 05:23:00 PM PDT 24 Jul 24 05:23:03 PM PDT 24 463225558 ps
T862 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4234161382 Jul 24 05:22:45 PM PDT 24 Jul 24 05:22:46 PM PDT 24 401042608 ps
T863 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.258895917 Jul 24 05:22:34 PM PDT 24 Jul 24 05:22:36 PM PDT 24 373365216 ps
T864 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.768827789 Jul 24 05:22:45 PM PDT 24 Jul 24 05:22:48 PM PDT 24 508992993 ps
T865 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3291557162 Jul 24 05:22:51 PM PDT 24 Jul 24 05:22:52 PM PDT 24 410248536 ps
T866 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2934434017 Jul 24 05:23:03 PM PDT 24 Jul 24 05:23:05 PM PDT 24 448340159 ps
T867 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4157669053 Jul 24 05:22:51 PM PDT 24 Jul 24 05:22:52 PM PDT 24 318367877 ps
T868 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1703030620 Jul 24 05:22:47 PM PDT 24 Jul 24 05:22:49 PM PDT 24 322097725 ps
T869 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1896640839 Jul 24 05:22:58 PM PDT 24 Jul 24 05:22:59 PM PDT 24 527155341 ps
T870 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3229094668 Jul 24 05:22:43 PM PDT 24 Jul 24 05:22:45 PM PDT 24 4680822846 ps
T871 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3315449297 Jul 24 05:22:27 PM PDT 24 Jul 24 05:22:28 PM PDT 24 452126058 ps
T872 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2252555869 Jul 24 05:23:04 PM PDT 24 Jul 24 05:23:05 PM PDT 24 346373141 ps
T873 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.183504452 Jul 24 05:22:44 PM PDT 24 Jul 24 05:22:46 PM PDT 24 507399565 ps
T874 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3307226473 Jul 24 05:22:51 PM PDT 24 Jul 24 05:22:53 PM PDT 24 369719629 ps
T875 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.902967877 Jul 24 05:22:47 PM PDT 24 Jul 24 05:22:48 PM PDT 24 427650815 ps
T876 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1692351817 Jul 24 05:22:40 PM PDT 24 Jul 24 05:22:41 PM PDT 24 315116146 ps
T877 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3564471722 Jul 24 05:22:32 PM PDT 24 Jul 24 05:22:34 PM PDT 24 495137234 ps
T878 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2736028591 Jul 24 05:22:43 PM PDT 24 Jul 24 05:22:54 PM PDT 24 4831192251 ps
T879 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2768516423 Jul 24 05:22:34 PM PDT 24 Jul 24 05:22:36 PM PDT 24 554108864 ps
T880 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.154807707 Jul 24 05:22:52 PM PDT 24 Jul 24 05:22:53 PM PDT 24 454612236 ps
T881 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1091835493 Jul 24 05:22:46 PM PDT 24 Jul 24 05:22:47 PM PDT 24 350619607 ps
T882 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.30356421 Jul 24 05:22:51 PM PDT 24 Jul 24 05:22:54 PM PDT 24 506621950 ps
T883 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.874645185 Jul 24 05:22:28 PM PDT 24 Jul 24 05:22:32 PM PDT 24 5154092133 ps
T884 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1176589590 Jul 24 05:22:52 PM PDT 24 Jul 24 05:22:54 PM PDT 24 304429011 ps
T344 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3045482124 Jul 24 05:22:49 PM PDT 24 Jul 24 05:23:00 PM PDT 24 4429012965 ps
T885 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.412467684 Jul 24 05:22:48 PM PDT 24 Jul 24 05:22:50 PM PDT 24 428530075 ps
T886 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.630781959 Jul 24 05:23:00 PM PDT 24 Jul 24 05:23:00 PM PDT 24 378811871 ps
T887 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1520106172 Jul 24 05:22:31 PM PDT 24 Jul 24 05:22:32 PM PDT 24 544190881 ps
T888 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3263832419 Jul 24 05:22:36 PM PDT 24 Jul 24 05:22:42 PM PDT 24 2062768329 ps
T889 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3634221811 Jul 24 05:22:42 PM PDT 24 Jul 24 05:22:48 PM PDT 24 4423390386 ps
T890 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3281838794 Jul 24 05:22:26 PM PDT 24 Jul 24 05:23:28 PM PDT 24 52778056233 ps
T891 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1326116394 Jul 24 05:22:49 PM PDT 24 Jul 24 05:22:53 PM PDT 24 4990632609 ps
T892 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.4040921882 Jul 24 05:22:53 PM PDT 24 Jul 24 05:22:54 PM PDT 24 430049569 ps
T893 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2416711178 Jul 24 05:22:26 PM PDT 24 Jul 24 05:22:28 PM PDT 24 459623081 ps
T894 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3751805837 Jul 24 05:23:02 PM PDT 24 Jul 24 05:23:04 PM PDT 24 528653808 ps
T895 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3529543286 Jul 24 05:22:38 PM PDT 24 Jul 24 05:22:40 PM PDT 24 491815584 ps
T896 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1341998351 Jul 24 05:22:59 PM PDT 24 Jul 24 05:23:00 PM PDT 24 483579222 ps
T897 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1619441294 Jul 24 05:22:29 PM PDT 24 Jul 24 05:22:31 PM PDT 24 458305928 ps
T898 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2163769408 Jul 24 05:22:34 PM PDT 24 Jul 24 05:22:37 PM PDT 24 772015940 ps
T899 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1561810094 Jul 24 05:22:35 PM PDT 24 Jul 24 05:22:37 PM PDT 24 369398869 ps
T900 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.45492979 Jul 24 05:22:47 PM PDT 24 Jul 24 05:22:49 PM PDT 24 390006890 ps
T901 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.614501082 Jul 24 05:22:35 PM PDT 24 Jul 24 05:22:41 PM PDT 24 9117797450 ps
T902 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3229866154 Jul 24 05:22:44 PM PDT 24 Jul 24 05:22:47 PM PDT 24 520307303 ps
T903 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3011854798 Jul 24 05:22:43 PM PDT 24 Jul 24 05:22:45 PM PDT 24 536078702 ps
T904 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1784907657 Jul 24 05:22:48 PM PDT 24 Jul 24 05:23:10 PM PDT 24 8632077525 ps
T905 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.734603722 Jul 24 05:22:43 PM PDT 24 Jul 24 05:22:45 PM PDT 24 520081570 ps
T906 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3283318618 Jul 24 05:22:36 PM PDT 24 Jul 24 05:22:41 PM PDT 24 8606129373 ps
T907 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1314448419 Jul 24 05:22:51 PM PDT 24 Jul 24 05:22:52 PM PDT 24 418955816 ps
T908 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2473617588 Jul 24 05:22:35 PM PDT 24 Jul 24 05:22:58 PM PDT 24 8278367879 ps
T909 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3449240087 Jul 24 05:22:47 PM PDT 24 Jul 24 05:23:01 PM PDT 24 4938821181 ps
T910 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3556360907 Jul 24 05:22:46 PM PDT 24 Jul 24 05:22:55 PM PDT 24 2432430471 ps
T911 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.935066525 Jul 24 05:22:48 PM PDT 24 Jul 24 05:22:50 PM PDT 24 503010822 ps
T912 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2112058075 Jul 24 05:22:38 PM PDT 24 Jul 24 05:22:55 PM PDT 24 4386629163 ps
T913 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1711762859 Jul 24 05:22:44 PM PDT 24 Jul 24 05:22:47 PM PDT 24 324853932 ps
T914 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1428726722 Jul 24 05:22:26 PM PDT 24 Jul 24 05:22:29 PM PDT 24 1753157463 ps
T915 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1659576513 Jul 24 05:22:43 PM PDT 24 Jul 24 05:22:48 PM PDT 24 4998200700 ps
T916 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3433591374 Jul 24 05:22:29 PM PDT 24 Jul 24 05:22:31 PM PDT 24 559681624 ps
T917 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1594550357 Jul 24 05:22:47 PM PDT 24 Jul 24 05:22:48 PM PDT 24 522152929 ps

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2310669811
Short name T1
Test name
Test status
Simulation time 71250247699 ps
CPU time 108.55 seconds
Started Jul 24 07:16:44 PM PDT 24
Finished Jul 24 07:18:33 PM PDT 24
Peak memory 210020 kb
Host smart-e7bcaea6-f174-41ac-8ee1-ec2663c0cd00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310669811 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2310669811
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3683947348
Short name T11
Test name
Test status
Simulation time 593613601582 ps
CPU time 870.54 seconds
Started Jul 24 07:15:13 PM PDT 24
Finished Jul 24 07:29:44 PM PDT 24
Peak memory 201332 kb
Host smart-045be5d5-1eb7-4f8c-a78e-bd3472038468
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683947348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3683947348
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2981444824
Short name T13
Test name
Test status
Simulation time 339902875179 ps
CPU time 89.39 seconds
Started Jul 24 07:10:28 PM PDT 24
Finished Jul 24 07:11:58 PM PDT 24
Peak memory 211664 kb
Host smart-61588fa0-53f6-4402-b23e-fb2ff0d5740d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981444824 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2981444824
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1406291084
Short name T29
Test name
Test status
Simulation time 344927547318 ps
CPU time 951.12 seconds
Started Jul 24 07:12:33 PM PDT 24
Finished Jul 24 07:28:25 PM PDT 24
Peak memory 209884 kb
Host smart-cdc64011-a812-4f27-a050-3678f1d10eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406291084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1406291084
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2208552219
Short name T189
Test name
Test status
Simulation time 617943864061 ps
CPU time 372.3 seconds
Started Jul 24 07:10:53 PM PDT 24
Finished Jul 24 07:17:05 PM PDT 24
Peak memory 216124 kb
Host smart-c7fed170-3cbb-446d-b5f1-c88b32a5253f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208552219 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2208552219
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2039531580
Short name T14
Test name
Test status
Simulation time 59278637173 ps
CPU time 155.61 seconds
Started Jul 24 07:12:26 PM PDT 24
Finished Jul 24 07:15:02 PM PDT 24
Peak memory 210388 kb
Host smart-168f11d8-0fd0-484c-aab0-390a97b4d71f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039531580 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2039531580
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1655787643
Short name T132
Test name
Test status
Simulation time 515881702064 ps
CPU time 1142.81 seconds
Started Jul 24 07:10:37 PM PDT 24
Finished Jul 24 07:29:40 PM PDT 24
Peak memory 201252 kb
Host smart-612b7df5-049c-4bc1-8f4d-f74fbfbd1741
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655787643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1655787643
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.237988247
Short name T172
Test name
Test status
Simulation time 451991718422 ps
CPU time 254.9 seconds
Started Jul 24 07:15:21 PM PDT 24
Finished Jul 24 07:19:36 PM PDT 24
Peak memory 209976 kb
Host smart-fe0822e5-650c-48ae-9f50-d49426ed571f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237988247 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.237988247
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3992122629
Short name T6
Test name
Test status
Simulation time 551738238740 ps
CPU time 625.89 seconds
Started Jul 24 07:14:17 PM PDT 24
Finished Jul 24 07:24:43 PM PDT 24
Peak memory 201184 kb
Host smart-6d215a8c-220d-470b-948a-d69606fc72a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992122629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3992122629
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3786554714
Short name T59
Test name
Test status
Simulation time 394894957 ps
CPU time 3.49 seconds
Started Jul 24 05:22:44 PM PDT 24
Finished Jul 24 05:22:47 PM PDT 24
Peak memory 211092 kb
Host smart-1823f374-8eba-4dd1-aa7d-f793616ffc2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786554714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3786554714
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3606100991
Short name T136
Test name
Test status
Simulation time 589911445201 ps
CPU time 330.86 seconds
Started Jul 24 07:12:09 PM PDT 24
Finished Jul 24 07:17:40 PM PDT 24
Peak memory 201220 kb
Host smart-4648d48c-0e68-41c0-88cc-bf63dda559a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606100991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3606100991
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2409365222
Short name T214
Test name
Test status
Simulation time 536964988732 ps
CPU time 356.77 seconds
Started Jul 24 07:11:39 PM PDT 24
Finished Jul 24 07:17:36 PM PDT 24
Peak memory 201312 kb
Host smart-467e44ef-63e7-4463-bb52-777abedb7e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409365222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2409365222
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2318302551
Short name T9
Test name
Test status
Simulation time 645721159419 ps
CPU time 1475.24 seconds
Started Jul 24 07:11:58 PM PDT 24
Finished Jul 24 07:36:33 PM PDT 24
Peak memory 201236 kb
Host smart-d5afc6ae-511b-49da-9a52-2c192b68af75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318302551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2318302551
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3795093058
Short name T28
Test name
Test status
Simulation time 478188142840 ps
CPU time 327.09 seconds
Started Jul 24 07:12:27 PM PDT 24
Finished Jul 24 07:17:54 PM PDT 24
Peak memory 201332 kb
Host smart-4f278b8c-bd5b-4840-8187-39c0da7a9b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795093058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3795093058
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.884027848
Short name T227
Test name
Test status
Simulation time 542137233420 ps
CPU time 626.96 seconds
Started Jul 24 07:10:07 PM PDT 24
Finished Jul 24 07:20:34 PM PDT 24
Peak memory 201316 kb
Host smart-096b4c2a-b95b-40d2-83b2-2d7c4f0a2ccc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884027848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.884027848
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1565447522
Short name T161
Test name
Test status
Simulation time 557198258 ps
CPU time 0.91 seconds
Started Jul 24 07:10:53 PM PDT 24
Finished Jul 24 07:10:54 PM PDT 24
Peak memory 201012 kb
Host smart-bf165d0b-0b81-476b-896e-d12bedf3f32c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565447522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1565447522
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.15744608
Short name T113
Test name
Test status
Simulation time 523060263 ps
CPU time 1.18 seconds
Started Jul 24 05:22:40 PM PDT 24
Finished Jul 24 05:22:41 PM PDT 24
Peak memory 201412 kb
Host smart-b4478d89-2b07-4422-9069-edeab807c590
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15744608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.15744608
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3155724938
Short name T147
Test name
Test status
Simulation time 441791870700 ps
CPU time 123.82 seconds
Started Jul 24 07:10:47 PM PDT 24
Finished Jul 24 07:12:51 PM PDT 24
Peak memory 201272 kb
Host smart-b2504f07-497b-4714-95ee-4825cbfa8bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155724938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3155724938
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1525183090
Short name T62
Test name
Test status
Simulation time 8870647444 ps
CPU time 3.71 seconds
Started Jul 24 07:10:06 PM PDT 24
Finished Jul 24 07:10:10 PM PDT 24
Peak memory 218048 kb
Host smart-a5f37505-e5c3-4a1e-9ff6-741d0d5f01fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525183090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1525183090
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1296535784
Short name T171
Test name
Test status
Simulation time 383058582898 ps
CPU time 886.49 seconds
Started Jul 24 07:10:35 PM PDT 24
Finished Jul 24 07:25:21 PM PDT 24
Peak memory 201304 kb
Host smart-db71a8dd-fdea-4087-a0fc-5a265ae408a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296535784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1296535784
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1054836087
Short name T271
Test name
Test status
Simulation time 493633242797 ps
CPU time 575.33 seconds
Started Jul 24 07:14:43 PM PDT 24
Finished Jul 24 07:24:18 PM PDT 24
Peak memory 201256 kb
Host smart-952dafba-4aa7-4dde-8856-577435a209f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054836087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1054836087
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2565598643
Short name T232
Test name
Test status
Simulation time 414293230742 ps
CPU time 442.44 seconds
Started Jul 24 07:09:59 PM PDT 24
Finished Jul 24 07:17:22 PM PDT 24
Peak memory 210012 kb
Host smart-a5ff8c9a-8672-40f0-b1ef-72d22a5a0887
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565598643 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2565598643
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.565766890
Short name T207
Test name
Test status
Simulation time 665640824893 ps
CPU time 794.74 seconds
Started Jul 24 07:16:14 PM PDT 24
Finished Jul 24 07:29:29 PM PDT 24
Peak memory 201632 kb
Host smart-c9b9809b-ed18-4dbb-a52a-0cea0f6b0189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565766890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
565766890
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3908576673
Short name T199
Test name
Test status
Simulation time 325029485908 ps
CPU time 232.19 seconds
Started Jul 24 07:10:24 PM PDT 24
Finished Jul 24 07:14:16 PM PDT 24
Peak memory 201248 kb
Host smart-881701fe-17ff-421f-98e4-5ce80aaa4e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908576673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3908576673
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1348866171
Short name T36
Test name
Test status
Simulation time 86003306770 ps
CPU time 64.32 seconds
Started Jul 24 07:13:00 PM PDT 24
Finished Jul 24 07:14:04 PM PDT 24
Peak memory 210060 kb
Host smart-068ce743-fdda-4c05-ad77-05d187b0e1c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348866171 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1348866171
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1297158136
Short name T269
Test name
Test status
Simulation time 372986084210 ps
CPU time 622.7 seconds
Started Jul 24 07:10:39 PM PDT 24
Finished Jul 24 07:21:02 PM PDT 24
Peak memory 201260 kb
Host smart-15c26d6b-9c7d-4d4f-9dbc-c3549981eba1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297158136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1297158136
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1927661008
Short name T37
Test name
Test status
Simulation time 68556019741 ps
CPU time 160.14 seconds
Started Jul 24 07:14:42 PM PDT 24
Finished Jul 24 07:17:22 PM PDT 24
Peak memory 210096 kb
Host smart-ffc8c068-b8f6-44c8-a98c-ed9205a60f06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927661008 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1927661008
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2357660445
Short name T42
Test name
Test status
Simulation time 399526352871 ps
CPU time 461.7 seconds
Started Jul 24 07:10:22 PM PDT 24
Finished Jul 24 07:18:03 PM PDT 24
Peak memory 201216 kb
Host smart-71c7507c-ea27-44cb-bf89-8bded2362596
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357660445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2357660445
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1488382627
Short name T200
Test name
Test status
Simulation time 632931289338 ps
CPU time 670.78 seconds
Started Jul 24 07:10:02 PM PDT 24
Finished Jul 24 07:21:13 PM PDT 24
Peak memory 201676 kb
Host smart-cc44a0b7-2105-42e2-b6cf-0a43af638503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488382627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1488382627
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3343839047
Short name T340
Test name
Test status
Simulation time 8500438622 ps
CPU time 7.27 seconds
Started Jul 24 05:22:29 PM PDT 24
Finished Jul 24 05:22:36 PM PDT 24
Peak memory 201824 kb
Host smart-08150949-50eb-454f-ba3a-d5adcaa876a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343839047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3343839047
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.466348564
Short name T213
Test name
Test status
Simulation time 325198495850 ps
CPU time 763.36 seconds
Started Jul 24 07:11:06 PM PDT 24
Finished Jul 24 07:23:50 PM PDT 24
Peak memory 201256 kb
Host smart-fe31fd8c-38a9-4991-a338-c0b1ebaf886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466348564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.466348564
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.9632264
Short name T226
Test name
Test status
Simulation time 324632573016 ps
CPU time 791.71 seconds
Started Jul 24 07:15:13 PM PDT 24
Finished Jul 24 07:28:25 PM PDT 24
Peak memory 201156 kb
Host smart-552481ef-000e-4fa6-bc1a-d6cc936dc3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9632264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.9632264
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2958007835
Short name T324
Test name
Test status
Simulation time 187586997251 ps
CPU time 291.82 seconds
Started Jul 24 07:13:38 PM PDT 24
Finished Jul 24 07:18:30 PM PDT 24
Peak memory 201240 kb
Host smart-24fc817d-5a2e-40df-8b77-4b1a098c686f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958007835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2958007835
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2624804662
Short name T264
Test name
Test status
Simulation time 525431180510 ps
CPU time 1117.23 seconds
Started Jul 24 07:13:37 PM PDT 24
Finished Jul 24 07:32:15 PM PDT 24
Peak memory 201236 kb
Host smart-a8c86ce1-7d47-4f67-815a-a791bb85fd8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624804662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2624804662
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1213034855
Short name T219
Test name
Test status
Simulation time 360940300298 ps
CPU time 203.14 seconds
Started Jul 24 07:15:59 PM PDT 24
Finished Jul 24 07:19:23 PM PDT 24
Peak memory 201248 kb
Host smart-bb876c66-f5c9-4f70-92b1-c56eea9bb1c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213034855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1213034855
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1173771701
Short name T95
Test name
Test status
Simulation time 496811853350 ps
CPU time 1162.13 seconds
Started Jul 24 07:16:07 PM PDT 24
Finished Jul 24 07:35:29 PM PDT 24
Peak memory 201300 kb
Host smart-29fd54d8-73a3-474d-aa56-348324c41d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173771701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1173771701
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2635771489
Short name T299
Test name
Test status
Simulation time 501727837372 ps
CPU time 279.63 seconds
Started Jul 24 07:10:37 PM PDT 24
Finished Jul 24 07:15:17 PM PDT 24
Peak memory 201280 kb
Host smart-5debfb75-b876-4620-a6d0-c74fe6878bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635771489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2635771489
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1454327456
Short name T96
Test name
Test status
Simulation time 382855279391 ps
CPU time 336.2 seconds
Started Jul 24 07:16:27 PM PDT 24
Finished Jul 24 07:22:03 PM PDT 24
Peak memory 201316 kb
Host smart-62413ad7-be22-440a-a010-c513d3623627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454327456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1454327456
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.3948871014
Short name T222
Test name
Test status
Simulation time 330752950394 ps
CPU time 216.14 seconds
Started Jul 24 07:10:33 PM PDT 24
Finished Jul 24 07:14:10 PM PDT 24
Peak memory 201212 kb
Host smart-bafee720-7f25-48b8-af9e-8219fc0e23eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948871014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.3948871014
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3989572150
Short name T51
Test name
Test status
Simulation time 4881084938 ps
CPU time 3.39 seconds
Started Jul 24 05:22:44 PM PDT 24
Finished Jul 24 05:22:47 PM PDT 24
Peak memory 201804 kb
Host smart-f379db7e-5900-4c96-880c-692209b384c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989572150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3989572150
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.549685544
Short name T295
Test name
Test status
Simulation time 548488200276 ps
CPU time 1218.13 seconds
Started Jul 24 07:10:05 PM PDT 24
Finished Jul 24 07:30:23 PM PDT 24
Peak memory 201220 kb
Host smart-a06261b0-52e1-4d25-94a3-439c22017575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549685544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.549685544
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.973787290
Short name T290
Test name
Test status
Simulation time 491754953914 ps
CPU time 757.21 seconds
Started Jul 24 07:11:03 PM PDT 24
Finished Jul 24 07:23:40 PM PDT 24
Peak memory 201356 kb
Host smart-4492e31e-00b4-4417-a242-7a2a358284c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973787290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.973787290
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1288492848
Short name T241
Test name
Test status
Simulation time 493337160292 ps
CPU time 520.6 seconds
Started Jul 24 07:13:55 PM PDT 24
Finished Jul 24 07:22:36 PM PDT 24
Peak memory 201124 kb
Host smart-7310f300-4c64-4bf6-b348-cf0f17a5d149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288492848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1288492848
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3302798046
Short name T41
Test name
Test status
Simulation time 299731367956 ps
CPU time 306.27 seconds
Started Jul 24 07:10:22 PM PDT 24
Finished Jul 24 07:15:28 PM PDT 24
Peak memory 210104 kb
Host smart-557452b1-a42c-4813-8d3f-f09a17deb186
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302798046 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3302798046
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1462786208
Short name T135
Test name
Test status
Simulation time 321669976281 ps
CPU time 183.58 seconds
Started Jul 24 07:11:56 PM PDT 24
Finished Jul 24 07:15:00 PM PDT 24
Peak memory 201312 kb
Host smart-afdd4ca7-abe4-4980-bcc4-ccbc327a7980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462786208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1462786208
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2226358885
Short name T166
Test name
Test status
Simulation time 487917349110 ps
CPU time 302.14 seconds
Started Jul 24 07:12:50 PM PDT 24
Finished Jul 24 07:17:52 PM PDT 24
Peak memory 201228 kb
Host smart-1c9b77e2-4dad-48c3-ad2c-71e3ebbaa4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226358885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2226358885
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3488747893
Short name T30
Test name
Test status
Simulation time 1981612150692 ps
CPU time 898.22 seconds
Started Jul 24 07:15:19 PM PDT 24
Finished Jul 24 07:30:18 PM PDT 24
Peak memory 209896 kb
Host smart-59849f7f-5fd3-4e83-a5bb-160cb946ffda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488747893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3488747893
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1241004774
Short name T321
Test name
Test status
Simulation time 414102723961 ps
CPU time 126.75 seconds
Started Jul 24 07:15:32 PM PDT 24
Finished Jul 24 07:17:39 PM PDT 24
Peak memory 201308 kb
Host smart-8eb4729e-3e8f-4780-a19a-ca3e031db700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241004774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1241004774
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2661116973
Short name T283
Test name
Test status
Simulation time 338161297136 ps
CPU time 373.64 seconds
Started Jul 24 07:15:20 PM PDT 24
Finished Jul 24 07:21:34 PM PDT 24
Peak memory 201276 kb
Host smart-e5211f32-916f-4976-a48b-860f35b67a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661116973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2661116973
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3432874377
Short name T292
Test name
Test status
Simulation time 339931230460 ps
CPU time 278.37 seconds
Started Jul 24 07:10:47 PM PDT 24
Finished Jul 24 07:15:25 PM PDT 24
Peak memory 201296 kb
Host smart-d0a776bb-24ca-4f82-a3e3-15929fd3fce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432874377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3432874377
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.622925105
Short name T104
Test name
Test status
Simulation time 339868819934 ps
CPU time 271.73 seconds
Started Jul 24 07:11:00 PM PDT 24
Finished Jul 24 07:15:32 PM PDT 24
Peak memory 201236 kb
Host smart-3bff949e-dabf-4888-8b8a-935da7c8e1c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622925105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gati
ng.622925105
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.2601530124
Short name T288
Test name
Test status
Simulation time 171465106009 ps
CPU time 198.94 seconds
Started Jul 24 07:14:17 PM PDT 24
Finished Jul 24 07:17:36 PM PDT 24
Peak memory 201160 kb
Host smart-fecddeaf-4a73-44fd-adcf-e3d6ce91bf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601530124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2601530124
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3514204891
Short name T296
Test name
Test status
Simulation time 369756433249 ps
CPU time 903.77 seconds
Started Jul 24 07:10:37 PM PDT 24
Finished Jul 24 07:25:41 PM PDT 24
Peak memory 201204 kb
Host smart-efdf69a3-e9d1-4e8c-aafd-12ca3a7a32f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514204891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3514204891
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2075154644
Short name T272
Test name
Test status
Simulation time 190183335026 ps
CPU time 428.24 seconds
Started Jul 24 07:11:44 PM PDT 24
Finished Jul 24 07:18:53 PM PDT 24
Peak memory 201244 kb
Host smart-9f949697-b2c1-4d94-8726-6af5982c2436
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075154644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2075154644
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.4089076435
Short name T259
Test name
Test status
Simulation time 168947849435 ps
CPU time 106.53 seconds
Started Jul 24 07:16:07 PM PDT 24
Finished Jul 24 07:17:54 PM PDT 24
Peak memory 201248 kb
Host smart-4e675400-8233-4dd3-b5fd-c2211cd95bcc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089076435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.4089076435
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2275355447
Short name T146
Test name
Test status
Simulation time 374201523771 ps
CPU time 50.09 seconds
Started Jul 24 07:10:22 PM PDT 24
Finished Jul 24 07:11:13 PM PDT 24
Peak memory 201236 kb
Host smart-e756f90a-438d-485b-93a8-bdb17a3ac3a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275355447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2275355447
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1221318077
Short name T142
Test name
Test status
Simulation time 491637849747 ps
CPU time 69.17 seconds
Started Jul 24 07:10:27 PM PDT 24
Finished Jul 24 07:11:36 PM PDT 24
Peak memory 201252 kb
Host smart-76a07381-72ce-4517-95f2-7ac4a5fd8303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221318077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1221318077
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.4035845455
Short name T325
Test name
Test status
Simulation time 497034615113 ps
CPU time 1169.6 seconds
Started Jul 24 07:15:52 PM PDT 24
Finished Jul 24 07:35:22 PM PDT 24
Peak memory 201232 kb
Host smart-29463486-57d0-4781-b87a-cbb1da9fbd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035845455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.4035845455
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1773668497
Short name T833
Test name
Test status
Simulation time 528772110 ps
CPU time 3.03 seconds
Started Jul 24 05:22:36 PM PDT 24
Finished Jul 24 05:22:40 PM PDT 24
Peak memory 210032 kb
Host smart-aa89e840-be64-4e47-a267-e382fa72caed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773668497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1773668497
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3100596072
Short name T282
Test name
Test status
Simulation time 494903033954 ps
CPU time 551.42 seconds
Started Jul 24 07:10:36 PM PDT 24
Finished Jul 24 07:19:47 PM PDT 24
Peak memory 201184 kb
Host smart-beaa9dbe-762b-4dc6-98f7-82c3878d2d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100596072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3100596072
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.164084093
Short name T252
Test name
Test status
Simulation time 516441728382 ps
CPU time 326.41 seconds
Started Jul 24 07:11:46 PM PDT 24
Finished Jul 24 07:17:12 PM PDT 24
Peak memory 201296 kb
Host smart-ec2633ea-c181-45d3-90fc-2c8be4701013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164084093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.164084093
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1925318405
Short name T99
Test name
Test status
Simulation time 521652659660 ps
CPU time 329.74 seconds
Started Jul 24 07:13:15 PM PDT 24
Finished Jul 24 07:18:45 PM PDT 24
Peak memory 201196 kb
Host smart-d520648c-989a-40c1-98af-0e4701f94220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925318405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1925318405
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2961433272
Short name T44
Test name
Test status
Simulation time 107140930536 ps
CPU time 390.98 seconds
Started Jul 24 07:13:52 PM PDT 24
Finished Jul 24 07:20:23 PM PDT 24
Peak memory 201672 kb
Host smart-72b1f876-194d-40f1-98ac-f197fc58e607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961433272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2961433272
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3461082149
Short name T194
Test name
Test status
Simulation time 142906754105 ps
CPU time 729.38 seconds
Started Jul 24 07:10:38 PM PDT 24
Finished Jul 24 07:22:48 PM PDT 24
Peak memory 201644 kb
Host smart-1b586725-8894-443f-af7d-9365215b89b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461082149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3461082149
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.125422237
Short name T12
Test name
Test status
Simulation time 371429131820 ps
CPU time 794.32 seconds
Started Jul 24 07:11:06 PM PDT 24
Finished Jul 24 07:24:21 PM PDT 24
Peak memory 201296 kb
Host smart-6b8ff1b5-1972-486d-9c99-d98046317823
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125422237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.125422237
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1758083640
Short name T257
Test name
Test status
Simulation time 360541020137 ps
CPU time 444.75 seconds
Started Jul 24 07:11:26 PM PDT 24
Finished Jul 24 07:18:51 PM PDT 24
Peak memory 201228 kb
Host smart-146da9d7-d0e4-43c5-aa4e-773db46f5079
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758083640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1758083640
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3811457622
Short name T242
Test name
Test status
Simulation time 161854233914 ps
CPU time 92.37 seconds
Started Jul 24 07:13:26 PM PDT 24
Finished Jul 24 07:14:58 PM PDT 24
Peak memory 201252 kb
Host smart-158842ec-47dd-4f7e-9b28-e61ee22fa058
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811457622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3811457622
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2628733057
Short name T206
Test name
Test status
Simulation time 334413707395 ps
CPU time 676.2 seconds
Started Jul 24 07:13:21 PM PDT 24
Finished Jul 24 07:24:37 PM PDT 24
Peak memory 201280 kb
Host smart-239eaa6f-7bfa-48aa-af2b-acce25f6a357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628733057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2628733057
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1305772097
Short name T156
Test name
Test status
Simulation time 545343093860 ps
CPU time 198.16 seconds
Started Jul 24 07:14:05 PM PDT 24
Finished Jul 24 07:17:23 PM PDT 24
Peak memory 201228 kb
Host smart-59a0323a-4650-4fd7-9886-44c5c794b06d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305772097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1305772097
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1823584650
Short name T346
Test name
Test status
Simulation time 97126569474 ps
CPU time 314.13 seconds
Started Jul 24 07:15:47 PM PDT 24
Finished Jul 24 07:21:01 PM PDT 24
Peak memory 201640 kb
Host smart-8e7ed4a6-8a37-4bf5-b4e7-70b77e09bdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823584650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1823584650
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1904328078
Short name T266
Test name
Test status
Simulation time 173958051386 ps
CPU time 15.21 seconds
Started Jul 24 07:10:19 PM PDT 24
Finished Jul 24 07:10:34 PM PDT 24
Peak memory 201236 kb
Host smart-2999bfcc-20cd-414f-9ddd-006294d12c54
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904328078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1904328078
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2908105663
Short name T192
Test name
Test status
Simulation time 87778189430 ps
CPU time 283.74 seconds
Started Jul 24 07:10:20 PM PDT 24
Finished Jul 24 07:15:04 PM PDT 24
Peak memory 201724 kb
Host smart-67e3ab6d-863c-47ec-b445-9beb54fddeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908105663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2908105663
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1659576513
Short name T915
Test name
Test status
Simulation time 4998200700 ps
CPU time 4.66 seconds
Started Jul 24 05:22:43 PM PDT 24
Finished Jul 24 05:22:48 PM PDT 24
Peak memory 201832 kb
Host smart-29091545-b837-49cb-b587-63f820e9f3df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659576513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1659576513
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.5572411
Short name T210
Test name
Test status
Simulation time 334885234282 ps
CPU time 759.8 seconds
Started Jul 24 07:10:01 PM PDT 24
Finished Jul 24 07:22:41 PM PDT 24
Peak memory 201276 kb
Host smart-7f760b5c-50c5-407e-bb43-95085babf6ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5572411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gat
ing_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gating.5572411
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1912960076
Short name T233
Test name
Test status
Simulation time 497999393893 ps
CPU time 1133.18 seconds
Started Jul 24 07:10:11 PM PDT 24
Finished Jul 24 07:29:04 PM PDT 24
Peak memory 201256 kb
Host smart-7bfd5424-769d-4afa-9381-ba123607e056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912960076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1912960076
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.228157017
Short name T319
Test name
Test status
Simulation time 527461549085 ps
CPU time 1165.15 seconds
Started Jul 24 07:10:20 PM PDT 24
Finished Jul 24 07:29:45 PM PDT 24
Peak memory 201240 kb
Host smart-d7e611fb-7de4-4e7b-b542-7e27206a5703
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228157017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.228157017
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1967320271
Short name T312
Test name
Test status
Simulation time 195832486722 ps
CPU time 107.86 seconds
Started Jul 24 07:10:36 PM PDT 24
Finished Jul 24 07:12:24 PM PDT 24
Peak memory 201188 kb
Host smart-45c88bca-95e3-4564-afd9-4893575b6d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967320271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1967320271
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3915727746
Short name T239
Test name
Test status
Simulation time 373594927300 ps
CPU time 201.88 seconds
Started Jul 24 07:10:44 PM PDT 24
Finished Jul 24 07:14:06 PM PDT 24
Peak memory 201240 kb
Host smart-7d895e89-6469-44ec-80e7-52c72bb90b9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915727746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3915727746
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3093528469
Short name T258
Test name
Test status
Simulation time 540874876652 ps
CPU time 663.56 seconds
Started Jul 24 07:11:44 PM PDT 24
Finished Jul 24 07:22:48 PM PDT 24
Peak memory 201164 kb
Host smart-6990d8a4-d993-49ed-93d1-4ac97b4de10c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093528469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3093528469
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1469288460
Short name T655
Test name
Test status
Simulation time 338999701016 ps
CPU time 206.12 seconds
Started Jul 24 07:10:10 PM PDT 24
Finished Jul 24 07:13:37 PM PDT 24
Peak memory 201280 kb
Host smart-341b1866-9485-4ba9-a806-1402c58f1c85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469288460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1469288460
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3919544209
Short name T217
Test name
Test status
Simulation time 496887022489 ps
CPU time 562.9 seconds
Started Jul 24 07:12:32 PM PDT 24
Finished Jul 24 07:21:55 PM PDT 24
Peak memory 201292 kb
Host smart-548971f3-7955-4017-8e1b-dfe034886952
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919544209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3919544209
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3225097875
Short name T334
Test name
Test status
Simulation time 166538791766 ps
CPU time 97.44 seconds
Started Jul 24 07:12:54 PM PDT 24
Finished Jul 24 07:14:32 PM PDT 24
Peak memory 201100 kb
Host smart-fdba2148-ad1f-44ef-bc5a-e46a51551cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225097875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3225097875
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2493942906
Short name T193
Test name
Test status
Simulation time 117151575211 ps
CPU time 617.56 seconds
Started Jul 24 07:13:20 PM PDT 24
Finished Jul 24 07:23:38 PM PDT 24
Peak memory 201764 kb
Host smart-69836c18-8a0b-4bd2-9055-de4b77fae4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493942906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2493942906
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3270704751
Short name T218
Test name
Test status
Simulation time 224810362714 ps
CPU time 69.9 seconds
Started Jul 24 07:14:43 PM PDT 24
Finished Jul 24 07:15:53 PM PDT 24
Peak memory 201244 kb
Host smart-25e7df4d-9edc-457e-b2df-2497596b3250
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270704751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3270704751
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3626656795
Short name T235
Test name
Test status
Simulation time 504511288466 ps
CPU time 405.17 seconds
Started Jul 24 07:10:18 PM PDT 24
Finished Jul 24 07:17:03 PM PDT 24
Peak memory 201200 kb
Host smart-c0ffeaa5-5b59-43be-9ceb-8facfc142200
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626656795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3626656795
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3089588802
Short name T260
Test name
Test status
Simulation time 452731446987 ps
CPU time 802.63 seconds
Started Jul 24 07:10:18 PM PDT 24
Finished Jul 24 07:23:41 PM PDT 24
Peak memory 201192 kb
Host smart-37861f7e-5068-4c51-be1f-fb53686daf23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089588802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3089588802
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1890842616
Short name T347
Test name
Test status
Simulation time 123305667179 ps
CPU time 493.96 seconds
Started Jul 24 07:10:29 PM PDT 24
Finished Jul 24 07:18:43 PM PDT 24
Peak memory 201688 kb
Host smart-31eccb44-50c9-4d88-849c-8d0cb49ab609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890842616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1890842616
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3474438337
Short name T843
Test name
Test status
Simulation time 850616154 ps
CPU time 2.51 seconds
Started Jul 24 05:22:26 PM PDT 24
Finished Jul 24 05:22:29 PM PDT 24
Peak memory 201736 kb
Host smart-b7975ca7-76d0-4e03-b267-d5efa68d6899
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474438337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3474438337
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3281838794
Short name T890
Test name
Test status
Simulation time 52778056233 ps
CPU time 62 seconds
Started Jul 24 05:22:26 PM PDT 24
Finished Jul 24 05:23:28 PM PDT 24
Peak memory 201724 kb
Host smart-0c20f019-0f07-4d5b-b705-e9cd1f0ac491
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281838794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3281838794
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.804424939
Short name T118
Test name
Test status
Simulation time 1107181614 ps
CPU time 1.42 seconds
Started Jul 24 05:22:24 PM PDT 24
Finished Jul 24 05:22:25 PM PDT 24
Peak memory 201500 kb
Host smart-017585bd-6f64-4ae4-9913-e831e4ecd813
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804424939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.804424939
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2416711178
Short name T893
Test name
Test status
Simulation time 459623081 ps
CPU time 1.79 seconds
Started Jul 24 05:22:26 PM PDT 24
Finished Jul 24 05:22:28 PM PDT 24
Peak memory 201576 kb
Host smart-46b27b49-46a5-40e0-b18b-83671e5832a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416711178 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2416711178
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1070424333
Short name T853
Test name
Test status
Simulation time 446787800 ps
CPU time 0.98 seconds
Started Jul 24 05:22:31 PM PDT 24
Finished Jul 24 05:22:32 PM PDT 24
Peak memory 201416 kb
Host smart-89a67422-a5ff-47ce-b86e-a71e8fd92600
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070424333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1070424333
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2075800045
Short name T810
Test name
Test status
Simulation time 498161715 ps
CPU time 1.34 seconds
Started Jul 24 05:22:25 PM PDT 24
Finished Jul 24 05:22:26 PM PDT 24
Peak memory 201376 kb
Host smart-ed2e3eec-340e-44d2-a0fd-a439ae572fef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075800045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2075800045
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.509566270
Short name T804
Test name
Test status
Simulation time 5337746453 ps
CPU time 9.35 seconds
Started Jul 24 05:22:26 PM PDT 24
Finished Jul 24 05:22:36 PM PDT 24
Peak memory 201744 kb
Host smart-f19e96f9-a330-4caa-a61b-f1a7b9268686
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509566270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.509566270
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1270736052
Short name T852
Test name
Test status
Simulation time 691456730 ps
CPU time 1.87 seconds
Started Jul 24 05:22:28 PM PDT 24
Finished Jul 24 05:22:30 PM PDT 24
Peak memory 201792 kb
Host smart-e020bf80-ff72-41e7-953f-6349233827ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270736052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1270736052
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3457681373
Short name T341
Test name
Test status
Simulation time 8724324954 ps
CPU time 20.6 seconds
Started Jul 24 05:22:28 PM PDT 24
Finished Jul 24 05:22:49 PM PDT 24
Peak memory 201776 kb
Host smart-4e23fc2c-3c33-43f3-aefd-736cc10e07df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457681373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3457681373
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4219783147
Short name T129
Test name
Test status
Simulation time 769918301 ps
CPU time 3.12 seconds
Started Jul 24 05:22:25 PM PDT 24
Finished Jul 24 05:22:28 PM PDT 24
Peak memory 201696 kb
Host smart-1dccace3-5b42-4928-b0a4-22f91530a2eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219783147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.4219783147
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1063442903
Short name T117
Test name
Test status
Simulation time 14439737916 ps
CPU time 11.88 seconds
Started Jul 24 05:22:27 PM PDT 24
Finished Jul 24 05:22:39 PM PDT 24
Peak memory 201720 kb
Host smart-dd635b55-a2ff-4b66-a34a-565d1f1bde3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063442903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1063442903
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4209178020
Short name T111
Test name
Test status
Simulation time 1142412997 ps
CPU time 1.41 seconds
Started Jul 24 05:22:30 PM PDT 24
Finished Jul 24 05:22:31 PM PDT 24
Peak memory 201404 kb
Host smart-7ec59b19-c301-471e-858a-a6757f027757
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209178020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.4209178020
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3315449297
Short name T871
Test name
Test status
Simulation time 452126058 ps
CPU time 1.22 seconds
Started Jul 24 05:22:27 PM PDT 24
Finished Jul 24 05:22:28 PM PDT 24
Peak memory 201528 kb
Host smart-0ffa49eb-884b-48d4-9818-f7dd09a8df2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315449297 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3315449297
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1619441294
Short name T897
Test name
Test status
Simulation time 458305928 ps
CPU time 1.33 seconds
Started Jul 24 05:22:29 PM PDT 24
Finished Jul 24 05:22:31 PM PDT 24
Peak memory 201480 kb
Host smart-4e0e4d25-1b59-412b-8176-8d1b0f3c5f8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619441294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1619441294
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1520106172
Short name T887
Test name
Test status
Simulation time 544190881 ps
CPU time 0.84 seconds
Started Jul 24 05:22:31 PM PDT 24
Finished Jul 24 05:22:32 PM PDT 24
Peak memory 201412 kb
Host smart-f7ca6ddc-3b5b-40e7-b948-bfc86c094109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520106172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1520106172
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2339021981
Short name T126
Test name
Test status
Simulation time 2272009450 ps
CPU time 3.26 seconds
Started Jul 24 05:22:25 PM PDT 24
Finished Jul 24 05:22:28 PM PDT 24
Peak memory 201580 kb
Host smart-47142ad6-b436-43eb-ac65-46c925a7592b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339021981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2339021981
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1428726722
Short name T914
Test name
Test status
Simulation time 1753157463 ps
CPU time 2.76 seconds
Started Jul 24 05:22:26 PM PDT 24
Finished Jul 24 05:22:29 PM PDT 24
Peak memory 201804 kb
Host smart-53a8c5ff-fcd9-4c30-bb90-1bc7cd7abae0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428726722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1428726722
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.727746818
Short name T823
Test name
Test status
Simulation time 477339900 ps
CPU time 1.96 seconds
Started Jul 24 05:22:39 PM PDT 24
Finished Jul 24 05:22:41 PM PDT 24
Peak memory 201600 kb
Host smart-314ec415-27b6-49a9-ae77-b554a986306b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727746818 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.727746818
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.201003936
Short name T123
Test name
Test status
Simulation time 542770976 ps
CPU time 1.15 seconds
Started Jul 24 05:22:38 PM PDT 24
Finished Jul 24 05:22:39 PM PDT 24
Peak memory 201512 kb
Host smart-8bba909b-233a-41b7-a633-a0d3b32560b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201003936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.201003936
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3298728802
Short name T795
Test name
Test status
Simulation time 422226147 ps
CPU time 1.59 seconds
Started Jul 24 05:22:48 PM PDT 24
Finished Jul 24 05:22:49 PM PDT 24
Peak memory 201452 kb
Host smart-a2427f00-b646-4894-8d14-7efed35d680c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298728802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3298728802
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3512428407
Short name T827
Test name
Test status
Simulation time 2075469635 ps
CPU time 2.52 seconds
Started Jul 24 05:22:37 PM PDT 24
Finished Jul 24 05:22:39 PM PDT 24
Peak memory 201560 kb
Host smart-18f98f9c-225b-4ef8-bb9f-7d089b0967bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512428407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3512428407
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3347846458
Short name T811
Test name
Test status
Simulation time 457866637 ps
CPU time 2.04 seconds
Started Jul 24 05:22:40 PM PDT 24
Finished Jul 24 05:22:42 PM PDT 24
Peak memory 201516 kb
Host smart-e12dbcf6-fb4a-4967-aa10-10be21649b1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347846458 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3347846458
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3661761476
Short name T802
Test name
Test status
Simulation time 473912680 ps
CPU time 1.63 seconds
Started Jul 24 05:22:38 PM PDT 24
Finished Jul 24 05:22:40 PM PDT 24
Peak memory 201504 kb
Host smart-e30280c6-0f2b-450b-8c07-b7a6c8d478be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661761476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3661761476
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.760865783
Short name T128
Test name
Test status
Simulation time 2112757889 ps
CPU time 3.23 seconds
Started Jul 24 05:22:44 PM PDT 24
Finished Jul 24 05:22:47 PM PDT 24
Peak memory 201568 kb
Host smart-db675338-b44a-48e3-bb63-5d618e98f787
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760865783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.760865783
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.417637354
Short name T838
Test name
Test status
Simulation time 556652664 ps
CPU time 2.18 seconds
Started Jul 24 05:22:43 PM PDT 24
Finished Jul 24 05:22:45 PM PDT 24
Peak memory 201784 kb
Host smart-e7918f57-12f4-4fd9-b5c3-e36c52ae01e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417637354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.417637354
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2596735096
Short name T56
Test name
Test status
Simulation time 8344822275 ps
CPU time 7.33 seconds
Started Jul 24 05:22:41 PM PDT 24
Finished Jul 24 05:22:48 PM PDT 24
Peak memory 201844 kb
Host smart-6e95747d-d09d-47f8-800e-934f4ee67e62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596735096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2596735096
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4234161382
Short name T862
Test name
Test status
Simulation time 401042608 ps
CPU time 1.03 seconds
Started Jul 24 05:22:45 PM PDT 24
Finished Jul 24 05:22:46 PM PDT 24
Peak memory 201564 kb
Host smart-8f283382-8f08-4ec8-bf50-6876abc9268b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234161382 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.4234161382
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.421494714
Short name T110
Test name
Test status
Simulation time 473995399 ps
CPU time 1.72 seconds
Started Jul 24 05:22:47 PM PDT 24
Finished Jul 24 05:22:49 PM PDT 24
Peak memory 201480 kb
Host smart-f46e32fa-e1b3-48e3-b95c-8e77e5770374
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421494714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.421494714
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3192638197
Short name T832
Test name
Test status
Simulation time 469639152 ps
CPU time 0.96 seconds
Started Jul 24 05:22:39 PM PDT 24
Finished Jul 24 05:22:40 PM PDT 24
Peak memory 201432 kb
Host smart-6c476a5d-a0dd-4a5a-8dd5-fb1c6902fcfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192638197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3192638197
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3263832419
Short name T888
Test name
Test status
Simulation time 2062768329 ps
CPU time 5.59 seconds
Started Jul 24 05:22:36 PM PDT 24
Finished Jul 24 05:22:42 PM PDT 24
Peak memory 201464 kb
Host smart-cb1640fb-32d1-4db0-bb21-e63a41c8312f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263832419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3263832419
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.583668627
Short name T63
Test name
Test status
Simulation time 994441495 ps
CPU time 2.53 seconds
Started Jul 24 05:22:35 PM PDT 24
Finished Jul 24 05:22:38 PM PDT 24
Peak memory 201844 kb
Host smart-39bfd04c-e334-41fb-a277-d85bb680177a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583668627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.583668627
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1784907657
Short name T904
Test name
Test status
Simulation time 8632077525 ps
CPU time 22.32 seconds
Started Jul 24 05:22:48 PM PDT 24
Finished Jul 24 05:23:10 PM PDT 24
Peak memory 201748 kb
Host smart-fe81591d-6aba-429a-ac99-4c28ef5dc7b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784907657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1784907657
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1005171395
Short name T854
Test name
Test status
Simulation time 799855474 ps
CPU time 1.74 seconds
Started Jul 24 05:22:44 PM PDT 24
Finished Jul 24 05:22:46 PM PDT 24
Peak memory 210060 kb
Host smart-82c66b42-0acb-4937-9d3e-96f220f5cb7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005171395 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1005171395
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3529543286
Short name T895
Test name
Test status
Simulation time 491815584 ps
CPU time 1.81 seconds
Started Jul 24 05:22:38 PM PDT 24
Finished Jul 24 05:22:40 PM PDT 24
Peak memory 201420 kb
Host smart-171a2a69-c2af-4ad3-8962-186b194eac97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529543286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3529543286
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4142173989
Short name T857
Test name
Test status
Simulation time 532491306 ps
CPU time 1.92 seconds
Started Jul 24 05:22:37 PM PDT 24
Finished Jul 24 05:22:39 PM PDT 24
Peak memory 201456 kb
Host smart-1aa11463-32e0-40d7-aed3-ad0c38326847
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142173989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.4142173989
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2112058075
Short name T912
Test name
Test status
Simulation time 4386629163 ps
CPU time 16.53 seconds
Started Jul 24 05:22:38 PM PDT 24
Finished Jul 24 05:22:55 PM PDT 24
Peak memory 201824 kb
Host smart-bcbf751d-5a57-4555-ab22-a59bdadb055c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112058075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2112058075
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3011854798
Short name T903
Test name
Test status
Simulation time 536078702 ps
CPU time 1.97 seconds
Started Jul 24 05:22:43 PM PDT 24
Finished Jul 24 05:22:45 PM PDT 24
Peak memory 218108 kb
Host smart-533c40d5-80a8-457d-826d-51fdd5797c44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011854798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3011854798
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1504814575
Short name T57
Test name
Test status
Simulation time 4198378816 ps
CPU time 10.38 seconds
Started Jul 24 05:22:42 PM PDT 24
Finished Jul 24 05:22:52 PM PDT 24
Peak memory 201832 kb
Host smart-9f909e10-1df3-4c1c-839b-a8445666735f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504814575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1504814575
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1594550357
Short name T917
Test name
Test status
Simulation time 522152929 ps
CPU time 1.1 seconds
Started Jul 24 05:22:47 PM PDT 24
Finished Jul 24 05:22:48 PM PDT 24
Peak memory 201624 kb
Host smart-59f5dfa5-43c8-437c-9ee9-b6d4e176d3ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594550357 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1594550357
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1091835493
Short name T881
Test name
Test status
Simulation time 350619607 ps
CPU time 1.61 seconds
Started Jul 24 05:22:46 PM PDT 24
Finished Jul 24 05:22:47 PM PDT 24
Peak memory 201472 kb
Host smart-101dc979-de90-4ec3-b16f-cc17034d9432
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091835493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1091835493
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3057558770
Short name T798
Test name
Test status
Simulation time 418010346 ps
CPU time 1.1 seconds
Started Jul 24 05:22:48 PM PDT 24
Finished Jul 24 05:22:49 PM PDT 24
Peak memory 201452 kb
Host smart-55ac6968-3fa8-480b-8f32-923f4a8746d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057558770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3057558770
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1711762859
Short name T913
Test name
Test status
Simulation time 324853932 ps
CPU time 2.87 seconds
Started Jul 24 05:22:44 PM PDT 24
Finished Jul 24 05:22:47 PM PDT 24
Peak memory 201808 kb
Host smart-e237add8-e6a6-4d9e-8f9c-125a5bf4f520
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711762859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1711762859
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2736028591
Short name T878
Test name
Test status
Simulation time 4831192251 ps
CPU time 11.72 seconds
Started Jul 24 05:22:43 PM PDT 24
Finished Jul 24 05:22:54 PM PDT 24
Peak memory 201800 kb
Host smart-6767a905-f099-46ef-85c4-7846c8dc901a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736028591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2736028591
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2903628336
Short name T90
Test name
Test status
Simulation time 407709960 ps
CPU time 1.32 seconds
Started Jul 24 05:22:47 PM PDT 24
Finished Jul 24 05:22:49 PM PDT 24
Peak memory 201524 kb
Host smart-03b1c4b7-1375-4d6f-8707-fcf60dece7e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903628336 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2903628336
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.618912503
Short name T52
Test name
Test status
Simulation time 332137723 ps
CPU time 1.17 seconds
Started Jul 24 05:22:49 PM PDT 24
Finished Jul 24 05:22:50 PM PDT 24
Peak memory 201512 kb
Host smart-4d861654-fe47-4084-849f-7d3e53eed06d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618912503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.618912503
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3540374224
Short name T796
Test name
Test status
Simulation time 418740115 ps
CPU time 1.64 seconds
Started Jul 24 05:22:48 PM PDT 24
Finished Jul 24 05:22:50 PM PDT 24
Peak memory 201520 kb
Host smart-f5c1caff-035f-4633-8fcf-28e77f20e9b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540374224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3540374224
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3556360907
Short name T910
Test name
Test status
Simulation time 2432430471 ps
CPU time 8.18 seconds
Started Jul 24 05:22:46 PM PDT 24
Finished Jul 24 05:22:55 PM PDT 24
Peak memory 201528 kb
Host smart-ae6c4211-d50a-4061-ae1d-90e1ae052039
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556360907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3556360907
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3229866154
Short name T902
Test name
Test status
Simulation time 520307303 ps
CPU time 2.63 seconds
Started Jul 24 05:22:44 PM PDT 24
Finished Jul 24 05:22:47 PM PDT 24
Peak memory 201888 kb
Host smart-91418fa6-cab2-4459-84ed-c99fdd1a3cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229866154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3229866154
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1385165560
Short name T342
Test name
Test status
Simulation time 4195359114 ps
CPU time 3.76 seconds
Started Jul 24 05:22:50 PM PDT 24
Finished Jul 24 05:22:53 PM PDT 24
Peak memory 201712 kb
Host smart-670b8be8-9f9f-4778-9305-69f19ec8ffd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385165560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1385165560
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3109519931
Short name T822
Test name
Test status
Simulation time 476175419 ps
CPU time 1.26 seconds
Started Jul 24 05:22:45 PM PDT 24
Finished Jul 24 05:22:46 PM PDT 24
Peak memory 201628 kb
Host smart-c40c5249-7e65-4ab3-83ef-7c8f9eaf015d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109519931 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3109519931
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.30356421
Short name T882
Test name
Test status
Simulation time 506621950 ps
CPU time 1.98 seconds
Started Jul 24 05:22:51 PM PDT 24
Finished Jul 24 05:22:54 PM PDT 24
Peak memory 201524 kb
Host smart-cede133a-35f8-443e-99f4-5c65cc1827cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30356421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.30356421
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3692244166
Short name T813
Test name
Test status
Simulation time 510543130 ps
CPU time 1.7 seconds
Started Jul 24 05:22:43 PM PDT 24
Finished Jul 24 05:22:45 PM PDT 24
Peak memory 201460 kb
Host smart-272cfdeb-a173-40b5-8682-bd4050e79c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692244166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3692244166
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3586018606
Short name T806
Test name
Test status
Simulation time 2923162905 ps
CPU time 5.9 seconds
Started Jul 24 05:22:50 PM PDT 24
Finished Jul 24 05:22:56 PM PDT 24
Peak memory 201568 kb
Host smart-c382c915-dfc3-4fcd-8433-10a84f2861aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586018606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3586018606
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.768827789
Short name T864
Test name
Test status
Simulation time 508992993 ps
CPU time 2.87 seconds
Started Jul 24 05:22:45 PM PDT 24
Finished Jul 24 05:22:48 PM PDT 24
Peak memory 211012 kb
Host smart-285b6703-9ae6-4a4d-8dbb-16ddd059b48d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768827789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.768827789
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.4189714871
Short name T842
Test name
Test status
Simulation time 4906023126 ps
CPU time 3.57 seconds
Started Jul 24 05:22:54 PM PDT 24
Finished Jul 24 05:22:58 PM PDT 24
Peak memory 201828 kb
Host smart-2a813130-4cb9-476e-85f4-690b3f2d4e1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189714871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.4189714871
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.4265442142
Short name T803
Test name
Test status
Simulation time 449684713 ps
CPU time 1.84 seconds
Started Jul 24 05:22:43 PM PDT 24
Finished Jul 24 05:22:45 PM PDT 24
Peak memory 201648 kb
Host smart-4e530d21-c025-4702-bc0c-ac58e5dd2d0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265442142 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.4265442142
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2904430771
Short name T119
Test name
Test status
Simulation time 457315892 ps
CPU time 1.06 seconds
Started Jul 24 05:22:44 PM PDT 24
Finished Jul 24 05:22:45 PM PDT 24
Peak memory 201452 kb
Host smart-03a82573-94dc-485c-8f3b-0b7ab4984892
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904430771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2904430771
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.712021405
Short name T835
Test name
Test status
Simulation time 445814854 ps
CPU time 1.69 seconds
Started Jul 24 05:22:48 PM PDT 24
Finished Jul 24 05:22:50 PM PDT 24
Peak memory 201520 kb
Host smart-75c5a93b-0832-438b-a4c0-fc0285312549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712021405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.712021405
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3229094668
Short name T870
Test name
Test status
Simulation time 4680822846 ps
CPU time 2.63 seconds
Started Jul 24 05:22:43 PM PDT 24
Finished Jul 24 05:22:45 PM PDT 24
Peak memory 201784 kb
Host smart-2e72d83a-35f3-4f75-9abf-2568156d0e44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229094668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3229094668
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1703030620
Short name T868
Test name
Test status
Simulation time 322097725 ps
CPU time 1.89 seconds
Started Jul 24 05:22:47 PM PDT 24
Finished Jul 24 05:22:49 PM PDT 24
Peak memory 201824 kb
Host smart-d25b4de1-cb65-4455-b47f-5e62e824c5b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703030620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1703030620
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3045482124
Short name T344
Test name
Test status
Simulation time 4429012965 ps
CPU time 11.17 seconds
Started Jul 24 05:22:49 PM PDT 24
Finished Jul 24 05:23:00 PM PDT 24
Peak memory 201904 kb
Host smart-21d71d98-4354-4d7b-bfc2-0b3db19c2463
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045482124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3045482124
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.902967877
Short name T875
Test name
Test status
Simulation time 427650815 ps
CPU time 1.26 seconds
Started Jul 24 05:22:47 PM PDT 24
Finished Jul 24 05:22:48 PM PDT 24
Peak memory 201620 kb
Host smart-5c252670-a5e1-4c40-8c03-00b34c9b1006
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902967877 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.902967877
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2748382670
Short name T114
Test name
Test status
Simulation time 365242173 ps
CPU time 1.02 seconds
Started Jul 24 05:22:49 PM PDT 24
Finished Jul 24 05:22:50 PM PDT 24
Peak memory 201508 kb
Host smart-de66a935-51ba-4e81-a132-c793139e4357
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748382670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2748382670
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2135155177
Short name T819
Test name
Test status
Simulation time 447142545 ps
CPU time 1.24 seconds
Started Jul 24 05:22:45 PM PDT 24
Finished Jul 24 05:22:47 PM PDT 24
Peak memory 201320 kb
Host smart-d99ead32-5fe7-4439-8e9a-1e993f1a6367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135155177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2135155177
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1326116394
Short name T891
Test name
Test status
Simulation time 4990632609 ps
CPU time 3.74 seconds
Started Jul 24 05:22:49 PM PDT 24
Finished Jul 24 05:22:53 PM PDT 24
Peak memory 201800 kb
Host smart-1248f20f-5033-4fa0-b895-aa142a57d89f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326116394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1326116394
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3449240087
Short name T909
Test name
Test status
Simulation time 4938821181 ps
CPU time 13.44 seconds
Started Jul 24 05:22:47 PM PDT 24
Finished Jul 24 05:23:01 PM PDT 24
Peak memory 201744 kb
Host smart-8cebd36c-4a82-4b52-89bc-18400abc77c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449240087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3449240087
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3957324656
Short name T851
Test name
Test status
Simulation time 564158476 ps
CPU time 2.08 seconds
Started Jul 24 05:23:02 PM PDT 24
Finished Jul 24 05:23:05 PM PDT 24
Peak memory 201548 kb
Host smart-5609482e-2894-4456-8f03-a75375c156d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957324656 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3957324656
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.454543890
Short name T127
Test name
Test status
Simulation time 499383852 ps
CPU time 1.76 seconds
Started Jul 24 05:22:59 PM PDT 24
Finished Jul 24 05:23:01 PM PDT 24
Peak memory 201404 kb
Host smart-2081d98a-d013-49b0-9cc8-c2eb2be731ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454543890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.454543890
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1875084271
Short name T797
Test name
Test status
Simulation time 508577205 ps
CPU time 0.92 seconds
Started Jul 24 05:22:46 PM PDT 24
Finished Jul 24 05:22:47 PM PDT 24
Peak memory 201492 kb
Host smart-e95cf1bd-61d3-496a-a23c-0eee72a9355c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875084271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1875084271
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3050770234
Short name T821
Test name
Test status
Simulation time 4730928267 ps
CPU time 15.44 seconds
Started Jul 24 05:22:58 PM PDT 24
Finished Jul 24 05:23:14 PM PDT 24
Peak memory 201804 kb
Host smart-0b927afa-40f7-4830-baad-cfe889fe366a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050770234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3050770234
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.935066525
Short name T911
Test name
Test status
Simulation time 503010822 ps
CPU time 2.02 seconds
Started Jul 24 05:22:48 PM PDT 24
Finished Jul 24 05:22:50 PM PDT 24
Peak memory 209996 kb
Host smart-dca2183a-1348-4b4d-9872-e45e6f215629
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935066525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.935066525
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.4270560045
Short name T55
Test name
Test status
Simulation time 8618410380 ps
CPU time 12.9 seconds
Started Jul 24 05:22:47 PM PDT 24
Finished Jul 24 05:23:00 PM PDT 24
Peak memory 201880 kb
Host smart-cab1576f-2768-4624-83ec-e5655426f4ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270560045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.4270560045
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1005378372
Short name T856
Test name
Test status
Simulation time 1133058799 ps
CPU time 2.58 seconds
Started Jul 24 05:22:28 PM PDT 24
Finished Jul 24 05:22:31 PM PDT 24
Peak memory 201628 kb
Host smart-df63322c-63d8-441d-8bd8-06ea74c22dbb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005378372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1005378372
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3874921775
Short name T115
Test name
Test status
Simulation time 1122834967 ps
CPU time 5.79 seconds
Started Jul 24 05:22:27 PM PDT 24
Finished Jul 24 05:22:33 PM PDT 24
Peak memory 201612 kb
Host smart-a6a38a7f-bb93-4822-8ae5-a1f43db1c245
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874921775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3874921775
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1182929948
Short name T858
Test name
Test status
Simulation time 1073273098 ps
CPU time 1.12 seconds
Started Jul 24 05:22:27 PM PDT 24
Finished Jul 24 05:22:29 PM PDT 24
Peak memory 201420 kb
Host smart-e1cf5538-c430-4dc9-b169-ebbd8d936779
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182929948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1182929948
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3433591374
Short name T916
Test name
Test status
Simulation time 559681624 ps
CPU time 1.64 seconds
Started Jul 24 05:22:29 PM PDT 24
Finished Jul 24 05:22:31 PM PDT 24
Peak memory 201604 kb
Host smart-e449168d-ca0a-4db3-a4f0-252b90573a98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433591374 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3433591374
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1012512356
Short name T125
Test name
Test status
Simulation time 431761056 ps
CPU time 1.82 seconds
Started Jul 24 05:22:30 PM PDT 24
Finished Jul 24 05:22:32 PM PDT 24
Peak memory 201524 kb
Host smart-604e169a-035b-4318-be57-b6b7e4b95786
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012512356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1012512356
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1071960265
Short name T799
Test name
Test status
Simulation time 423894810 ps
CPU time 0.92 seconds
Started Jul 24 05:22:30 PM PDT 24
Finished Jul 24 05:22:31 PM PDT 24
Peak memory 201520 kb
Host smart-3b2850cf-22f3-450b-9c20-4475c3d5cb60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071960265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1071960265
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.874645185
Short name T883
Test name
Test status
Simulation time 5154092133 ps
CPU time 4.1 seconds
Started Jul 24 05:22:28 PM PDT 24
Finished Jul 24 05:22:32 PM PDT 24
Peak memory 201768 kb
Host smart-e6a092aa-da2b-4fbe-9f86-bec6b04b4cde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874645185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.874645185
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1084045188
Short name T71
Test name
Test status
Simulation time 471627519 ps
CPU time 3 seconds
Started Jul 24 05:22:27 PM PDT 24
Finished Jul 24 05:22:30 PM PDT 24
Peak memory 210048 kb
Host smart-913e1e34-6ea7-4e0e-8ec4-89fb11b6a07e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084045188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1084045188
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3720134979
Short name T845
Test name
Test status
Simulation time 4082076303 ps
CPU time 7.88 seconds
Started Jul 24 05:22:30 PM PDT 24
Finished Jul 24 05:22:38 PM PDT 24
Peak memory 201796 kb
Host smart-b608edb5-d06a-4079-a536-f5131ce3cffe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720134979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3720134979
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1169927975
Short name T848
Test name
Test status
Simulation time 527458323 ps
CPU time 0.73 seconds
Started Jul 24 05:22:52 PM PDT 24
Finished Jul 24 05:22:53 PM PDT 24
Peak memory 201352 kb
Host smart-b8f34f0b-49ce-44f6-ba5d-761401a135b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169927975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1169927975
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3612137577
Short name T834
Test name
Test status
Simulation time 540208224 ps
CPU time 1.31 seconds
Started Jul 24 05:22:51 PM PDT 24
Finished Jul 24 05:22:52 PM PDT 24
Peak memory 201528 kb
Host smart-07639367-34e8-4cd7-93cf-1d020ab7f2ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612137577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3612137577
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2010777342
Short name T859
Test name
Test status
Simulation time 315740439 ps
CPU time 1.36 seconds
Started Jul 24 05:22:49 PM PDT 24
Finished Jul 24 05:22:50 PM PDT 24
Peak memory 201480 kb
Host smart-d9a88d34-f7ca-4373-bbf5-e80c2f8ffa9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010777342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2010777342
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3291557162
Short name T865
Test name
Test status
Simulation time 410248536 ps
CPU time 0.89 seconds
Started Jul 24 05:22:51 PM PDT 24
Finished Jul 24 05:22:52 PM PDT 24
Peak memory 201432 kb
Host smart-dcd20fbe-a306-4856-9799-6c0502973bed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291557162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3291557162
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1176589590
Short name T884
Test name
Test status
Simulation time 304429011 ps
CPU time 1.36 seconds
Started Jul 24 05:22:52 PM PDT 24
Finished Jul 24 05:22:54 PM PDT 24
Peak memory 201416 kb
Host smart-898a6ff8-207e-4f2e-b596-f29e33f3c35b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176589590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1176589590
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.154807707
Short name T880
Test name
Test status
Simulation time 454612236 ps
CPU time 0.82 seconds
Started Jul 24 05:22:52 PM PDT 24
Finished Jul 24 05:22:53 PM PDT 24
Peak memory 201492 kb
Host smart-fe8d7c31-78cb-43bf-96f2-47ed59230a4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154807707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.154807707
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2711053399
Short name T820
Test name
Test status
Simulation time 717168869 ps
CPU time 0.71 seconds
Started Jul 24 05:22:56 PM PDT 24
Finished Jul 24 05:22:56 PM PDT 24
Peak memory 201460 kb
Host smart-765ae0a6-7fc1-470c-89a4-1187baa774fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711053399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2711053399
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3484653445
Short name T801
Test name
Test status
Simulation time 446454568 ps
CPU time 0.93 seconds
Started Jul 24 05:22:51 PM PDT 24
Finished Jul 24 05:22:53 PM PDT 24
Peak memory 201492 kb
Host smart-48a6d414-9204-4099-93ef-19c0ce1b2298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484653445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3484653445
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.412467684
Short name T885
Test name
Test status
Simulation time 428530075 ps
CPU time 1.57 seconds
Started Jul 24 05:22:48 PM PDT 24
Finished Jul 24 05:22:50 PM PDT 24
Peak memory 201376 kb
Host smart-1bc89e1b-121c-4438-8bc7-313d6561ebd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412467684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.412467684
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3307226473
Short name T874
Test name
Test status
Simulation time 369719629 ps
CPU time 1.1 seconds
Started Jul 24 05:22:51 PM PDT 24
Finished Jul 24 05:22:53 PM PDT 24
Peak memory 201520 kb
Host smart-ddf6829d-93c9-4347-a400-76577202d8bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307226473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3307226473
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.2814099962
Short name T818
Test name
Test status
Simulation time 665425619 ps
CPU time 1.76 seconds
Started Jul 24 05:22:33 PM PDT 24
Finished Jul 24 05:22:35 PM PDT 24
Peak memory 201728 kb
Host smart-3c962415-c4f7-4fbf-9adf-53abd1152328
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814099962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.2814099962
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1268048229
Short name T816
Test name
Test status
Simulation time 52967046571 ps
CPU time 59.57 seconds
Started Jul 24 05:22:32 PM PDT 24
Finished Jul 24 05:23:32 PM PDT 24
Peak memory 201780 kb
Host smart-3a9f1aec-83b0-4731-9f05-c74f25190fa2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268048229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1268048229
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1863061073
Short name T808
Test name
Test status
Simulation time 1094194910 ps
CPU time 3.08 seconds
Started Jul 24 05:22:32 PM PDT 24
Finished Jul 24 05:22:35 PM PDT 24
Peak memory 201496 kb
Host smart-c70c67f9-af66-4e59-97a3-70ea4fb966db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863061073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1863061073
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1498497493
Short name T85
Test name
Test status
Simulation time 464597087 ps
CPU time 1.5 seconds
Started Jul 24 05:22:32 PM PDT 24
Finished Jul 24 05:22:34 PM PDT 24
Peak memory 201632 kb
Host smart-5f56b352-cdd7-48b2-bcc0-45552db6d579
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498497493 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1498497493
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1561810094
Short name T899
Test name
Test status
Simulation time 369398869 ps
CPU time 1.59 seconds
Started Jul 24 05:22:35 PM PDT 24
Finished Jul 24 05:22:37 PM PDT 24
Peak memory 201488 kb
Host smart-d5a34c33-3a81-4f41-84a3-5b166b2b4bea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561810094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1561810094
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2192370805
Short name T846
Test name
Test status
Simulation time 432865860 ps
CPU time 0.95 seconds
Started Jul 24 05:22:33 PM PDT 24
Finished Jul 24 05:22:35 PM PDT 24
Peak memory 201464 kb
Host smart-5e0fc673-854d-40bd-a2d2-86fa820c530f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192370805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2192370805
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2678633316
Short name T825
Test name
Test status
Simulation time 4558693618 ps
CPU time 6.41 seconds
Started Jul 24 05:22:36 PM PDT 24
Finished Jul 24 05:22:43 PM PDT 24
Peak memory 201756 kb
Host smart-d1edb345-a86a-45b4-bd8a-1343828eea73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678633316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2678633316
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4157504411
Short name T837
Test name
Test status
Simulation time 665964906 ps
CPU time 2.6 seconds
Started Jul 24 05:22:28 PM PDT 24
Finished Jul 24 05:22:31 PM PDT 24
Peak memory 218120 kb
Host smart-b017e920-e988-4103-aa0e-201662ca8be6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157504411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.4157504411
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1825790297
Short name T805
Test name
Test status
Simulation time 4211630814 ps
CPU time 11.54 seconds
Started Jul 24 05:22:32 PM PDT 24
Finished Jul 24 05:22:44 PM PDT 24
Peak memory 201764 kb
Host smart-9dbf52af-8b20-4bcb-b833-04ada0246099
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825790297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1825790297
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.155070334
Short name T794
Test name
Test status
Simulation time 380216784 ps
CPU time 0.76 seconds
Started Jul 24 05:22:53 PM PDT 24
Finished Jul 24 05:22:54 PM PDT 24
Peak memory 201408 kb
Host smart-cb64c191-7fd1-400f-a256-26ae43e21e30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155070334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.155070334
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1896640839
Short name T869
Test name
Test status
Simulation time 527155341 ps
CPU time 0.94 seconds
Started Jul 24 05:22:58 PM PDT 24
Finished Jul 24 05:22:59 PM PDT 24
Peak memory 201472 kb
Host smart-e7bfd3f5-4d97-4c25-92aa-2cec94dc6575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896640839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1896640839
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1314448419
Short name T907
Test name
Test status
Simulation time 418955816 ps
CPU time 0.85 seconds
Started Jul 24 05:22:51 PM PDT 24
Finished Jul 24 05:22:52 PM PDT 24
Peak memory 201428 kb
Host smart-1a61e553-fa53-4aa9-8314-2da8d6cbad6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314448419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1314448419
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.4243956029
Short name T831
Test name
Test status
Simulation time 290008871 ps
CPU time 1.3 seconds
Started Jul 24 05:22:56 PM PDT 24
Finished Jul 24 05:22:58 PM PDT 24
Peak memory 201644 kb
Host smart-0b57a314-d1f4-401e-8f9c-a57644631f80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243956029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.4243956029
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3751805837
Short name T894
Test name
Test status
Simulation time 528653808 ps
CPU time 1.73 seconds
Started Jul 24 05:23:02 PM PDT 24
Finished Jul 24 05:23:04 PM PDT 24
Peak memory 201468 kb
Host smart-b5dd7ec7-87e4-4726-9c91-233cb880e429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751805837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3751805837
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.45492979
Short name T900
Test name
Test status
Simulation time 390006890 ps
CPU time 1.36 seconds
Started Jul 24 05:22:47 PM PDT 24
Finished Jul 24 05:22:49 PM PDT 24
Peak memory 201496 kb
Host smart-5736dcc0-4a1f-4d1c-a605-b1114cd82ec1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45492979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.45492979
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4225730709
Short name T847
Test name
Test status
Simulation time 479114019 ps
CPU time 0.91 seconds
Started Jul 24 05:22:49 PM PDT 24
Finished Jul 24 05:22:50 PM PDT 24
Peak memory 201504 kb
Host smart-9ff8a8ae-2524-4c11-8d0f-492af6eb5bcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225730709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.4225730709
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3621973921
Short name T815
Test name
Test status
Simulation time 353364826 ps
CPU time 0.86 seconds
Started Jul 24 05:22:50 PM PDT 24
Finished Jul 24 05:22:51 PM PDT 24
Peak memory 201504 kb
Host smart-285e5f09-27ca-4cfd-9a32-abcfdcf0bf89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621973921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3621973921
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1341998351
Short name T896
Test name
Test status
Simulation time 483579222 ps
CPU time 1.11 seconds
Started Jul 24 05:22:59 PM PDT 24
Finished Jul 24 05:23:00 PM PDT 24
Peak memory 201464 kb
Host smart-b9ac6322-b09b-4d30-b031-7943c5009667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341998351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1341998351
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.630781959
Short name T886
Test name
Test status
Simulation time 378811871 ps
CPU time 0.81 seconds
Started Jul 24 05:23:00 PM PDT 24
Finished Jul 24 05:23:00 PM PDT 24
Peak memory 201416 kb
Host smart-460c78b5-0771-430e-a3c8-bf566103b6fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630781959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.630781959
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2796038872
Short name T120
Test name
Test status
Simulation time 963026079 ps
CPU time 4.62 seconds
Started Jul 24 05:22:37 PM PDT 24
Finished Jul 24 05:22:42 PM PDT 24
Peak memory 201672 kb
Host smart-fa3761db-390d-49a9-975d-3bc52cbaad70
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796038872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2796038872
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2257442943
Short name T121
Test name
Test status
Simulation time 29705718080 ps
CPU time 17.72 seconds
Started Jul 24 05:22:37 PM PDT 24
Finished Jul 24 05:22:55 PM PDT 24
Peak memory 201672 kb
Host smart-9f290232-06d6-412e-9b56-a0c096d9b0de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257442943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2257442943
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3461055368
Short name T849
Test name
Test status
Simulation time 683148465 ps
CPU time 1.05 seconds
Started Jul 24 05:22:42 PM PDT 24
Finished Jul 24 05:22:44 PM PDT 24
Peak memory 201408 kb
Host smart-7d01d2b1-9c50-4abe-a458-f1cc37e00a80
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461055368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3461055368
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3083856323
Short name T829
Test name
Test status
Simulation time 555516406 ps
CPU time 1.15 seconds
Started Jul 24 05:22:35 PM PDT 24
Finished Jul 24 05:22:37 PM PDT 24
Peak memory 201624 kb
Host smart-e38d11f8-7111-4c55-9cca-80bf2458d6ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083856323 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3083856323
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3531481024
Short name T828
Test name
Test status
Simulation time 385649402 ps
CPU time 1.6 seconds
Started Jul 24 05:22:36 PM PDT 24
Finished Jul 24 05:22:37 PM PDT 24
Peak memory 201460 kb
Host smart-f6c999fa-5240-47f8-9d98-696121a3669f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531481024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3531481024
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4229228918
Short name T844
Test name
Test status
Simulation time 378312132 ps
CPU time 1.51 seconds
Started Jul 24 05:22:36 PM PDT 24
Finished Jul 24 05:22:38 PM PDT 24
Peak memory 201520 kb
Host smart-2f0ddaeb-0eaa-4412-ac2f-5952650c27ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229228918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.4229228918
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.976165196
Short name T807
Test name
Test status
Simulation time 2660858943 ps
CPU time 2.33 seconds
Started Jul 24 05:22:37 PM PDT 24
Finished Jul 24 05:22:39 PM PDT 24
Peak memory 201552 kb
Host smart-f798cdd9-c255-45f9-a824-14ef7c037cdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976165196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.976165196
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3501002217
Short name T839
Test name
Test status
Simulation time 490151270 ps
CPU time 2.12 seconds
Started Jul 24 05:22:36 PM PDT 24
Finished Jul 24 05:22:39 PM PDT 24
Peak memory 201888 kb
Host smart-81242458-9f5e-409c-a8e3-6916482fa538
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501002217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3501002217
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3283318618
Short name T906
Test name
Test status
Simulation time 8606129373 ps
CPU time 4.95 seconds
Started Jul 24 05:22:36 PM PDT 24
Finished Jul 24 05:22:41 PM PDT 24
Peak memory 201752 kb
Host smart-468a8b9c-d863-49d8-8a83-2b93a84793b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283318618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3283318618
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.4040921882
Short name T892
Test name
Test status
Simulation time 430049569 ps
CPU time 0.94 seconds
Started Jul 24 05:22:53 PM PDT 24
Finished Jul 24 05:22:54 PM PDT 24
Peak memory 201512 kb
Host smart-bca63477-a7ca-4da2-9d5e-87eb3aeaf618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040921882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.4040921882
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.3283406378
Short name T800
Test name
Test status
Simulation time 521932120 ps
CPU time 1.2 seconds
Started Jul 24 05:22:51 PM PDT 24
Finished Jul 24 05:22:52 PM PDT 24
Peak memory 201496 kb
Host smart-7c6e61d5-a291-4fc4-98fd-059e444a948e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283406378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.3283406378
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2252555869
Short name T872
Test name
Test status
Simulation time 346373141 ps
CPU time 1.48 seconds
Started Jul 24 05:23:04 PM PDT 24
Finished Jul 24 05:23:05 PM PDT 24
Peak memory 201436 kb
Host smart-f247cdd4-9265-492b-9d0b-8b0dca3f9681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252555869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2252555869
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2016311600
Short name T812
Test name
Test status
Simulation time 486983506 ps
CPU time 1.76 seconds
Started Jul 24 05:22:52 PM PDT 24
Finished Jul 24 05:22:54 PM PDT 24
Peak memory 201460 kb
Host smart-91d884c9-9035-46b1-b8bb-fcc111576555
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016311600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2016311600
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2934434017
Short name T866
Test name
Test status
Simulation time 448340159 ps
CPU time 1.65 seconds
Started Jul 24 05:23:03 PM PDT 24
Finished Jul 24 05:23:05 PM PDT 24
Peak memory 201408 kb
Host smart-d0da3381-da43-4da0-8d0d-c2a64b5be2be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934434017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2934434017
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.819532532
Short name T861
Test name
Test status
Simulation time 463225558 ps
CPU time 1.67 seconds
Started Jul 24 05:23:00 PM PDT 24
Finished Jul 24 05:23:03 PM PDT 24
Peak memory 201452 kb
Host smart-cd428a48-af6a-4157-a9c2-dcc9fd8f2505
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819532532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.819532532
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.83824392
Short name T817
Test name
Test status
Simulation time 521190018 ps
CPU time 1.7 seconds
Started Jul 24 05:22:51 PM PDT 24
Finished Jul 24 05:22:52 PM PDT 24
Peak memory 201484 kb
Host smart-2189631a-0e42-4e58-b714-f9b8c65b5fad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83824392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.83824392
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.4157669053
Short name T867
Test name
Test status
Simulation time 318367877 ps
CPU time 1.17 seconds
Started Jul 24 05:22:51 PM PDT 24
Finished Jul 24 05:22:52 PM PDT 24
Peak memory 201472 kb
Host smart-94515fe5-4ebe-4b40-b6bd-17233116942f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157669053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.4157669053
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3182974016
Short name T840
Test name
Test status
Simulation time 369332479 ps
CPU time 1.03 seconds
Started Jul 24 05:22:47 PM PDT 24
Finished Jul 24 05:22:48 PM PDT 24
Peak memory 201500 kb
Host smart-ff186919-33cb-44d5-9661-468fb2ed0830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182974016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3182974016
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.583902874
Short name T841
Test name
Test status
Simulation time 359856260 ps
CPU time 1.03 seconds
Started Jul 24 05:22:52 PM PDT 24
Finished Jul 24 05:22:53 PM PDT 24
Peak memory 201364 kb
Host smart-979b69ca-8351-4c4e-85a5-1d03b371ff51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583902874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.583902874
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2678872385
Short name T855
Test name
Test status
Simulation time 458591184 ps
CPU time 1.89 seconds
Started Jul 24 05:22:39 PM PDT 24
Finished Jul 24 05:22:41 PM PDT 24
Peak memory 201600 kb
Host smart-bf1615c6-b63f-4029-b86a-8cc0ade4a821
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678872385 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2678872385
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3564471722
Short name T877
Test name
Test status
Simulation time 495137234 ps
CPU time 1.82 seconds
Started Jul 24 05:22:32 PM PDT 24
Finished Jul 24 05:22:34 PM PDT 24
Peak memory 201528 kb
Host smart-3aeea736-8e30-4154-880b-9d983c01ed29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564471722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3564471722
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.258895917
Short name T863
Test name
Test status
Simulation time 373365216 ps
CPU time 1.56 seconds
Started Jul 24 05:22:34 PM PDT 24
Finished Jul 24 05:22:36 PM PDT 24
Peak memory 201432 kb
Host smart-4107f008-c458-4943-ba5b-1074c6eb05b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258895917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.258895917
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3634221811
Short name T889
Test name
Test status
Simulation time 4423390386 ps
CPU time 6.07 seconds
Started Jul 24 05:22:42 PM PDT 24
Finished Jul 24 05:22:48 PM PDT 24
Peak memory 201800 kb
Host smart-4bbd9df2-cfb5-4585-b2a1-a44777d71e00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634221811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3634221811
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.3980176562
Short name T70
Test name
Test status
Simulation time 413072998 ps
CPU time 2.25 seconds
Started Jul 24 05:22:33 PM PDT 24
Finished Jul 24 05:22:35 PM PDT 24
Peak memory 201760 kb
Host smart-2f1cd27c-8049-425b-8335-e060906ab3ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980176562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.3980176562
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1292793590
Short name T824
Test name
Test status
Simulation time 4438868209 ps
CPU time 6.1 seconds
Started Jul 24 05:22:43 PM PDT 24
Finished Jul 24 05:22:49 PM PDT 24
Peak memory 201784 kb
Host smart-f46d1e7e-d13b-44a7-9210-e3fc58f9495a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292793590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1292793590
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.183504452
Short name T873
Test name
Test status
Simulation time 507399565 ps
CPU time 2.07 seconds
Started Jul 24 05:22:44 PM PDT 24
Finished Jul 24 05:22:46 PM PDT 24
Peak memory 201600 kb
Host smart-4a2dd463-acb8-438e-8a74-c6aafb4b6d4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183504452 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.183504452
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.997011795
Short name T116
Test name
Test status
Simulation time 513642847 ps
CPU time 1.88 seconds
Started Jul 24 05:22:37 PM PDT 24
Finished Jul 24 05:22:39 PM PDT 24
Peak memory 201368 kb
Host smart-09d77738-0aa6-41bf-9487-3b00fd0c463d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997011795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.997011795
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.734603722
Short name T905
Test name
Test status
Simulation time 520081570 ps
CPU time 1.77 seconds
Started Jul 24 05:22:43 PM PDT 24
Finished Jul 24 05:22:45 PM PDT 24
Peak memory 201424 kb
Host smart-b2e5efab-9823-4d35-894f-96753ee8ee53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734603722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.734603722
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2906796389
Short name T49
Test name
Test status
Simulation time 2447388314 ps
CPU time 3.9 seconds
Started Jul 24 05:22:33 PM PDT 24
Finished Jul 24 05:22:37 PM PDT 24
Peak memory 201576 kb
Host smart-9d94acd1-79ab-4313-9223-e4a006a66a23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906796389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2906796389
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2163769408
Short name T898
Test name
Test status
Simulation time 772015940 ps
CPU time 3.02 seconds
Started Jul 24 05:22:34 PM PDT 24
Finished Jul 24 05:22:37 PM PDT 24
Peak memory 201688 kb
Host smart-b50daa15-5445-4730-bd0a-7d19a333803d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163769408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2163769408
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2473617588
Short name T908
Test name
Test status
Simulation time 8278367879 ps
CPU time 22.47 seconds
Started Jul 24 05:22:35 PM PDT 24
Finished Jul 24 05:22:58 PM PDT 24
Peak memory 201820 kb
Host smart-da488362-8030-4aca-869b-ae3f6884c0b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473617588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2473617588
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2768516423
Short name T879
Test name
Test status
Simulation time 554108864 ps
CPU time 2.06 seconds
Started Jul 24 05:22:34 PM PDT 24
Finished Jul 24 05:22:36 PM PDT 24
Peak memory 201524 kb
Host smart-fbc99880-65cb-4be1-af2f-a4fa4f7a25d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768516423 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2768516423
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.553942377
Short name T122
Test name
Test status
Simulation time 402905557 ps
CPU time 0.94 seconds
Started Jul 24 05:22:38 PM PDT 24
Finished Jul 24 05:22:39 PM PDT 24
Peak memory 201476 kb
Host smart-b9677437-c3ea-4804-9e7e-35ee41326d53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553942377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.553942377
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2254350632
Short name T830
Test name
Test status
Simulation time 474872117 ps
CPU time 1.76 seconds
Started Jul 24 05:22:34 PM PDT 24
Finished Jul 24 05:22:36 PM PDT 24
Peak memory 201404 kb
Host smart-f58a620c-897c-4d08-8edb-b183071fc1f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254350632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2254350632
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3250796129
Short name T809
Test name
Test status
Simulation time 1862074778 ps
CPU time 3.34 seconds
Started Jul 24 05:22:35 PM PDT 24
Finished Jul 24 05:22:39 PM PDT 24
Peak memory 201528 kb
Host smart-ee6836a0-282c-47c5-a428-e9427a0320ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250796129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3250796129
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2016327680
Short name T860
Test name
Test status
Simulation time 478236745 ps
CPU time 2.75 seconds
Started Jul 24 05:22:33 PM PDT 24
Finished Jul 24 05:22:36 PM PDT 24
Peak memory 201756 kb
Host smart-235af03f-96b0-40f5-a26b-f74cae06470c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016327680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2016327680
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1178233732
Short name T69
Test name
Test status
Simulation time 4290178583 ps
CPU time 11.11 seconds
Started Jul 24 05:22:31 PM PDT 24
Finished Jul 24 05:22:42 PM PDT 24
Peak memory 201820 kb
Host smart-6d7f7f27-423b-4cf3-a6d5-0f31661e15af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178233732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1178233732
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2106052203
Short name T850
Test name
Test status
Simulation time 508570553 ps
CPU time 1.6 seconds
Started Jul 24 05:22:46 PM PDT 24
Finished Jul 24 05:22:48 PM PDT 24
Peak memory 201784 kb
Host smart-21feae03-7d29-4451-8598-2ccbe681cd52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106052203 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2106052203
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1033438572
Short name T112
Test name
Test status
Simulation time 496714102 ps
CPU time 1.39 seconds
Started Jul 24 05:22:39 PM PDT 24
Finished Jul 24 05:22:40 PM PDT 24
Peak memory 201380 kb
Host smart-39ca1db5-324e-4872-b39d-1152752225f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033438572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1033438572
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3784459063
Short name T826
Test name
Test status
Simulation time 403130694 ps
CPU time 1.41 seconds
Started Jul 24 05:22:42 PM PDT 24
Finished Jul 24 05:22:43 PM PDT 24
Peak memory 201408 kb
Host smart-0caf7d9f-7ee8-42db-8c64-e6c65328c352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784459063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3784459063
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1492960152
Short name T814
Test name
Test status
Simulation time 1992710609 ps
CPU time 1.65 seconds
Started Jul 24 05:22:40 PM PDT 24
Finished Jul 24 05:22:42 PM PDT 24
Peak memory 201416 kb
Host smart-5a388806-f308-4412-8f1b-2c1739972ce9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492960152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1492960152
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3889909071
Short name T65
Test name
Test status
Simulation time 559340618 ps
CPU time 3.33 seconds
Started Jul 24 05:22:33 PM PDT 24
Finished Jul 24 05:22:37 PM PDT 24
Peak memory 217644 kb
Host smart-c66a6ef1-7fa5-4c62-9662-6285a97a9d30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889909071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3889909071
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.614501082
Short name T901
Test name
Test status
Simulation time 9117797450 ps
CPU time 6.78 seconds
Started Jul 24 05:22:35 PM PDT 24
Finished Jul 24 05:22:41 PM PDT 24
Peak memory 201808 kb
Host smart-6d3ff405-62a6-412c-a6e2-7052974e2327
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614501082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.614501082
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4043936611
Short name T836
Test name
Test status
Simulation time 428983273 ps
CPU time 1.89 seconds
Started Jul 24 05:22:37 PM PDT 24
Finished Jul 24 05:22:39 PM PDT 24
Peak memory 201552 kb
Host smart-b253386c-b898-49c7-af1e-53ecea562366
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043936611 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.4043936611
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.2049654233
Short name T124
Test name
Test status
Simulation time 493807138 ps
CPU time 1.89 seconds
Started Jul 24 05:22:50 PM PDT 24
Finished Jul 24 05:22:52 PM PDT 24
Peak memory 201464 kb
Host smart-f5cc2207-711b-4d8d-9a57-31da38d7a761
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049654233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.2049654233
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1692351817
Short name T876
Test name
Test status
Simulation time 315116146 ps
CPU time 1.33 seconds
Started Jul 24 05:22:40 PM PDT 24
Finished Jul 24 05:22:41 PM PDT 24
Peak memory 201464 kb
Host smart-931dfe46-3dce-411b-9600-2e5ccfd1754c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692351817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1692351817
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1946344903
Short name T50
Test name
Test status
Simulation time 2661186463 ps
CPU time 6.4 seconds
Started Jul 24 05:22:40 PM PDT 24
Finished Jul 24 05:22:47 PM PDT 24
Peak memory 201620 kb
Host smart-4dc91a2f-e0fe-49e2-a39c-1110b6157d0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946344903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1946344903
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3277584885
Short name T66
Test name
Test status
Simulation time 446949615 ps
CPU time 2.82 seconds
Started Jul 24 05:22:41 PM PDT 24
Finished Jul 24 05:22:44 PM PDT 24
Peak memory 218100 kb
Host smart-3bc71203-da4f-4698-8c25-68cb36dad44f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277584885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3277584885
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3493620767
Short name T343
Test name
Test status
Simulation time 4344929541 ps
CPU time 10.59 seconds
Started Jul 24 05:22:42 PM PDT 24
Finished Jul 24 05:22:53 PM PDT 24
Peak memory 201860 kb
Host smart-f7bca885-134c-4815-a024-26e3360c7395
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493620767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3493620767
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2214242873
Short name T722
Test name
Test status
Simulation time 320736821 ps
CPU time 1.03 seconds
Started Jul 24 07:10:01 PM PDT 24
Finished Jul 24 07:10:03 PM PDT 24
Peak memory 201036 kb
Host smart-ac73f1ce-6f23-47de-bf7f-5fafec0cac08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214242873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2214242873
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1948842189
Short name T602
Test name
Test status
Simulation time 585855828452 ps
CPU time 243.07 seconds
Started Jul 24 07:09:58 PM PDT 24
Finished Jul 24 07:14:02 PM PDT 24
Peak memory 201244 kb
Host smart-618d3ed3-6129-420b-8bec-8201f70150c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948842189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1948842189
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.49664707
Short name T533
Test name
Test status
Simulation time 163220258408 ps
CPU time 107.79 seconds
Started Jul 24 07:10:06 PM PDT 24
Finished Jul 24 07:11:54 PM PDT 24
Peak memory 201144 kb
Host smart-1bcb8b66-e893-421d-a302-5d768ff61d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49664707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.49664707
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.199088627
Short name T212
Test name
Test status
Simulation time 485666984291 ps
CPU time 1130.52 seconds
Started Jul 24 07:09:57 PM PDT 24
Finished Jul 24 07:28:48 PM PDT 24
Peak memory 201264 kb
Host smart-4f068805-a7cd-4fa7-8608-826a1b56b8f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=199088627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.199088627
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.4015755773
Short name T339
Test name
Test status
Simulation time 498714903456 ps
CPU time 1212.86 seconds
Started Jul 24 07:10:04 PM PDT 24
Finished Jul 24 07:30:17 PM PDT 24
Peak memory 201328 kb
Host smart-26dc377d-2d4a-4ae6-944d-3f0820f92eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015755773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.4015755773
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2477352329
Short name T25
Test name
Test status
Simulation time 167266283286 ps
CPU time 189.91 seconds
Started Jul 24 07:10:05 PM PDT 24
Finished Jul 24 07:13:15 PM PDT 24
Peak memory 201200 kb
Host smart-133e2fcd-73e6-4fa2-886a-0c80194a9813
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477352329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2477352329
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.4288149267
Short name T240
Test name
Test status
Simulation time 355875361669 ps
CPU time 67.49 seconds
Started Jul 24 07:10:05 PM PDT 24
Finished Jul 24 07:11:12 PM PDT 24
Peak memory 201300 kb
Host smart-96286c38-8d05-462d-8342-bf0b4fac59fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288149267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.4288149267
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.202080908
Short name T396
Test name
Test status
Simulation time 394429858102 ps
CPU time 849.63 seconds
Started Jul 24 07:10:06 PM PDT 24
Finished Jul 24 07:24:16 PM PDT 24
Peak memory 201200 kb
Host smart-cfbed565-b201-44e0-822d-7bebe194c1db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202080908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.202080908
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.980306551
Short name T621
Test name
Test status
Simulation time 122296846251 ps
CPU time 615.75 seconds
Started Jul 24 07:09:58 PM PDT 24
Finished Jul 24 07:20:14 PM PDT 24
Peak memory 201704 kb
Host smart-ad64b106-e0bf-49d9-9b31-b1304777e051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980306551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.980306551
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3796945282
Short name T404
Test name
Test status
Simulation time 28456241389 ps
CPU time 6.3 seconds
Started Jul 24 07:10:02 PM PDT 24
Finished Jul 24 07:10:09 PM PDT 24
Peak memory 201092 kb
Host smart-22072dc7-e90e-48ee-8d0a-422780b3906e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796945282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3796945282
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.4238277136
Short name T516
Test name
Test status
Simulation time 2912835891 ps
CPU time 7.5 seconds
Started Jul 24 07:10:09 PM PDT 24
Finished Jul 24 07:10:16 PM PDT 24
Peak memory 201048 kb
Host smart-aa0cef3f-0030-41cb-be3b-a992b7ea9dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238277136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.4238277136
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2925454358
Short name T611
Test name
Test status
Simulation time 6108061093 ps
CPU time 9.08 seconds
Started Jul 24 07:10:02 PM PDT 24
Finished Jul 24 07:10:11 PM PDT 24
Peak memory 201084 kb
Host smart-cb019ce2-6005-418d-83a8-28cbab6de984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925454358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2925454358
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1056265493
Short name T268
Test name
Test status
Simulation time 165750124622 ps
CPU time 207.99 seconds
Started Jul 24 07:10:10 PM PDT 24
Finished Jul 24 07:13:39 PM PDT 24
Peak memory 218020 kb
Host smart-8d8e19d2-6a5f-4ad3-a063-980ebcc8fed5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056265493 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1056265493
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2611159036
Short name T545
Test name
Test status
Simulation time 367692394 ps
CPU time 0.83 seconds
Started Jul 24 07:10:06 PM PDT 24
Finished Jul 24 07:10:07 PM PDT 24
Peak memory 201076 kb
Host smart-b055be9b-d7ab-4ce2-a942-1c0094b1cbe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611159036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2611159036
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.168270507
Short name T326
Test name
Test status
Simulation time 336559482509 ps
CPU time 394.27 seconds
Started Jul 24 07:10:05 PM PDT 24
Finished Jul 24 07:16:40 PM PDT 24
Peak memory 201220 kb
Host smart-6ca2dd7e-5e31-4088-9acd-5c0b855fe8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168270507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.168270507
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3186106571
Short name T610
Test name
Test status
Simulation time 164163079962 ps
CPU time 203.7 seconds
Started Jul 24 07:10:07 PM PDT 24
Finished Jul 24 07:13:31 PM PDT 24
Peak memory 201240 kb
Host smart-576c0f84-4a25-4523-96fb-e5ca9170d9d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186106571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3186106571
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.4031793602
Short name T311
Test name
Test status
Simulation time 493303780441 ps
CPU time 324.44 seconds
Started Jul 24 07:10:02 PM PDT 24
Finished Jul 24 07:15:27 PM PDT 24
Peak memory 201300 kb
Host smart-f46c4ea3-69d7-4068-9852-fe74ca1ef8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031793602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.4031793602
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1114264611
Short name T433
Test name
Test status
Simulation time 491723038088 ps
CPU time 1170.99 seconds
Started Jul 24 07:10:03 PM PDT 24
Finished Jul 24 07:29:34 PM PDT 24
Peak memory 201212 kb
Host smart-bffd7061-85ed-489e-b073-b75b61858599
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114264611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1114264611
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.716611614
Short name T521
Test name
Test status
Simulation time 607043746318 ps
CPU time 240.36 seconds
Started Jul 24 07:10:01 PM PDT 24
Finished Jul 24 07:14:01 PM PDT 24
Peak memory 201216 kb
Host smart-ab1e305f-6832-475f-8d55-f6cf287355c7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716611614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.716611614
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1773339682
Short name T87
Test name
Test status
Simulation time 128726996920 ps
CPU time 366.05 seconds
Started Jul 24 07:10:07 PM PDT 24
Finished Jul 24 07:16:13 PM PDT 24
Peak memory 201672 kb
Host smart-da952ba3-d172-470e-825d-3798f50299e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773339682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1773339682
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2087321740
Short name T591
Test name
Test status
Simulation time 24195415073 ps
CPU time 55.67 seconds
Started Jul 24 07:10:03 PM PDT 24
Finished Jul 24 07:10:59 PM PDT 24
Peak memory 201104 kb
Host smart-1e5cb960-8e67-4fd8-a992-e7bc0204d817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087321740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2087321740
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3545080221
Short name T658
Test name
Test status
Simulation time 3146753902 ps
CPU time 8.19 seconds
Started Jul 24 07:10:06 PM PDT 24
Finished Jul 24 07:10:14 PM PDT 24
Peak memory 201044 kb
Host smart-10284952-634a-482f-9b7e-c18c1acba6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545080221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3545080221
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2886671688
Short name T61
Test name
Test status
Simulation time 4120119097 ps
CPU time 10.73 seconds
Started Jul 24 07:09:59 PM PDT 24
Finished Jul 24 07:10:10 PM PDT 24
Peak memory 216840 kb
Host smart-85da9186-b685-494d-975d-06025d044f41
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886671688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2886671688
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2513621873
Short name T462
Test name
Test status
Simulation time 5707065983 ps
CPU time 4.69 seconds
Started Jul 24 07:09:56 PM PDT 24
Finished Jul 24 07:10:01 PM PDT 24
Peak memory 201116 kb
Host smart-73e79060-51d3-43e7-b2ce-8544089eb72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513621873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2513621873
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.903630042
Short name T541
Test name
Test status
Simulation time 214637372277 ps
CPU time 408.72 seconds
Started Jul 24 07:09:58 PM PDT 24
Finished Jul 24 07:16:47 PM PDT 24
Peak memory 201240 kb
Host smart-9c42f63c-12b1-4a63-9e0e-ffe158145c68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903630042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.903630042
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.484456433
Short name T523
Test name
Test status
Simulation time 407304385 ps
CPU time 1.03 seconds
Started Jul 24 07:10:23 PM PDT 24
Finished Jul 24 07:10:25 PM PDT 24
Peak memory 201036 kb
Host smart-9614320e-eaea-4460-8bb5-b60d8ee3ea34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484456433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.484456433
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3854615480
Short name T2
Test name
Test status
Simulation time 168005306205 ps
CPU time 380.6 seconds
Started Jul 24 07:10:22 PM PDT 24
Finished Jul 24 07:16:43 PM PDT 24
Peak memory 201200 kb
Host smart-96c58a20-37cc-4e16-8fa2-bb604b8ba5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854615480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3854615480
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.54595799
Short name T519
Test name
Test status
Simulation time 165250273824 ps
CPU time 382.04 seconds
Started Jul 24 07:10:22 PM PDT 24
Finished Jul 24 07:16:44 PM PDT 24
Peak memory 201280 kb
Host smart-82cac193-fcf1-4bde-9a42-910cd0ab0671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54595799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.54595799
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3939581654
Short name T626
Test name
Test status
Simulation time 485175157646 ps
CPU time 287.42 seconds
Started Jul 24 07:10:21 PM PDT 24
Finished Jul 24 07:15:08 PM PDT 24
Peak memory 201176 kb
Host smart-edb1c6a9-c379-434f-80b9-68733788c528
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939581654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3939581654
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1586959103
Short name T180
Test name
Test status
Simulation time 329313373148 ps
CPU time 44.96 seconds
Started Jul 24 07:10:18 PM PDT 24
Finished Jul 24 07:11:03 PM PDT 24
Peak memory 201360 kb
Host smart-8aaac6bb-b2b2-4f73-97bf-c2eecd2a9719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586959103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1586959103
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1992214031
Short name T511
Test name
Test status
Simulation time 495912149777 ps
CPU time 1215.86 seconds
Started Jul 24 07:10:37 PM PDT 24
Finished Jul 24 07:30:53 PM PDT 24
Peak memory 201240 kb
Host smart-9161b900-1dc0-414d-a4e6-88e66a7cff1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992214031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1992214031
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.479477972
Short name T629
Test name
Test status
Simulation time 596041201831 ps
CPU time 240.45 seconds
Started Jul 24 07:10:37 PM PDT 24
Finished Jul 24 07:14:38 PM PDT 24
Peak memory 201244 kb
Host smart-d93c1a76-4e96-4a20-951c-f3c2b5760297
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479477972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.479477972
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3420821825
Short name T675
Test name
Test status
Simulation time 93684050316 ps
CPU time 330.27 seconds
Started Jul 24 07:10:27 PM PDT 24
Finished Jul 24 07:15:58 PM PDT 24
Peak memory 201692 kb
Host smart-31dad836-1679-43fc-976e-bfe680e51157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420821825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3420821825
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.4171453183
Short name T446
Test name
Test status
Simulation time 39918673028 ps
CPU time 19.84 seconds
Started Jul 24 07:10:20 PM PDT 24
Finished Jul 24 07:10:40 PM PDT 24
Peak memory 201084 kb
Host smart-2d966c83-6bf1-439c-9204-a7abc19f6d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171453183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.4171453183
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2537109784
Short name T455
Test name
Test status
Simulation time 3329967337 ps
CPU time 8.66 seconds
Started Jul 24 07:10:21 PM PDT 24
Finished Jul 24 07:10:30 PM PDT 24
Peak memory 201060 kb
Host smart-7148da9b-8b93-4ba1-8d16-322a6010e490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537109784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2537109784
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3689170256
Short name T426
Test name
Test status
Simulation time 5643618555 ps
CPU time 11.22 seconds
Started Jul 24 07:10:23 PM PDT 24
Finished Jul 24 07:10:34 PM PDT 24
Peak memory 201228 kb
Host smart-e65b2d7a-7218-4a88-ab7f-8cbfd74519ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689170256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3689170256
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.299934797
Short name T329
Test name
Test status
Simulation time 179874008766 ps
CPU time 84.18 seconds
Started Jul 24 07:10:22 PM PDT 24
Finished Jul 24 07:11:46 PM PDT 24
Peak memory 201276 kb
Host smart-a4f28977-0bc7-42b7-a841-d38e61efe8b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299934797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
299934797
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3662301269
Short name T767
Test name
Test status
Simulation time 495672155 ps
CPU time 1.22 seconds
Started Jul 24 07:10:23 PM PDT 24
Finished Jul 24 07:10:25 PM PDT 24
Peak memory 201028 kb
Host smart-b32b0325-710d-4108-ac7f-876b65ec69da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662301269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3662301269
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2966339976
Short name T697
Test name
Test status
Simulation time 546337261768 ps
CPU time 657.89 seconds
Started Jul 24 07:10:24 PM PDT 24
Finished Jul 24 07:21:22 PM PDT 24
Peak memory 201252 kb
Host smart-ac794173-38bf-4c50-933b-deef8c7eff5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966339976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2966339976
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2418467888
Short name T748
Test name
Test status
Simulation time 169464846922 ps
CPU time 102.08 seconds
Started Jul 24 07:10:19 PM PDT 24
Finished Jul 24 07:12:01 PM PDT 24
Peak memory 201320 kb
Host smart-ec712469-30e3-4a0e-9da8-c7b1fb082d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418467888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2418467888
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2221532360
Short name T151
Test name
Test status
Simulation time 163887423183 ps
CPU time 65.91 seconds
Started Jul 24 07:10:22 PM PDT 24
Finished Jul 24 07:11:29 PM PDT 24
Peak memory 201432 kb
Host smart-15d54211-eb72-4408-9934-7b5fed228224
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221532360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2221532360
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3658387638
Short name T289
Test name
Test status
Simulation time 323945338099 ps
CPU time 287.24 seconds
Started Jul 24 07:10:32 PM PDT 24
Finished Jul 24 07:15:19 PM PDT 24
Peak memory 201304 kb
Host smart-ef7e44af-d3d6-466b-905d-7eaf36e90c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658387638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3658387638
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3598627471
Short name T792
Test name
Test status
Simulation time 165993930909 ps
CPU time 103.72 seconds
Started Jul 24 07:10:22 PM PDT 24
Finished Jul 24 07:12:06 PM PDT 24
Peak memory 201288 kb
Host smart-be06ad8c-6038-4d9a-8fc9-db0ceaa2d5fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598627471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3598627471
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2343900924
Short name T584
Test name
Test status
Simulation time 184260792357 ps
CPU time 26.62 seconds
Started Jul 24 07:10:20 PM PDT 24
Finished Jul 24 07:10:46 PM PDT 24
Peak memory 201232 kb
Host smart-815a02dc-a90c-47c0-9e8b-2014a8c6e55e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343900924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2343900924
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2678072710
Short name T459
Test name
Test status
Simulation time 104063482885 ps
CPU time 421.94 seconds
Started Jul 24 07:10:34 PM PDT 24
Finished Jul 24 07:17:36 PM PDT 24
Peak memory 201664 kb
Host smart-90330bda-2cd9-49d2-8e1c-18ad0cae87e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678072710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2678072710
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.789683064
Short name T559
Test name
Test status
Simulation time 42296973849 ps
CPU time 96.05 seconds
Started Jul 24 07:10:35 PM PDT 24
Finished Jul 24 07:12:11 PM PDT 24
Peak memory 200980 kb
Host smart-9e1225e9-e370-4919-8557-c0b6d9235e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789683064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.789683064
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.768731771
Short name T524
Test name
Test status
Simulation time 3022000165 ps
CPU time 2.36 seconds
Started Jul 24 07:10:22 PM PDT 24
Finished Jul 24 07:10:24 PM PDT 24
Peak memory 201088 kb
Host smart-fe897373-f447-435b-9742-eabec45a5e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768731771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.768731771
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1730325961
Short name T689
Test name
Test status
Simulation time 5959399457 ps
CPU time 7.48 seconds
Started Jul 24 07:10:19 PM PDT 24
Finished Jul 24 07:10:27 PM PDT 24
Peak memory 201108 kb
Host smart-a968e59c-b67a-4f2f-97cd-6cd56c679597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730325961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1730325961
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.4091396635
Short name T662
Test name
Test status
Simulation time 1462987920787 ps
CPU time 721.81 seconds
Started Jul 24 07:10:22 PM PDT 24
Finished Jul 24 07:22:25 PM PDT 24
Peak memory 201664 kb
Host smart-8af29217-c78a-43df-bfc0-e6e5a66b9de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091396635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.4091396635
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2690570029
Short name T81
Test name
Test status
Simulation time 27798840211 ps
CPU time 60.63 seconds
Started Jul 24 07:10:23 PM PDT 24
Finished Jul 24 07:11:24 PM PDT 24
Peak memory 201380 kb
Host smart-e0ea36ec-eebb-4853-82fd-77a9f4501777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690570029 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2690570029
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3764921970
Short name T103
Test name
Test status
Simulation time 348737209 ps
CPU time 0.85 seconds
Started Jul 24 07:10:24 PM PDT 24
Finished Jul 24 07:10:25 PM PDT 24
Peak memory 201036 kb
Host smart-336544c0-db11-4b9d-9787-627e9a5a3717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764921970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3764921970
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.497133955
Short name T234
Test name
Test status
Simulation time 524295096542 ps
CPU time 840.79 seconds
Started Jul 24 07:10:26 PM PDT 24
Finished Jul 24 07:24:27 PM PDT 24
Peak memory 201156 kb
Host smart-0a0daba7-da99-45cf-b5d1-df07f519e5f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497133955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.497133955
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1003343445
Short name T229
Test name
Test status
Simulation time 167250487235 ps
CPU time 94.1 seconds
Started Jul 24 07:10:37 PM PDT 24
Finished Jul 24 07:12:12 PM PDT 24
Peak memory 201288 kb
Host smart-25eb66aa-74ee-4228-81d8-4b000c4bd9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003343445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1003343445
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.28920927
Short name T100
Test name
Test status
Simulation time 495260900262 ps
CPU time 100.03 seconds
Started Jul 24 07:10:23 PM PDT 24
Finished Jul 24 07:12:04 PM PDT 24
Peak memory 201248 kb
Host smart-234e05fc-6b4a-42ac-8488-dfb9130933d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=28920927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt
_fixed.28920927
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1821068195
Short name T94
Test name
Test status
Simulation time 164238600963 ps
CPU time 31.3 seconds
Started Jul 24 07:10:23 PM PDT 24
Finished Jul 24 07:10:55 PM PDT 24
Peak memory 201232 kb
Host smart-26eca9aa-1b7a-4fd8-bfc9-733389da9ca1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821068195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1821068195
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2155786723
Short name T176
Test name
Test status
Simulation time 566652327165 ps
CPU time 240.61 seconds
Started Jul 24 07:10:34 PM PDT 24
Finished Jul 24 07:14:35 PM PDT 24
Peak memory 201192 kb
Host smart-235008f5-612d-43e9-b6f8-f8484e2c78de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155786723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2155786723
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.32452894
Short name T5
Test name
Test status
Simulation time 396633027377 ps
CPU time 237.08 seconds
Started Jul 24 07:10:25 PM PDT 24
Finished Jul 24 07:14:22 PM PDT 24
Peak memory 201272 kb
Host smart-98c33bd9-32a2-4ea1-a9f8-3dba3d77115b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32452894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.a
dc_ctrl_filters_wakeup_fixed.32452894
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.4262121262
Short name T719
Test name
Test status
Simulation time 116933001333 ps
CPU time 631.62 seconds
Started Jul 24 07:10:22 PM PDT 24
Finished Jul 24 07:20:54 PM PDT 24
Peak memory 201716 kb
Host smart-2117617c-a169-4c2c-8e6a-41461bf3a3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262121262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.4262121262
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.4113006240
Short name T179
Test name
Test status
Simulation time 43579905000 ps
CPU time 107.4 seconds
Started Jul 24 07:10:33 PM PDT 24
Finished Jul 24 07:12:21 PM PDT 24
Peak memory 201052 kb
Host smart-c30badec-2e20-4630-a07c-9ac446da4194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113006240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.4113006240
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.4171949230
Short name T678
Test name
Test status
Simulation time 4998436427 ps
CPU time 2.79 seconds
Started Jul 24 07:10:27 PM PDT 24
Finished Jul 24 07:10:31 PM PDT 24
Peak memory 201100 kb
Host smart-abda3dc9-4223-432c-966a-91f963ee5cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171949230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.4171949230
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.1481537605
Short name T612
Test name
Test status
Simulation time 5900583072 ps
CPU time 7.53 seconds
Started Jul 24 07:10:27 PM PDT 24
Finished Jul 24 07:10:35 PM PDT 24
Peak memory 201108 kb
Host smart-27b24461-76f0-481f-823c-c3c9a27ba213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481537605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.1481537605
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.60069988
Short name T482
Test name
Test status
Simulation time 275601608345 ps
CPU time 891.99 seconds
Started Jul 24 07:10:24 PM PDT 24
Finished Jul 24 07:25:16 PM PDT 24
Peak memory 209884 kb
Host smart-7a7409bb-2ba7-4887-b0fd-47aa1f3a995c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60069988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.60069988
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2350928420
Short name T403
Test name
Test status
Simulation time 520066902 ps
CPU time 1.83 seconds
Started Jul 24 07:10:31 PM PDT 24
Finished Jul 24 07:10:33 PM PDT 24
Peak memory 201052 kb
Host smart-8f6622e3-0a78-47e9-86ee-d5faeb35f715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350928420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2350928420
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1913695207
Short name T336
Test name
Test status
Simulation time 493085786135 ps
CPU time 554.86 seconds
Started Jul 24 07:10:33 PM PDT 24
Finished Jul 24 07:19:48 PM PDT 24
Peak memory 201248 kb
Host smart-197504e7-b4f7-4f38-a558-c89f1a17e503
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913695207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1913695207
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1136878605
Short name T585
Test name
Test status
Simulation time 329876418472 ps
CPU time 185.44 seconds
Started Jul 24 07:10:34 PM PDT 24
Finished Jul 24 07:13:40 PM PDT 24
Peak memory 201284 kb
Host smart-226576f3-2935-4be3-bb5a-794d89b23385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136878605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1136878605
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1456505124
Short name T543
Test name
Test status
Simulation time 490820152378 ps
CPU time 194.39 seconds
Started Jul 24 07:10:28 PM PDT 24
Finished Jul 24 07:13:43 PM PDT 24
Peak memory 201340 kb
Host smart-11ef4b93-9d50-4ad8-893a-4b6f5ef5bcf9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456505124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1456505124
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2496726453
Short name T569
Test name
Test status
Simulation time 162641842245 ps
CPU time 88.21 seconds
Started Jul 24 07:10:36 PM PDT 24
Finished Jul 24 07:12:05 PM PDT 24
Peak memory 201188 kb
Host smart-29c89071-e995-4a8b-bb96-04ec9c53703c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496726453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2496726453
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.836504019
Short name T412
Test name
Test status
Simulation time 317438216347 ps
CPU time 187.73 seconds
Started Jul 24 07:10:28 PM PDT 24
Finished Jul 24 07:13:36 PM PDT 24
Peak memory 201176 kb
Host smart-747bf4c5-306b-41c7-a493-f7ceb9e7af15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=836504019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.836504019
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3683054163
Short name T581
Test name
Test status
Simulation time 178143251443 ps
CPU time 204.17 seconds
Started Jul 24 07:10:40 PM PDT 24
Finished Jul 24 07:14:05 PM PDT 24
Peak memory 201220 kb
Host smart-dd0a5989-b3ec-41e1-b5b8-e9a9063a6b39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683054163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3683054163
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.217856820
Short name T731
Test name
Test status
Simulation time 415713310354 ps
CPU time 228.31 seconds
Started Jul 24 07:10:24 PM PDT 24
Finished Jul 24 07:14:12 PM PDT 24
Peak memory 201216 kb
Host smart-e391e6c1-df37-4a2a-8b6e-f8ff6c91d839
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217856820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.217856820
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3018182512
Short name T349
Test name
Test status
Simulation time 118461246683 ps
CPU time 413.73 seconds
Started Jul 24 07:10:37 PM PDT 24
Finished Jul 24 07:17:31 PM PDT 24
Peak memory 201708 kb
Host smart-52132f61-049d-4ef4-9c2c-f26aa25afc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018182512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3018182512
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2550906336
Short name T359
Test name
Test status
Simulation time 38839144311 ps
CPU time 17.94 seconds
Started Jul 24 07:10:22 PM PDT 24
Finished Jul 24 07:10:40 PM PDT 24
Peak memory 201092 kb
Host smart-9aa0c70e-a8d7-4a6d-a17d-23e12a612533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550906336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2550906336
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2485184909
Short name T599
Test name
Test status
Simulation time 3654010515 ps
CPU time 8.51 seconds
Started Jul 24 07:10:39 PM PDT 24
Finished Jul 24 07:10:48 PM PDT 24
Peak memory 201072 kb
Host smart-faf72ee3-5fb0-49c6-af9a-77ebaadb5b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485184909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2485184909
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2850347434
Short name T388
Test name
Test status
Simulation time 5692989652 ps
CPU time 13.12 seconds
Started Jul 24 07:10:33 PM PDT 24
Finished Jul 24 07:10:46 PM PDT 24
Peak memory 201008 kb
Host smart-535cf74e-efba-42b7-8de1-e3361a5ae4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850347434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2850347434
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1832724899
Short name T387
Test name
Test status
Simulation time 217152211211 ps
CPU time 77.22 seconds
Started Jul 24 07:10:29 PM PDT 24
Finished Jul 24 07:11:46 PM PDT 24
Peak memory 201288 kb
Host smart-103109da-4770-4c3a-b123-5c5a0a02ef2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832724899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1832724899
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.4042030102
Short name T774
Test name
Test status
Simulation time 429136894 ps
CPU time 1.61 seconds
Started Jul 24 07:10:30 PM PDT 24
Finished Jul 24 07:10:32 PM PDT 24
Peak memory 201048 kb
Host smart-12a027be-422d-4a7c-a9b9-e80d48b0e109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042030102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.4042030102
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3092561472
Short name T278
Test name
Test status
Simulation time 156885238669 ps
CPU time 385.82 seconds
Started Jul 24 07:10:30 PM PDT 24
Finished Jul 24 07:16:56 PM PDT 24
Peak memory 201268 kb
Host smart-ed70e01a-aa8f-49a9-88dd-4217cdf5bccf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092561472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3092561472
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.360118231
Short name T564
Test name
Test status
Simulation time 321623367916 ps
CPU time 369.84 seconds
Started Jul 24 07:10:35 PM PDT 24
Finished Jul 24 07:16:45 PM PDT 24
Peak memory 201304 kb
Host smart-24de6c77-4fc0-451b-a885-d2df32a08e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360118231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.360118231
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1930725998
Short name T106
Test name
Test status
Simulation time 328126872844 ps
CPU time 198.09 seconds
Started Jul 24 07:10:30 PM PDT 24
Finished Jul 24 07:13:48 PM PDT 24
Peak memory 201236 kb
Host smart-97c14271-beb1-4367-93af-31039b2574d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930725998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1930725998
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3407870786
Short name T436
Test name
Test status
Simulation time 485868712293 ps
CPU time 1170.19 seconds
Started Jul 24 07:10:34 PM PDT 24
Finished Jul 24 07:30:05 PM PDT 24
Peak memory 201168 kb
Host smart-b4c8ea92-1dc1-48f0-81d5-be2c629b4446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407870786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3407870786
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.29247304
Short name T752
Test name
Test status
Simulation time 170345054436 ps
CPU time 369.13 seconds
Started Jul 24 07:10:34 PM PDT 24
Finished Jul 24 07:16:44 PM PDT 24
Peak memory 201292 kb
Host smart-23125329-0bba-450e-89cf-96ea612b2c01
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=29247304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixed
.29247304
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.528370235
Short name T145
Test name
Test status
Simulation time 384287307078 ps
CPU time 408.06 seconds
Started Jul 24 07:10:35 PM PDT 24
Finished Jul 24 07:17:24 PM PDT 24
Peak memory 201168 kb
Host smart-18041f88-1f78-49c4-b0fa-5dc3c1a6d124
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528370235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.528370235
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1875087627
Short name T537
Test name
Test status
Simulation time 408061650670 ps
CPU time 179.08 seconds
Started Jul 24 07:10:33 PM PDT 24
Finished Jul 24 07:13:32 PM PDT 24
Peak memory 201300 kb
Host smart-da163559-fc97-4dc4-b2ee-00e7ad120d92
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875087627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1875087627
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.129633224
Short name T741
Test name
Test status
Simulation time 72057192300 ps
CPU time 384.65 seconds
Started Jul 24 07:10:37 PM PDT 24
Finished Jul 24 07:17:02 PM PDT 24
Peak memory 201664 kb
Host smart-a542b375-0df4-40f0-806e-2d45eb8b7811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129633224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.129633224
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.4145377079
Short name T558
Test name
Test status
Simulation time 28379755421 ps
CPU time 63.77 seconds
Started Jul 24 07:10:31 PM PDT 24
Finished Jul 24 07:11:35 PM PDT 24
Peak memory 201068 kb
Host smart-88e6c1db-0291-4c21-804f-24109af8f047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145377079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.4145377079
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.329261966
Short name T385
Test name
Test status
Simulation time 3454794546 ps
CPU time 4.81 seconds
Started Jul 24 07:10:42 PM PDT 24
Finished Jul 24 07:10:47 PM PDT 24
Peak memory 201048 kb
Host smart-93868eb2-2032-49d2-8611-fa078cbbb9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329261966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.329261966
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3384768596
Short name T630
Test name
Test status
Simulation time 5954837055 ps
CPU time 10.79 seconds
Started Jul 24 07:10:40 PM PDT 24
Finished Jul 24 07:10:51 PM PDT 24
Peak memory 201112 kb
Host smart-00dd71a3-6ec2-45a9-acc3-4a61976e7d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384768596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3384768596
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2844454023
Short name T152
Test name
Test status
Simulation time 206898898740 ps
CPU time 83.06 seconds
Started Jul 24 07:10:31 PM PDT 24
Finished Jul 24 07:11:54 PM PDT 24
Peak memory 201220 kb
Host smart-6bf94098-b57d-44f1-9458-f5eb15bd2b7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844454023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2844454023
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3311540901
Short name T15
Test name
Test status
Simulation time 71542180983 ps
CPU time 164.23 seconds
Started Jul 24 07:10:32 PM PDT 24
Finished Jul 24 07:13:17 PM PDT 24
Peak memory 209636 kb
Host smart-beb549e5-cc5b-446d-85bc-90b1d7c7cfff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311540901 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3311540901
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.939525207
Short name T406
Test name
Test status
Simulation time 534441391 ps
CPU time 1.28 seconds
Started Jul 24 07:10:34 PM PDT 24
Finished Jul 24 07:10:36 PM PDT 24
Peak memory 200916 kb
Host smart-e5992398-dbec-46b9-ae2f-ddd014aac634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939525207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.939525207
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3011834081
Short name T107
Test name
Test status
Simulation time 162749614314 ps
CPU time 350.79 seconds
Started Jul 24 07:10:37 PM PDT 24
Finished Jul 24 07:16:28 PM PDT 24
Peak memory 201300 kb
Host smart-6f942f36-3daa-4096-b853-fab8f8d282e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011834081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3011834081
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1263932926
Short name T641
Test name
Test status
Simulation time 489687596794 ps
CPU time 1100.12 seconds
Started Jul 24 07:10:33 PM PDT 24
Finished Jul 24 07:28:53 PM PDT 24
Peak memory 201312 kb
Host smart-63b7353f-d67c-4989-97c4-39e414b557e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263932926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1263932926
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.14411134
Short name T664
Test name
Test status
Simulation time 329388129304 ps
CPU time 739.04 seconds
Started Jul 24 07:10:33 PM PDT 24
Finished Jul 24 07:22:52 PM PDT 24
Peak memory 201288 kb
Host smart-4451a153-7000-4d94-ae40-e92c78f6e3fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=14411134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt
_fixed.14411134
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1022857602
Short name T597
Test name
Test status
Simulation time 331962840143 ps
CPU time 740.36 seconds
Started Jul 24 07:10:36 PM PDT 24
Finished Jul 24 07:22:56 PM PDT 24
Peak memory 201228 kb
Host smart-27143a5e-1d96-4924-993c-235789b05cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022857602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1022857602
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1376797816
Short name T649
Test name
Test status
Simulation time 488978364914 ps
CPU time 264.24 seconds
Started Jul 24 07:10:34 PM PDT 24
Finished Jul 24 07:14:59 PM PDT 24
Peak memory 201180 kb
Host smart-2fe043e7-c668-44d5-8d0c-93ab1f8f9f7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376797816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1376797816
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3473719793
Short name T338
Test name
Test status
Simulation time 247552437483 ps
CPU time 528.05 seconds
Started Jul 24 07:10:31 PM PDT 24
Finished Jul 24 07:19:19 PM PDT 24
Peak memory 201252 kb
Host smart-b5a474fb-5ef9-4552-afb4-a6bd2f9ac47b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473719793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3473719793
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1824068788
Short name T475
Test name
Test status
Simulation time 398663789555 ps
CPU time 821.33 seconds
Started Jul 24 07:10:35 PM PDT 24
Finished Jul 24 07:24:17 PM PDT 24
Peak memory 201288 kb
Host smart-401428bb-6532-422f-b4aa-17fc33425c12
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824068788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1824068788
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3938279834
Short name T345
Test name
Test status
Simulation time 108114538064 ps
CPU time 576.83 seconds
Started Jul 24 07:10:34 PM PDT 24
Finished Jul 24 07:20:11 PM PDT 24
Peak memory 201676 kb
Host smart-9e8a1197-a5d5-4cbc-b797-dca47678e9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938279834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3938279834
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1239333152
Short name T736
Test name
Test status
Simulation time 23299603369 ps
CPU time 50.6 seconds
Started Jul 24 07:10:34 PM PDT 24
Finished Jul 24 07:11:25 PM PDT 24
Peak memory 201084 kb
Host smart-322b02c6-7880-415c-be30-440e6c2de374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239333152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1239333152
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.704553847
Short name T356
Test name
Test status
Simulation time 4700754078 ps
CPU time 11.62 seconds
Started Jul 24 07:10:36 PM PDT 24
Finished Jul 24 07:10:47 PM PDT 24
Peak memory 201024 kb
Host smart-7a08dd96-bd23-46ca-9703-79cb3d9bc923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704553847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.704553847
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.911192685
Short name T168
Test name
Test status
Simulation time 5780996724 ps
CPU time 15.75 seconds
Started Jul 24 07:10:30 PM PDT 24
Finished Jul 24 07:10:46 PM PDT 24
Peak memory 201036 kb
Host smart-97fbbbf7-906b-4ca4-98df-4cfcd3e7bdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911192685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.911192685
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3732743023
Short name T625
Test name
Test status
Simulation time 501165195565 ps
CPU time 1487.09 seconds
Started Jul 24 07:10:33 PM PDT 24
Finished Jul 24 07:35:21 PM PDT 24
Peak memory 209880 kb
Host smart-8c9a5bfb-d767-419b-a26c-1c095ae7d4fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732743023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3732743023
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3271920443
Short name T38
Test name
Test status
Simulation time 9351585039 ps
CPU time 46.07 seconds
Started Jul 24 07:10:35 PM PDT 24
Finished Jul 24 07:11:22 PM PDT 24
Peak memory 209976 kb
Host smart-33ef19a3-2a7b-459d-97b9-020aae3aa2bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271920443 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3271920443
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.418054565
Short name T508
Test name
Test status
Simulation time 532801139 ps
CPU time 1.24 seconds
Started Jul 24 07:10:41 PM PDT 24
Finished Jul 24 07:10:42 PM PDT 24
Peak memory 200924 kb
Host smart-5b639a86-603f-441d-8d63-56ae96b499a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418054565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.418054565
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.438066225
Short name T715
Test name
Test status
Simulation time 332747759853 ps
CPU time 418.36 seconds
Started Jul 24 07:10:34 PM PDT 24
Finished Jul 24 07:17:33 PM PDT 24
Peak memory 201308 kb
Host smart-0afcd940-f304-40a7-a9a6-41890bdeb70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438066225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.438066225
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3237574766
Short name T586
Test name
Test status
Simulation time 324145835131 ps
CPU time 709.77 seconds
Started Jul 24 07:10:35 PM PDT 24
Finished Jul 24 07:22:25 PM PDT 24
Peak memory 201224 kb
Host smart-7eeeeecd-e2e6-4969-a76b-cbc6ef5503c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237574766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3237574766
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2415680451
Short name T108
Test name
Test status
Simulation time 488080402390 ps
CPU time 313.28 seconds
Started Jul 24 07:10:32 PM PDT 24
Finished Jul 24 07:15:46 PM PDT 24
Peak memory 201176 kb
Host smart-42563201-1441-4313-9704-90c33e168ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415680451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2415680451
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3261234079
Short name T505
Test name
Test status
Simulation time 162569727578 ps
CPU time 190.31 seconds
Started Jul 24 07:10:35 PM PDT 24
Finished Jul 24 07:13:46 PM PDT 24
Peak memory 201260 kb
Host smart-e49da714-6674-4358-bb0a-6612f18d47c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261234079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3261234079
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1886645482
Short name T275
Test name
Test status
Simulation time 370450228600 ps
CPU time 831.15 seconds
Started Jul 24 07:10:36 PM PDT 24
Finished Jul 24 07:24:27 PM PDT 24
Peak memory 201192 kb
Host smart-5f3251ab-387c-4553-a9aa-402bd9f2b73a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886645482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1886645482
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1718382527
Short name T434
Test name
Test status
Simulation time 594976542497 ps
CPU time 671.86 seconds
Started Jul 24 07:10:37 PM PDT 24
Finished Jul 24 07:21:49 PM PDT 24
Peak memory 201348 kb
Host smart-42aaf124-77b8-4e8a-8425-05db76e4b83b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718382527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1718382527
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1194569381
Short name T45
Test name
Test status
Simulation time 23883433855 ps
CPU time 12.95 seconds
Started Jul 24 07:10:37 PM PDT 24
Finished Jul 24 07:10:50 PM PDT 24
Peak memory 201032 kb
Host smart-712ec965-9d50-45e7-b368-f90e486994b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194569381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1194569381
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.266908608
Short name T489
Test name
Test status
Simulation time 3933237470 ps
CPU time 1.22 seconds
Started Jul 24 07:10:39 PM PDT 24
Finished Jul 24 07:10:40 PM PDT 24
Peak memory 201140 kb
Host smart-2ebf59f7-721d-456e-9ef8-94fd74a9e28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266908608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.266908608
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3640446232
Short name T470
Test name
Test status
Simulation time 5680760321 ps
CPU time 14.4 seconds
Started Jul 24 07:10:34 PM PDT 24
Finished Jul 24 07:10:48 PM PDT 24
Peak memory 201132 kb
Host smart-b781b78d-835b-4980-85b9-6f0e79eeede5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640446232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3640446232
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3676080414
Short name T23
Test name
Test status
Simulation time 101136735548 ps
CPU time 63.13 seconds
Started Jul 24 07:10:35 PM PDT 24
Finished Jul 24 07:11:39 PM PDT 24
Peak memory 209608 kb
Host smart-d6df4085-9ea7-4947-a3f5-23d762b87483
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676080414 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3676080414
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1318210141
Short name T456
Test name
Test status
Simulation time 476255412 ps
CPU time 1.67 seconds
Started Jul 24 07:10:40 PM PDT 24
Finished Jul 24 07:10:42 PM PDT 24
Peak memory 200984 kb
Host smart-e72d106d-be8b-45d2-83f9-c2a23393fb6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318210141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1318210141
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1251573312
Short name T150
Test name
Test status
Simulation time 175317504108 ps
CPU time 418.82 seconds
Started Jul 24 07:10:41 PM PDT 24
Finished Jul 24 07:17:40 PM PDT 24
Peak memory 201260 kb
Host smart-fc7995d9-ddc4-4e86-b59f-21247b7408cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251573312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1251573312
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1440740796
Short name T618
Test name
Test status
Simulation time 165214965631 ps
CPU time 411.78 seconds
Started Jul 24 07:10:45 PM PDT 24
Finished Jul 24 07:17:37 PM PDT 24
Peak memory 201324 kb
Host smart-0c447b3a-186c-4b0c-9fe9-b3bdc7926a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440740796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1440740796
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.4252346037
Short name T256
Test name
Test status
Simulation time 164902378807 ps
CPU time 96.87 seconds
Started Jul 24 07:10:44 PM PDT 24
Finished Jul 24 07:12:21 PM PDT 24
Peak memory 201316 kb
Host smart-e29e1f1c-4cf3-48d7-837c-5306f37b7f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252346037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4252346037
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3329965373
Short name T423
Test name
Test status
Simulation time 497784402632 ps
CPU time 1153.57 seconds
Started Jul 24 07:10:41 PM PDT 24
Finished Jul 24 07:29:55 PM PDT 24
Peak memory 201272 kb
Host smart-ceabe534-98f8-4125-a962-5d70450c4223
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329965373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3329965373
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3614513553
Short name T138
Test name
Test status
Simulation time 487817038655 ps
CPU time 283.23 seconds
Started Jul 24 07:10:42 PM PDT 24
Finished Jul 24 07:15:25 PM PDT 24
Peak memory 201252 kb
Host smart-fd9438d5-2e69-4864-8123-87003d139010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614513553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3614513553
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1392531625
Short name T550
Test name
Test status
Simulation time 487048682847 ps
CPU time 1132.57 seconds
Started Jul 24 07:10:38 PM PDT 24
Finished Jul 24 07:29:31 PM PDT 24
Peak memory 201272 kb
Host smart-bbf46790-1bba-4d00-88f4-7a3ec49c97e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392531625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1392531625
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3722685256
Short name T27
Test name
Test status
Simulation time 231747008241 ps
CPU time 130.38 seconds
Started Jul 24 07:10:44 PM PDT 24
Finished Jul 24 07:12:54 PM PDT 24
Peak memory 201236 kb
Host smart-7c0eeb98-bff8-4534-93e0-6fa08dd618b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722685256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3722685256
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.578867010
Short name T407
Test name
Test status
Simulation time 594564648346 ps
CPU time 96.58 seconds
Started Jul 24 07:10:45 PM PDT 24
Finished Jul 24 07:12:22 PM PDT 24
Peak memory 201240 kb
Host smart-a475da34-48d3-4c91-ae13-65315339485f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578867010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.578867010
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2261668792
Short name T46
Test name
Test status
Simulation time 74173845440 ps
CPU time 337.65 seconds
Started Jul 24 07:10:40 PM PDT 24
Finished Jul 24 07:16:18 PM PDT 24
Peak memory 201676 kb
Host smart-e792cbbb-3ac0-484f-9d56-a83f7b7f542b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261668792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2261668792
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1135473275
Short name T93
Test name
Test status
Simulation time 30749439985 ps
CPU time 66.57 seconds
Started Jul 24 07:10:40 PM PDT 24
Finished Jul 24 07:11:47 PM PDT 24
Peak memory 201108 kb
Host smart-4ed93bd7-a248-45a9-b4c8-ef3ff1076f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135473275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1135473275
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.4105429364
Short name T105
Test name
Test status
Simulation time 5442283798 ps
CPU time 13.28 seconds
Started Jul 24 07:10:46 PM PDT 24
Finished Jul 24 07:11:00 PM PDT 24
Peak memory 201080 kb
Host smart-de7aad42-ba0f-425d-9a0f-c0d7c6e53839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105429364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.4105429364
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3144073795
Short name T435
Test name
Test status
Simulation time 6168957910 ps
CPU time 14.73 seconds
Started Jul 24 07:10:42 PM PDT 24
Finished Jul 24 07:10:57 PM PDT 24
Peak memory 201152 kb
Host smart-5b15a4df-c474-4b3f-a502-c8c29566f18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144073795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3144073795
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3922807370
Short name T154
Test name
Test status
Simulation time 362154053158 ps
CPU time 738.64 seconds
Started Jul 24 07:10:44 PM PDT 24
Finished Jul 24 07:23:03 PM PDT 24
Peak memory 213084 kb
Host smart-b48775d9-8bee-47ec-bd78-f97d69e643af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922807370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3922807370
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.197756391
Short name T18
Test name
Test status
Simulation time 26089610861 ps
CPU time 72.72 seconds
Started Jul 24 07:10:39 PM PDT 24
Finished Jul 24 07:11:52 PM PDT 24
Peak memory 210096 kb
Host smart-d632c291-5d8a-407e-a56e-8ea99b9df720
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197756391 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.197756391
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2149969229
Short name T91
Test name
Test status
Simulation time 516157702 ps
CPU time 0.71 seconds
Started Jul 24 07:10:50 PM PDT 24
Finished Jul 24 07:10:50 PM PDT 24
Peak memory 201044 kb
Host smart-b2edb23b-49ee-4ac6-8096-8fadfafce71c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149969229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2149969229
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1412754095
Short name T701
Test name
Test status
Simulation time 169030342929 ps
CPU time 7.97 seconds
Started Jul 24 07:10:49 PM PDT 24
Finished Jul 24 07:10:57 PM PDT 24
Peak memory 201268 kb
Host smart-b77e7cf1-a0aa-4a7a-a9e5-4993d89bc797
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412754095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1412754095
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3118315839
Short name T149
Test name
Test status
Simulation time 501591696439 ps
CPU time 97.58 seconds
Started Jul 24 07:10:41 PM PDT 24
Finished Jul 24 07:12:19 PM PDT 24
Peak memory 201208 kb
Host smart-c07743ef-d3fb-4c4b-b3f0-fa57231e8307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118315839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3118315839
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2314951231
Short name T637
Test name
Test status
Simulation time 161227655439 ps
CPU time 382.03 seconds
Started Jul 24 07:10:45 PM PDT 24
Finished Jul 24 07:17:08 PM PDT 24
Peak memory 201312 kb
Host smart-296f7037-5b68-4e54-895a-e4112f0903ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314951231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2314951231
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2519435398
Short name T163
Test name
Test status
Simulation time 323332533528 ps
CPU time 102.12 seconds
Started Jul 24 07:10:43 PM PDT 24
Finished Jul 24 07:12:25 PM PDT 24
Peak memory 201232 kb
Host smart-59811568-b91c-4fda-a5b8-b6ae5fcca0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519435398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2519435398
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3399457064
Short name T674
Test name
Test status
Simulation time 329863735328 ps
CPU time 200.36 seconds
Started Jul 24 07:10:43 PM PDT 24
Finished Jul 24 07:14:04 PM PDT 24
Peak memory 201232 kb
Host smart-aea84aa2-0bc4-41b9-b0cb-1e965a293944
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399457064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3399457064
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3415392610
Short name T478
Test name
Test status
Simulation time 405624879936 ps
CPU time 909.99 seconds
Started Jul 24 07:10:41 PM PDT 24
Finished Jul 24 07:25:51 PM PDT 24
Peak memory 201180 kb
Host smart-159a8c91-8ff3-47d1-94aa-2cc31cec3d32
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415392610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3415392610
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2613089092
Short name T702
Test name
Test status
Simulation time 99854112476 ps
CPU time 481.55 seconds
Started Jul 24 07:10:51 PM PDT 24
Finished Jul 24 07:18:53 PM PDT 24
Peak memory 201692 kb
Host smart-fe0f9513-3121-41f1-81ef-6e1d16da2f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613089092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2613089092
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2289561959
Short name T623
Test name
Test status
Simulation time 33575215239 ps
CPU time 77.75 seconds
Started Jul 24 07:10:55 PM PDT 24
Finished Jul 24 07:12:13 PM PDT 24
Peak memory 201076 kb
Host smart-735836ec-3e09-431c-832e-87ea273bbfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289561959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2289561959
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.828807036
Short name T560
Test name
Test status
Simulation time 3711021073 ps
CPU time 1.74 seconds
Started Jul 24 07:10:47 PM PDT 24
Finished Jul 24 07:10:49 PM PDT 24
Peak memory 201052 kb
Host smart-904276b9-0e4f-48d1-9498-c0b21b169a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828807036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.828807036
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1628462035
Short name T440
Test name
Test status
Simulation time 5979350874 ps
CPU time 15.56 seconds
Started Jul 24 07:10:44 PM PDT 24
Finished Jul 24 07:11:00 PM PDT 24
Peak memory 201116 kb
Host smart-e8cf168e-ba6c-4cbc-a397-efbf7a43af73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628462035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1628462035
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.735602852
Short name T712
Test name
Test status
Simulation time 367019602888 ps
CPU time 253.13 seconds
Started Jul 24 07:10:46 PM PDT 24
Finished Jul 24 07:15:00 PM PDT 24
Peak memory 201220 kb
Host smart-3f4e840c-932e-469c-b930-40e5a6382720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735602852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
735602852
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3810203223
Short name T249
Test name
Test status
Simulation time 218672226979 ps
CPU time 180.72 seconds
Started Jul 24 07:10:47 PM PDT 24
Finished Jul 24 07:13:48 PM PDT 24
Peak memory 210072 kb
Host smart-68058fa9-ef18-4ab1-8080-5ffb88f14877
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810203223 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3810203223
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2083142323
Short name T677
Test name
Test status
Simulation time 161803472886 ps
CPU time 88.31 seconds
Started Jul 24 07:10:49 PM PDT 24
Finished Jul 24 07:12:18 PM PDT 24
Peak memory 201296 kb
Host smart-1ffa2fd6-b0ab-4e2b-acde-29a8bd8445ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083142323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2083142323
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1871571417
Short name T155
Test name
Test status
Simulation time 495507701481 ps
CPU time 127.57 seconds
Started Jul 24 07:10:47 PM PDT 24
Finished Jul 24 07:12:54 PM PDT 24
Peak memory 201340 kb
Host smart-f6ffabdc-6520-43d7-a7cd-e704f827f795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871571417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1871571417
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1373972431
Short name T608
Test name
Test status
Simulation time 330814544723 ps
CPU time 769.99 seconds
Started Jul 24 07:10:48 PM PDT 24
Finished Jul 24 07:23:38 PM PDT 24
Peak memory 201280 kb
Host smart-b631674b-d37d-46fa-89be-7d9d4d605a14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373972431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1373972431
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2810640006
Short name T308
Test name
Test status
Simulation time 494754586727 ps
CPU time 298.54 seconds
Started Jul 24 07:10:49 PM PDT 24
Finished Jul 24 07:15:48 PM PDT 24
Peak memory 201300 kb
Host smart-da3c95a2-b0ad-4673-a2bc-fbf6969c60dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810640006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2810640006
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.400738272
Short name T24
Test name
Test status
Simulation time 322307677270 ps
CPU time 756.72 seconds
Started Jul 24 07:10:47 PM PDT 24
Finished Jul 24 07:23:24 PM PDT 24
Peak memory 201236 kb
Host smart-9bc4e78f-1e4b-44ee-b759-d117778dfb0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=400738272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.400738272
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1208213616
Short name T243
Test name
Test status
Simulation time 189621640614 ps
CPU time 227.96 seconds
Started Jul 24 07:10:46 PM PDT 24
Finished Jul 24 07:14:34 PM PDT 24
Peak memory 201264 kb
Host smart-566429e0-2f81-4af7-a718-629e78ff4c37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208213616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1208213616
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3078393462
Short name T643
Test name
Test status
Simulation time 204232452200 ps
CPU time 221.77 seconds
Started Jul 24 07:10:48 PM PDT 24
Finished Jul 24 07:14:30 PM PDT 24
Peak memory 201180 kb
Host smart-fa4b8a29-8bc6-4cca-a3d8-ce2da8a19638
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078393462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3078393462
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1743867693
Short name T699
Test name
Test status
Simulation time 91976239020 ps
CPU time 389.03 seconds
Started Jul 24 07:10:48 PM PDT 24
Finished Jul 24 07:17:17 PM PDT 24
Peak memory 201764 kb
Host smart-a226c5fa-a474-4ef9-acc2-a55d7e6cf0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743867693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1743867693
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.4121351588
Short name T499
Test name
Test status
Simulation time 29683814988 ps
CPU time 20.42 seconds
Started Jul 24 07:10:48 PM PDT 24
Finished Jul 24 07:11:09 PM PDT 24
Peak memory 201096 kb
Host smart-d37020d2-309d-4f74-91b3-59dba83d0c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121351588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.4121351588
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2148278033
Short name T567
Test name
Test status
Simulation time 2807829072 ps
CPU time 2.45 seconds
Started Jul 24 07:10:49 PM PDT 24
Finished Jul 24 07:10:51 PM PDT 24
Peak memory 201080 kb
Host smart-02a19f09-deb3-4574-9004-d24b771b1c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148278033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2148278033
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1242250306
Short name T445
Test name
Test status
Simulation time 5708821103 ps
CPU time 7.35 seconds
Started Jul 24 07:10:49 PM PDT 24
Finished Jul 24 07:10:57 PM PDT 24
Peak memory 201132 kb
Host smart-b70f05b2-eec4-425b-87a3-7e0ee5140d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242250306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1242250306
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.4272400580
Short name T777
Test name
Test status
Simulation time 195325379519 ps
CPU time 1031.7 seconds
Started Jul 24 07:10:57 PM PDT 24
Finished Jul 24 07:28:09 PM PDT 24
Peak memory 201800 kb
Host smart-d7baf0c8-9c8c-44a4-bff9-466aee09bac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272400580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.4272400580
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.755360260
Short name T26
Test name
Test status
Simulation time 48653560117 ps
CPU time 125.45 seconds
Started Jul 24 07:10:55 PM PDT 24
Finished Jul 24 07:13:00 PM PDT 24
Peak memory 211068 kb
Host smart-36103948-d8d0-4de3-a5db-5852167b20ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755360260 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.755360260
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1143758509
Short name T422
Test name
Test status
Simulation time 384732005 ps
CPU time 1.31 seconds
Started Jul 24 07:10:04 PM PDT 24
Finished Jul 24 07:10:06 PM PDT 24
Peak memory 201032 kb
Host smart-67ab4933-07d7-413c-a537-9f8fa67c6539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143758509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1143758509
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2582488603
Short name T557
Test name
Test status
Simulation time 165417957548 ps
CPU time 232.57 seconds
Started Jul 24 07:10:06 PM PDT 24
Finished Jul 24 07:13:59 PM PDT 24
Peak memory 201196 kb
Host smart-5d01163d-f5b6-439c-8f0c-a79225ef73ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582488603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2582488603
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3806769399
Short name T262
Test name
Test status
Simulation time 335485999988 ps
CPU time 204.92 seconds
Started Jul 24 07:10:05 PM PDT 24
Finished Jul 24 07:13:31 PM PDT 24
Peak memory 201264 kb
Host smart-ffe34325-5350-4059-a442-06a61f04b8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806769399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3806769399
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3239052703
Short name T727
Test name
Test status
Simulation time 161625510028 ps
CPU time 370.99 seconds
Started Jul 24 07:10:07 PM PDT 24
Finished Jul 24 07:16:18 PM PDT 24
Peak memory 201304 kb
Host smart-ef8168e0-5028-4bb6-b8df-8a03b1e9a629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239052703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3239052703
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1100612782
Short name T720
Test name
Test status
Simulation time 161312718325 ps
CPU time 33.37 seconds
Started Jul 24 07:10:05 PM PDT 24
Finished Jul 24 07:10:38 PM PDT 24
Peak memory 201236 kb
Host smart-b77437ce-d1da-4d3b-b2a7-9fe358ae9426
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100612782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1100612782
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.925516032
Short name T317
Test name
Test status
Simulation time 492507919837 ps
CPU time 1056.15 seconds
Started Jul 24 07:10:00 PM PDT 24
Finished Jul 24 07:27:37 PM PDT 24
Peak memory 201408 kb
Host smart-400fc16a-98f6-4997-9735-01deb2bd6886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925516032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.925516032
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3081648004
Short name T661
Test name
Test status
Simulation time 165139295500 ps
CPU time 374.42 seconds
Started Jul 24 07:10:06 PM PDT 24
Finished Jul 24 07:16:21 PM PDT 24
Peak memory 201244 kb
Host smart-ca2f3ce3-4ffa-4bee-bb43-cb8195d3500b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081648004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3081648004
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.4050733561
Short name T279
Test name
Test status
Simulation time 178419066558 ps
CPU time 416.02 seconds
Started Jul 24 07:10:02 PM PDT 24
Finished Jul 24 07:16:59 PM PDT 24
Peak memory 201248 kb
Host smart-3d35d66a-5297-4741-9e68-c11cd5353305
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050733561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.4050733561
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.237153144
Short name T496
Test name
Test status
Simulation time 195510673657 ps
CPU time 122.08 seconds
Started Jul 24 07:10:12 PM PDT 24
Finished Jul 24 07:12:14 PM PDT 24
Peak memory 201216 kb
Host smart-571e0731-f4c2-4203-869f-522d2036afd6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237153144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.237153144
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1726380624
Short name T751
Test name
Test status
Simulation time 112747772480 ps
CPU time 527.61 seconds
Started Jul 24 07:10:09 PM PDT 24
Finished Jul 24 07:18:57 PM PDT 24
Peak memory 201760 kb
Host smart-0d49112a-bf71-4531-b424-921d877eb952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726380624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1726380624
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.122397491
Short name T654
Test name
Test status
Simulation time 43685161698 ps
CPU time 106.14 seconds
Started Jul 24 07:10:04 PM PDT 24
Finished Jul 24 07:11:50 PM PDT 24
Peak memory 201080 kb
Host smart-002490bd-6a36-40dc-8800-49e24dc09583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122397491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.122397491
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3294445702
Short name T647
Test name
Test status
Simulation time 3677145332 ps
CPU time 9.57 seconds
Started Jul 24 07:10:05 PM PDT 24
Finished Jul 24 07:10:15 PM PDT 24
Peak memory 201020 kb
Host smart-a49c59ee-7977-4844-98a3-4e8462a90758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294445702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3294445702
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.4062096909
Short name T60
Test name
Test status
Simulation time 4349819417 ps
CPU time 10.82 seconds
Started Jul 24 07:10:12 PM PDT 24
Finished Jul 24 07:10:23 PM PDT 24
Peak memory 216892 kb
Host smart-c788663e-a140-4478-aa9a-e7e088904bbf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062096909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.4062096909
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.4240177809
Short name T539
Test name
Test status
Simulation time 5923032762 ps
CPU time 14.74 seconds
Started Jul 24 07:10:00 PM PDT 24
Finished Jul 24 07:10:15 PM PDT 24
Peak memory 201260 kb
Host smart-a69fbe03-2e64-4c4e-a05b-4e1d2422b953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240177809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.4240177809
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3193609084
Short name T743
Test name
Test status
Simulation time 272731498622 ps
CPU time 577.22 seconds
Started Jul 24 07:10:14 PM PDT 24
Finished Jul 24 07:19:52 PM PDT 24
Peak memory 209900 kb
Host smart-35b2176e-0aeb-4fa9-8b1a-7fac11cb935d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193609084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3193609084
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.794228264
Short name T330
Test name
Test status
Simulation time 24271366399 ps
CPU time 54.53 seconds
Started Jul 24 07:10:07 PM PDT 24
Finished Jul 24 07:11:02 PM PDT 24
Peak memory 201412 kb
Host smart-b7a65eed-351f-4bbe-9fbd-29ee2fdd9818
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794228264 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.794228264
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2463148649
Short name T758
Test name
Test status
Simulation time 504507337 ps
CPU time 1.77 seconds
Started Jul 24 07:10:54 PM PDT 24
Finished Jul 24 07:10:56 PM PDT 24
Peak memory 201072 kb
Host smart-bf66766e-162c-4a19-bbd4-921bf6ff6cc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463148649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2463148649
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1401465024
Short name T497
Test name
Test status
Simulation time 166046609598 ps
CPU time 99.35 seconds
Started Jul 24 07:10:52 PM PDT 24
Finished Jul 24 07:12:31 PM PDT 24
Peak memory 201216 kb
Host smart-10ed883c-2eb6-4e2e-b476-fdaf8b53ebbe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401465024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1401465024
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3419773515
Short name T305
Test name
Test status
Simulation time 175017596743 ps
CPU time 199.25 seconds
Started Jul 24 07:10:54 PM PDT 24
Finished Jul 24 07:14:13 PM PDT 24
Peak memory 201268 kb
Host smart-76cc77f9-17e6-4443-a12e-92f40255d205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419773515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3419773515
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1445477502
Short name T327
Test name
Test status
Simulation time 482144639501 ps
CPU time 1127.84 seconds
Started Jul 24 07:10:54 PM PDT 24
Finished Jul 24 07:29:42 PM PDT 24
Peak memory 201152 kb
Host smart-e0644424-4ffa-43dd-a2dd-18e76d29f9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445477502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1445477502
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.632703612
Short name T791
Test name
Test status
Simulation time 331216925151 ps
CPU time 813.69 seconds
Started Jul 24 07:10:53 PM PDT 24
Finished Jul 24 07:24:27 PM PDT 24
Peak memory 201184 kb
Host smart-c66f1873-7e7a-49e4-bcea-26d45858af14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=632703612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.632703612
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.448901686
Short name T174
Test name
Test status
Simulation time 335138773067 ps
CPU time 104.38 seconds
Started Jul 24 07:10:54 PM PDT 24
Finished Jul 24 07:12:38 PM PDT 24
Peak memory 201216 kb
Host smart-1c064678-4b34-4c37-863f-6f7c44befef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448901686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.448901686
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1530850889
Short name T167
Test name
Test status
Simulation time 501644810755 ps
CPU time 1198.59 seconds
Started Jul 24 07:10:55 PM PDT 24
Finished Jul 24 07:30:54 PM PDT 24
Peak memory 201220 kb
Host smart-ff603ce2-4a60-49db-a0e5-c1e105ea8742
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530850889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1530850889
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2584973531
Short name T762
Test name
Test status
Simulation time 521598202419 ps
CPU time 1184.2 seconds
Started Jul 24 07:10:54 PM PDT 24
Finished Jul 24 07:30:38 PM PDT 24
Peak memory 201296 kb
Host smart-9c209a9f-67c3-496b-8351-f36fcbac780f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584973531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2584973531
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.526075397
Short name T498
Test name
Test status
Simulation time 200546247963 ps
CPU time 126.11 seconds
Started Jul 24 07:10:54 PM PDT 24
Finished Jul 24 07:13:00 PM PDT 24
Peak memory 201256 kb
Host smart-04d713fd-b78c-434a-8340-c67f5a4b35fe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526075397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.526075397
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1342648130
Short name T191
Test name
Test status
Simulation time 82838175437 ps
CPU time 438.92 seconds
Started Jul 24 07:10:55 PM PDT 24
Finished Jul 24 07:18:14 PM PDT 24
Peak memory 201744 kb
Host smart-a5ff3c2e-4205-4b19-bd83-269eab592330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342648130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1342648130
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1275660008
Short name T685
Test name
Test status
Simulation time 41384634980 ps
CPU time 59.68 seconds
Started Jul 24 07:10:56 PM PDT 24
Finished Jul 24 07:11:56 PM PDT 24
Peak memory 201128 kb
Host smart-cd9fa3f3-a379-454b-9846-b6bdc20ad7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275660008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1275660008
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1986401314
Short name T432
Test name
Test status
Simulation time 4872436497 ps
CPU time 12.17 seconds
Started Jul 24 07:10:54 PM PDT 24
Finished Jul 24 07:11:06 PM PDT 24
Peak memory 200980 kb
Host smart-96c362d9-f2d6-4585-be84-4a1e37551734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986401314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1986401314
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1468861582
Short name T526
Test name
Test status
Simulation time 5746979587 ps
CPU time 14.54 seconds
Started Jul 24 07:10:53 PM PDT 24
Finished Jul 24 07:11:08 PM PDT 24
Peak memory 201116 kb
Host smart-01e104fe-b411-4cc3-ad9f-c62750acf8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468861582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1468861582
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3693302763
Short name T350
Test name
Test status
Simulation time 287078183393 ps
CPU time 510.96 seconds
Started Jul 24 07:10:57 PM PDT 24
Finished Jul 24 07:19:28 PM PDT 24
Peak memory 201656 kb
Host smart-48c85126-ecd5-4b81-963e-4d67586a9688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693302763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3693302763
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.4264690602
Short name T672
Test name
Test status
Simulation time 529093578 ps
CPU time 0.91 seconds
Started Jul 24 07:11:08 PM PDT 24
Finished Jul 24 07:11:09 PM PDT 24
Peak memory 201024 kb
Host smart-63681003-49d2-4357-ab72-cc6995aa2958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264690602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.4264690602
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1882798998
Short name T220
Test name
Test status
Simulation time 160874720059 ps
CPU time 367.26 seconds
Started Jul 24 07:10:58 PM PDT 24
Finished Jul 24 07:17:06 PM PDT 24
Peak memory 201208 kb
Host smart-fff8fe9d-058c-40d9-9152-a9934cbf9345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882798998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1882798998
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2393398185
Short name T572
Test name
Test status
Simulation time 163930023781 ps
CPU time 368.29 seconds
Started Jul 24 07:11:00 PM PDT 24
Finished Jul 24 07:17:08 PM PDT 24
Peak memory 201248 kb
Host smart-e7df7e0c-20c5-4c62-a759-ef18776033ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393398185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2393398185
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.690153191
Short name T164
Test name
Test status
Simulation time 324361989809 ps
CPU time 103.49 seconds
Started Jul 24 07:11:01 PM PDT 24
Finished Jul 24 07:12:45 PM PDT 24
Peak memory 201228 kb
Host smart-ef31b7ac-b75b-4952-8cb7-7f514eff116a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690153191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.690153191
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3233996436
Short name T466
Test name
Test status
Simulation time 331571458973 ps
CPU time 159.19 seconds
Started Jul 24 07:10:59 PM PDT 24
Finished Jul 24 07:13:39 PM PDT 24
Peak memory 201180 kb
Host smart-009af39f-3bde-4658-a7fa-e05aac646f9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233996436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3233996436
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2898970469
Short name T8
Test name
Test status
Simulation time 597182300158 ps
CPU time 1468.14 seconds
Started Jul 24 07:10:58 PM PDT 24
Finished Jul 24 07:35:27 PM PDT 24
Peak memory 201216 kb
Host smart-59d64b50-30d3-466c-bdd6-6f383dc7ddb1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898970469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2898970469
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2266031133
Short name T451
Test name
Test status
Simulation time 607670234772 ps
CPU time 128.33 seconds
Started Jul 24 07:10:59 PM PDT 24
Finished Jul 24 07:13:08 PM PDT 24
Peak memory 201212 kb
Host smart-c7ee67ac-0294-4b96-9a2a-6ede24343147
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266031133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2266031133
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3240236859
Short name T348
Test name
Test status
Simulation time 127752220364 ps
CPU time 659.97 seconds
Started Jul 24 07:11:02 PM PDT 24
Finished Jul 24 07:22:02 PM PDT 24
Peak memory 201808 kb
Host smart-795ebbc5-1e6c-4448-bfef-f1d06a678473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240236859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3240236859
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3494134612
Short name T771
Test name
Test status
Simulation time 36423961335 ps
CPU time 82.72 seconds
Started Jul 24 07:10:56 PM PDT 24
Finished Jul 24 07:12:19 PM PDT 24
Peak memory 200980 kb
Host smart-20cf8d67-1baa-445a-ad98-683ad68ecc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494134612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3494134612
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2496534427
Short name T728
Test name
Test status
Simulation time 5093689677 ps
CPU time 7.87 seconds
Started Jul 24 07:10:58 PM PDT 24
Finished Jul 24 07:11:06 PM PDT 24
Peak memory 201076 kb
Host smart-e5a5a515-d02f-45cd-8682-a27ea1ff450c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496534427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2496534427
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.514202549
Short name T645
Test name
Test status
Simulation time 6071791289 ps
CPU time 7.62 seconds
Started Jul 24 07:10:53 PM PDT 24
Finished Jul 24 07:11:01 PM PDT 24
Peak memory 201072 kb
Host smart-6dd38f1c-db1e-4181-a2c4-ff7ad147142b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514202549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.514202549
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3729035153
Short name T201
Test name
Test status
Simulation time 179262904391 ps
CPU time 139.99 seconds
Started Jul 24 07:11:06 PM PDT 24
Finished Jul 24 07:13:27 PM PDT 24
Peak memory 201244 kb
Host smart-c4dd09ec-b5e4-4dbd-b82b-959adcf9ef12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729035153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3729035153
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2816558137
Short name T58
Test name
Test status
Simulation time 264149228396 ps
CPU time 186.9 seconds
Started Jul 24 07:11:05 PM PDT 24
Finished Jul 24 07:14:12 PM PDT 24
Peak memory 209976 kb
Host smart-54dc5728-9f66-404c-891b-7b5b43604d25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816558137 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2816558137
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2433884405
Short name T352
Test name
Test status
Simulation time 497506811 ps
CPU time 0.84 seconds
Started Jul 24 07:11:12 PM PDT 24
Finished Jul 24 07:11:13 PM PDT 24
Peak memory 201004 kb
Host smart-00202746-449e-4ca9-8d20-45130a191c48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433884405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2433884405
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3127443044
Short name T274
Test name
Test status
Simulation time 325455745514 ps
CPU time 91.99 seconds
Started Jul 24 07:11:10 PM PDT 24
Finished Jul 24 07:12:42 PM PDT 24
Peak memory 201224 kb
Host smart-9b7a7a69-a647-4718-9b33-66fe93854cb1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127443044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3127443044
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1493643725
Short name T251
Test name
Test status
Simulation time 165143479877 ps
CPU time 95.31 seconds
Started Jul 24 07:11:05 PM PDT 24
Finished Jul 24 07:12:41 PM PDT 24
Peak memory 201216 kb
Host smart-4d6338d2-824c-49a6-aef1-a099495f6d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493643725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1493643725
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1210884903
Short name T638
Test name
Test status
Simulation time 327449772430 ps
CPU time 195.05 seconds
Started Jul 24 07:11:09 PM PDT 24
Finished Jul 24 07:14:24 PM PDT 24
Peak memory 201220 kb
Host smart-79094690-33e6-4751-8a6b-9716fa51e5b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210884903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1210884903
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1421617055
Short name T297
Test name
Test status
Simulation time 165477399473 ps
CPU time 390.31 seconds
Started Jul 24 07:11:06 PM PDT 24
Finished Jul 24 07:17:37 PM PDT 24
Peak memory 201248 kb
Host smart-d0eaeb03-6771-4a78-a686-fb7cd354bcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421617055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1421617055
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1459955115
Short name T788
Test name
Test status
Simulation time 490002861611 ps
CPU time 202.37 seconds
Started Jul 24 07:11:07 PM PDT 24
Finished Jul 24 07:14:29 PM PDT 24
Peak memory 201272 kb
Host smart-fbfc9935-4bd0-42a2-8127-0b8db164bd70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459955115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1459955115
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.4186553299
Short name T449
Test name
Test status
Simulation time 203884926272 ps
CPU time 111.89 seconds
Started Jul 24 07:11:06 PM PDT 24
Finished Jul 24 07:12:58 PM PDT 24
Peak memory 201236 kb
Host smart-b5a09763-f412-4cc8-a947-469b368e4a2f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186553299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.4186553299
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3956048202
Short name T402
Test name
Test status
Simulation time 103592982953 ps
CPU time 348.75 seconds
Started Jul 24 07:11:13 PM PDT 24
Finished Jul 24 07:17:02 PM PDT 24
Peak memory 201736 kb
Host smart-110a695d-3188-4857-8dc6-c5138577dc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956048202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3956048202
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.4186877727
Short name T389
Test name
Test status
Simulation time 32606222539 ps
CPU time 14.94 seconds
Started Jul 24 07:11:06 PM PDT 24
Finished Jul 24 07:11:21 PM PDT 24
Peak memory 201084 kb
Host smart-95e7955d-efbf-4ea3-9a15-fbc726690359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186877727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.4186877727
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2327413993
Short name T170
Test name
Test status
Simulation time 4780567232 ps
CPU time 6.54 seconds
Started Jul 24 07:11:10 PM PDT 24
Finished Jul 24 07:11:17 PM PDT 24
Peak memory 201084 kb
Host smart-d80bb42e-39f9-4229-8280-0b8b6c1a8b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327413993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2327413993
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2065119663
Short name T483
Test name
Test status
Simulation time 5702284759 ps
CPU time 2.16 seconds
Started Jul 24 07:11:06 PM PDT 24
Finished Jul 24 07:11:08 PM PDT 24
Peak memory 201096 kb
Host smart-a4006159-152f-4a25-80a1-9670bac076c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065119663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2065119663
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2062131593
Short name T187
Test name
Test status
Simulation time 31000786462 ps
CPU time 73.18 seconds
Started Jul 24 07:11:13 PM PDT 24
Finished Jul 24 07:12:26 PM PDT 24
Peak memory 201104 kb
Host smart-b0149e48-41ee-4fec-b4e8-8aaf96cde33e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062131593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2062131593
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.636264946
Short name T209
Test name
Test status
Simulation time 246676525562 ps
CPU time 119.23 seconds
Started Jul 24 07:11:12 PM PDT 24
Finished Jul 24 07:13:11 PM PDT 24
Peak memory 209620 kb
Host smart-dc866315-3d8f-480b-a25a-f69b45355d65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636264946 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.636264946
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3064473412
Short name T528
Test name
Test status
Simulation time 435674543 ps
CPU time 1.68 seconds
Started Jul 24 07:11:17 PM PDT 24
Finished Jul 24 07:11:19 PM PDT 24
Peak memory 200916 kb
Host smart-50b2c823-38d8-4f4d-97df-72a6ca32cc41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064473412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3064473412
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2249888490
Short name T604
Test name
Test status
Simulation time 220799196791 ps
CPU time 127.19 seconds
Started Jul 24 07:11:10 PM PDT 24
Finished Jul 24 07:13:17 PM PDT 24
Peak memory 201236 kb
Host smart-40ce0540-d95a-4bbd-ab65-4bff38f2b20a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249888490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2249888490
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1198342053
Short name T286
Test name
Test status
Simulation time 163045099746 ps
CPU time 181.64 seconds
Started Jul 24 07:11:11 PM PDT 24
Finished Jul 24 07:14:13 PM PDT 24
Peak memory 201244 kb
Host smart-62c83441-cdb6-4feb-a0d6-29c2f768e5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198342053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1198342053
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1176998216
Short name T313
Test name
Test status
Simulation time 163470281941 ps
CPU time 200.3 seconds
Started Jul 24 07:11:11 PM PDT 24
Finished Jul 24 07:14:31 PM PDT 24
Peak memory 201320 kb
Host smart-a9e292a7-e9bd-4385-af00-e81da586496f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176998216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1176998216
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3426723222
Short name T441
Test name
Test status
Simulation time 504711699919 ps
CPU time 362.54 seconds
Started Jul 24 07:11:12 PM PDT 24
Finished Jul 24 07:17:14 PM PDT 24
Peak memory 201292 kb
Host smart-4561512d-7af2-4f24-aa88-e6eebc16ee37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426723222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3426723222
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2830475131
Short name T178
Test name
Test status
Simulation time 325884218943 ps
CPU time 257.67 seconds
Started Jul 24 07:11:13 PM PDT 24
Finished Jul 24 07:15:31 PM PDT 24
Peak memory 201320 kb
Host smart-641de861-a89b-4746-aae0-f6d24b680867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830475131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2830475131
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.4215665426
Short name T735
Test name
Test status
Simulation time 167785553738 ps
CPU time 204.19 seconds
Started Jul 24 07:11:15 PM PDT 24
Finished Jul 24 07:14:39 PM PDT 24
Peak memory 201220 kb
Host smart-e0cb5ca2-5d5a-48ce-83ba-3664f19212d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215665426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.4215665426
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1008323699
Short name T254
Test name
Test status
Simulation time 193069104550 ps
CPU time 117.26 seconds
Started Jul 24 07:11:13 PM PDT 24
Finished Jul 24 07:13:11 PM PDT 24
Peak memory 201252 kb
Host smart-ad8fc49b-4361-445c-8faa-a4a421b98c8a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008323699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1008323699
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1969813795
Short name T691
Test name
Test status
Simulation time 409690679092 ps
CPU time 182.99 seconds
Started Jul 24 07:11:08 PM PDT 24
Finished Jul 24 07:14:11 PM PDT 24
Peak memory 201244 kb
Host smart-6bdae221-cf40-40e2-a00a-62df7a304dc7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969813795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1969813795
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1811590950
Short name T506
Test name
Test status
Simulation time 82921610957 ps
CPU time 403.52 seconds
Started Jul 24 07:11:18 PM PDT 24
Finished Jul 24 07:18:02 PM PDT 24
Peak memory 201692 kb
Host smart-d27818dd-98c8-4f63-81a1-dc712bc492f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811590950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1811590950
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1873336031
Short name T502
Test name
Test status
Simulation time 45295855678 ps
CPU time 106.91 seconds
Started Jul 24 07:11:16 PM PDT 24
Finished Jul 24 07:13:03 PM PDT 24
Peak memory 201076 kb
Host smart-4588bbc2-12a4-4bc2-9eab-a7433a8b3f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873336031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1873336031
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.4081322925
Short name T488
Test name
Test status
Simulation time 4357308844 ps
CPU time 1.91 seconds
Started Jul 24 07:11:19 PM PDT 24
Finished Jul 24 07:11:22 PM PDT 24
Peak memory 201200 kb
Host smart-11987cb7-4160-45d9-8469-6af71c321a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081322925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.4081322925
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1085781813
Short name T364
Test name
Test status
Simulation time 5940331028 ps
CPU time 16.11 seconds
Started Jul 24 07:11:11 PM PDT 24
Finished Jul 24 07:11:28 PM PDT 24
Peak memory 201136 kb
Host smart-c80132b5-0209-443e-800f-502da95d98c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085781813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1085781813
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2493209434
Short name T700
Test name
Test status
Simulation time 517793156309 ps
CPU time 594.74 seconds
Started Jul 24 07:11:19 PM PDT 24
Finished Jul 24 07:21:14 PM PDT 24
Peak memory 201220 kb
Host smart-426d3e51-0b83-49d3-a84c-1c896372063f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493209434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2493209434
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3251379206
Short name T589
Test name
Test status
Simulation time 44615141074 ps
CPU time 45.79 seconds
Started Jul 24 07:11:17 PM PDT 24
Finished Jul 24 07:12:03 PM PDT 24
Peak memory 201456 kb
Host smart-ec7beaa0-235d-4af5-beb9-94dc8d9821ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251379206 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3251379206
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2112315162
Short name T745
Test name
Test status
Simulation time 594575276 ps
CPU time 0.71 seconds
Started Jul 24 07:11:32 PM PDT 24
Finished Jul 24 07:11:32 PM PDT 24
Peak memory 201044 kb
Host smart-90bdd921-4cd0-48fa-9e16-ec80db402c91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112315162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2112315162
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3511034945
Short name T10
Test name
Test status
Simulation time 170029508756 ps
CPU time 103.82 seconds
Started Jul 24 07:11:24 PM PDT 24
Finished Jul 24 07:13:08 PM PDT 24
Peak memory 201312 kb
Host smart-620084ce-a63d-43a7-9ea1-6b6c16f34641
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511034945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3511034945
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.4112295326
Short name T754
Test name
Test status
Simulation time 325219116361 ps
CPU time 195.99 seconds
Started Jul 24 07:11:24 PM PDT 24
Finished Jul 24 07:14:40 PM PDT 24
Peak memory 201196 kb
Host smart-ba52bc18-bf2b-44a7-ae70-17aeb7b6af1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112295326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.4112295326
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2433685738
Short name T714
Test name
Test status
Simulation time 327797305801 ps
CPU time 777.92 seconds
Started Jul 24 07:11:24 PM PDT 24
Finished Jul 24 07:24:22 PM PDT 24
Peak memory 201172 kb
Host smart-2b5cc31a-a2ba-4869-9608-c53f1e714cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433685738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2433685738
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2217424357
Short name T461
Test name
Test status
Simulation time 327561772816 ps
CPU time 185.07 seconds
Started Jul 24 07:11:25 PM PDT 24
Finished Jul 24 07:14:30 PM PDT 24
Peak memory 201112 kb
Host smart-254df653-8ebb-41e4-9a1f-1c25bd480422
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217424357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2217424357
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2046241007
Short name T609
Test name
Test status
Simulation time 490726612932 ps
CPU time 537.75 seconds
Started Jul 24 07:11:25 PM PDT 24
Finished Jul 24 07:20:23 PM PDT 24
Peak memory 201236 kb
Host smart-19443190-b1a6-42ab-9d95-f1d3a6865bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046241007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2046241007
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.744877009
Short name T410
Test name
Test status
Simulation time 493010190765 ps
CPU time 292.31 seconds
Started Jul 24 07:11:25 PM PDT 24
Finished Jul 24 07:16:18 PM PDT 24
Peak memory 201224 kb
Host smart-66402ed7-7535-4e5a-8585-b4d204cbc1d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=744877009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.744877009
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3795974580
Short name T561
Test name
Test status
Simulation time 389635533083 ps
CPU time 891.78 seconds
Started Jul 24 07:11:24 PM PDT 24
Finished Jul 24 07:26:16 PM PDT 24
Peak memory 201200 kb
Host smart-82256fe0-5a20-4111-8aa9-101b536b3a99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795974580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3795974580
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1414322844
Short name T429
Test name
Test status
Simulation time 119104454419 ps
CPU time 677.08 seconds
Started Jul 24 07:11:31 PM PDT 24
Finished Jul 24 07:22:48 PM PDT 24
Peak memory 201732 kb
Host smart-5e36b86b-e292-4b3e-bcde-9fb7bd732ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414322844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1414322844
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2272329749
Short name T593
Test name
Test status
Simulation time 45276040849 ps
CPU time 101.83 seconds
Started Jul 24 07:11:31 PM PDT 24
Finished Jul 24 07:13:13 PM PDT 24
Peak memory 201092 kb
Host smart-332b6d7e-fafa-4051-abe3-ca555b4211ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272329749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2272329749
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1680743867
Short name T525
Test name
Test status
Simulation time 5215650437 ps
CPU time 11.85 seconds
Started Jul 24 07:11:23 PM PDT 24
Finished Jul 24 07:11:35 PM PDT 24
Peak memory 201044 kb
Host smart-f2efc6bb-e629-4ea7-9edf-ef331ea634cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680743867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1680743867
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3385877085
Short name T600
Test name
Test status
Simulation time 5748608674 ps
CPU time 3.86 seconds
Started Jul 24 07:11:25 PM PDT 24
Finished Jul 24 07:11:28 PM PDT 24
Peak memory 201064 kb
Host smart-e3514df8-1ad2-40e4-be75-0b5737ce4737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385877085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3385877085
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2761729717
Short name T732
Test name
Test status
Simulation time 509034433026 ps
CPU time 1189.26 seconds
Started Jul 24 07:11:29 PM PDT 24
Finished Jul 24 07:31:18 PM PDT 24
Peak memory 209876 kb
Host smart-9339121a-ef12-48f4-8c6b-9bb09d03f844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761729717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2761729717
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.1873396640
Short name T605
Test name
Test status
Simulation time 48594564162 ps
CPU time 26.54 seconds
Started Jul 24 07:11:30 PM PDT 24
Finished Jul 24 07:11:57 PM PDT 24
Peak memory 209456 kb
Host smart-7bf11845-bbb6-44da-8a79-1729ce497740
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873396640 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.1873396640
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1650128502
Short name T68
Test name
Test status
Simulation time 315785315 ps
CPU time 1.35 seconds
Started Jul 24 07:11:39 PM PDT 24
Finished Jul 24 07:11:40 PM PDT 24
Peak memory 201060 kb
Host smart-d9da2eca-b268-4612-a79b-6bfbf12a4f08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650128502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1650128502
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1203676675
Short name T614
Test name
Test status
Simulation time 161155928987 ps
CPU time 87.41 seconds
Started Jul 24 07:11:38 PM PDT 24
Finished Jul 24 07:13:05 PM PDT 24
Peak memory 201372 kb
Host smart-eea82f91-6cae-4d20-911d-f4c6bbaaacf5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203676675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1203676675
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.432539199
Short name T577
Test name
Test status
Simulation time 317079732317 ps
CPU time 357.29 seconds
Started Jul 24 07:11:28 PM PDT 24
Finished Jul 24 07:17:26 PM PDT 24
Peak memory 201224 kb
Host smart-f71f034b-9d8d-4dcc-8bc1-e0b5cb57f81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432539199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.432539199
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.396144112
Short name T703
Test name
Test status
Simulation time 324716481489 ps
CPU time 190.85 seconds
Started Jul 24 07:11:31 PM PDT 24
Finished Jul 24 07:14:42 PM PDT 24
Peak memory 201296 kb
Host smart-1c6d2150-1bca-447f-9f10-65f2d300f8fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=396144112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.396144112
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3373322897
Short name T733
Test name
Test status
Simulation time 496547776427 ps
CPU time 262.21 seconds
Started Jul 24 07:11:30 PM PDT 24
Finished Jul 24 07:15:53 PM PDT 24
Peak memory 201276 kb
Host smart-06fe42b6-fb48-46f8-9dcc-00b990fcd750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373322897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3373322897
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1948413534
Short name T708
Test name
Test status
Simulation time 167324537329 ps
CPU time 24.36 seconds
Started Jul 24 07:11:30 PM PDT 24
Finished Jul 24 07:11:54 PM PDT 24
Peak memory 201232 kb
Host smart-f35e5f2d-a11b-40e2-9fdb-20d38a836f77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948413534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1948413534
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2403001343
Short name T619
Test name
Test status
Simulation time 557821516461 ps
CPU time 298.14 seconds
Started Jul 24 07:11:30 PM PDT 24
Finished Jul 24 07:16:28 PM PDT 24
Peak memory 201208 kb
Host smart-39a3e6f8-82ad-4137-83c8-d7b79f3dd85d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403001343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2403001343
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.4109825572
Short name T501
Test name
Test status
Simulation time 624897203537 ps
CPU time 773.03 seconds
Started Jul 24 07:11:39 PM PDT 24
Finished Jul 24 07:24:33 PM PDT 24
Peak memory 201184 kb
Host smart-b50b5fd0-9838-4c81-9c04-62b2af8ebf16
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109825572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.4109825572
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2771358805
Short name T740
Test name
Test status
Simulation time 106642201965 ps
CPU time 405.01 seconds
Started Jul 24 07:11:42 PM PDT 24
Finished Jul 24 07:18:27 PM PDT 24
Peak memory 201732 kb
Host smart-73619637-e34a-4bba-803b-f13a15b210a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771358805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2771358805
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1569144198
Short name T375
Test name
Test status
Simulation time 37510193866 ps
CPU time 24.51 seconds
Started Jul 24 07:11:39 PM PDT 24
Finished Jul 24 07:12:04 PM PDT 24
Peak memory 201072 kb
Host smart-e3eaabb6-421e-4a31-aeb5-28baae8d7a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569144198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1569144198
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3275664408
Short name T399
Test name
Test status
Simulation time 5187677540 ps
CPU time 2.56 seconds
Started Jul 24 07:11:40 PM PDT 24
Finished Jul 24 07:11:43 PM PDT 24
Peak memory 201116 kb
Host smart-dbffd938-c03d-473d-8d3b-d3be58344ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275664408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3275664408
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1246986487
Short name T601
Test name
Test status
Simulation time 5986307329 ps
CPU time 12.98 seconds
Started Jul 24 07:11:29 PM PDT 24
Finished Jul 24 07:11:42 PM PDT 24
Peak memory 201088 kb
Host smart-72f5f6db-40ad-45a0-b171-eb6971a1c0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246986487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1246986487
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.369582773
Short name T223
Test name
Test status
Simulation time 335539262245 ps
CPU time 395.96 seconds
Started Jul 24 07:11:40 PM PDT 24
Finished Jul 24 07:18:17 PM PDT 24
Peak memory 201276 kb
Host smart-399159a1-065b-49a8-8a6f-3beb2dd0206b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369582773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
369582773
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.653198705
Short name T21
Test name
Test status
Simulation time 188085472200 ps
CPU time 489.24 seconds
Started Jul 24 07:11:40 PM PDT 24
Finished Jul 24 07:19:49 PM PDT 24
Peak memory 210052 kb
Host smart-4095d4cf-a614-432d-b0a4-f6e20158ba56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653198705 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.653198705
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.88504766
Short name T392
Test name
Test status
Simulation time 512084042 ps
CPU time 1.82 seconds
Started Jul 24 07:11:50 PM PDT 24
Finished Jul 24 07:11:52 PM PDT 24
Peak memory 201040 kb
Host smart-03d94815-4ec6-416c-9301-645a26a0fa17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88504766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.88504766
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2869867389
Short name T205
Test name
Test status
Simulation time 168708733816 ps
CPU time 390.41 seconds
Started Jul 24 07:11:39 PM PDT 24
Finished Jul 24 07:18:10 PM PDT 24
Peak memory 201276 kb
Host smart-bfdbc873-ea36-4e46-a0a7-c0cf1d5348a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869867389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2869867389
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2955773768
Short name T514
Test name
Test status
Simulation time 490895753263 ps
CPU time 213.56 seconds
Started Jul 24 07:11:47 PM PDT 24
Finished Jul 24 07:15:21 PM PDT 24
Peak memory 201252 kb
Host smart-8167fdd0-2570-4d9c-9d64-bb5472b50cb9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955773768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2955773768
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1739731452
Short name T175
Test name
Test status
Simulation time 324326783188 ps
CPU time 49.54 seconds
Started Jul 24 07:11:40 PM PDT 24
Finished Jul 24 07:12:30 PM PDT 24
Peak memory 201304 kb
Host smart-158d8cd6-17a5-4132-8641-a9ff5e088918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739731452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1739731452
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3211115980
Short name T782
Test name
Test status
Simulation time 332163934156 ps
CPU time 82.11 seconds
Started Jul 24 07:11:39 PM PDT 24
Finished Jul 24 07:13:01 PM PDT 24
Peak memory 201188 kb
Host smart-009a7967-1a79-46b6-b08b-0c35c2e0d87a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211115980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3211115980
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.943340407
Short name T371
Test name
Test status
Simulation time 593629654680 ps
CPU time 730.67 seconds
Started Jul 24 07:11:47 PM PDT 24
Finished Jul 24 07:23:58 PM PDT 24
Peak memory 201184 kb
Host smart-586efc4a-7c80-4365-9080-0e5d3672f53d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943340407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.943340407
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1545283836
Short name T197
Test name
Test status
Simulation time 130732478493 ps
CPU time 673.67 seconds
Started Jul 24 07:11:45 PM PDT 24
Finished Jul 24 07:22:59 PM PDT 24
Peak memory 201676 kb
Host smart-138ea5b3-5df6-446f-8125-d92a1f3c3f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545283836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1545283836
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.797408867
Short name T481
Test name
Test status
Simulation time 25272220654 ps
CPU time 27 seconds
Started Jul 24 07:11:48 PM PDT 24
Finished Jul 24 07:12:15 PM PDT 24
Peak memory 201052 kb
Host smart-0c38b457-5166-4f8f-9b8f-09524d1cd208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797408867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.797408867
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.4056196119
Short name T471
Test name
Test status
Simulation time 5410048413 ps
CPU time 4.01 seconds
Started Jul 24 07:11:47 PM PDT 24
Finished Jul 24 07:11:52 PM PDT 24
Peak memory 201076 kb
Host smart-24f4dcce-315d-4cd1-b628-3621dc19d28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056196119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.4056196119
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2739847567
Short name T463
Test name
Test status
Simulation time 5802856173 ps
CPU time 14.76 seconds
Started Jul 24 07:11:38 PM PDT 24
Finished Jul 24 07:11:53 PM PDT 24
Peak memory 201092 kb
Host smart-1de27e8a-e5c6-4355-a2cb-4ed6909c0460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739847567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2739847567
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.258439744
Short name T773
Test name
Test status
Simulation time 352493648177 ps
CPU time 205.28 seconds
Started Jul 24 07:11:46 PM PDT 24
Finished Jul 24 07:15:12 PM PDT 24
Peak memory 201224 kb
Host smart-f20fbc80-ae84-4f46-a399-5c09b19e9960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258439744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
258439744
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4164228788
Short name T20
Test name
Test status
Simulation time 88150958520 ps
CPU time 191.88 seconds
Started Jul 24 07:11:45 PM PDT 24
Finished Jul 24 07:14:57 PM PDT 24
Peak memory 209632 kb
Host smart-9695169d-7993-4c24-ab17-5e647878b45b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164228788 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.4164228788
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.832070086
Short name T725
Test name
Test status
Simulation time 495064284 ps
CPU time 0.67 seconds
Started Jul 24 07:12:02 PM PDT 24
Finished Jul 24 07:12:02 PM PDT 24
Peak memory 201012 kb
Host smart-6b5b0070-eb87-4311-9caa-02ae45a2318b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832070086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.832070086
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3689896513
Short name T328
Test name
Test status
Simulation time 338755495776 ps
CPU time 132.41 seconds
Started Jul 24 07:11:58 PM PDT 24
Finished Jul 24 07:14:10 PM PDT 24
Peak memory 201220 kb
Host smart-ae64c5b8-55d8-4b91-a767-790c98a41f42
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689896513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3689896513
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.468911338
Short name T692
Test name
Test status
Simulation time 161677038890 ps
CPU time 184.56 seconds
Started Jul 24 07:11:58 PM PDT 24
Finished Jul 24 07:15:02 PM PDT 24
Peak memory 201220 kb
Host smart-b124ba6c-052c-47d0-8df8-20d3193755b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468911338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.468911338
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.708636045
Short name T438
Test name
Test status
Simulation time 497619688209 ps
CPU time 1113.08 seconds
Started Jul 24 07:11:59 PM PDT 24
Finished Jul 24 07:30:33 PM PDT 24
Peak memory 201220 kb
Host smart-c6179198-7cb6-4685-9076-9d71b36f91db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=708636045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.708636045
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1256270831
Short name T707
Test name
Test status
Simulation time 324086333073 ps
CPU time 357.8 seconds
Started Jul 24 07:11:51 PM PDT 24
Finished Jul 24 07:17:49 PM PDT 24
Peak memory 201268 kb
Host smart-e712c1c4-ae6a-4384-bc8a-bde490ab3011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256270831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1256270831
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1724183125
Short name T439
Test name
Test status
Simulation time 491896165079 ps
CPU time 301.32 seconds
Started Jul 24 07:11:52 PM PDT 24
Finished Jul 24 07:16:54 PM PDT 24
Peak memory 201224 kb
Host smart-e5241cec-34b6-4e4d-ad95-fb24c30d8b5d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724183125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1724183125
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.135350327
Short name T428
Test name
Test status
Simulation time 190381080090 ps
CPU time 242.05 seconds
Started Jul 24 07:11:56 PM PDT 24
Finished Jul 24 07:15:58 PM PDT 24
Peak memory 201116 kb
Host smart-2f18fcc7-3819-4c1d-a822-d8412a42ab73
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135350327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.135350327
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.291197905
Short name T88
Test name
Test status
Simulation time 143826612970 ps
CPU time 740.21 seconds
Started Jul 24 07:12:02 PM PDT 24
Finished Jul 24 07:24:23 PM PDT 24
Peak memory 201688 kb
Host smart-30cf4252-d20e-427f-99c0-32459eca54e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291197905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.291197905
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.513908810
Short name T354
Test name
Test status
Simulation time 45444344120 ps
CPU time 52.06 seconds
Started Jul 24 07:11:54 PM PDT 24
Finished Jul 24 07:12:47 PM PDT 24
Peak memory 201064 kb
Host smart-84031dcf-97f5-4bee-870e-1991b0e5b740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513908810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.513908810
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.4270112052
Short name T357
Test name
Test status
Simulation time 5194180826 ps
CPU time 3.71 seconds
Started Jul 24 07:11:55 PM PDT 24
Finished Jul 24 07:11:59 PM PDT 24
Peak memory 201060 kb
Host smart-fcb4686a-f89f-4300-ae6b-f2af873ef9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270112052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.4270112052
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1806001391
Short name T648
Test name
Test status
Simulation time 5878248031 ps
CPU time 2.81 seconds
Started Jul 24 07:11:53 PM PDT 24
Finished Jul 24 07:11:56 PM PDT 24
Peak memory 201108 kb
Host smart-20ef2cfc-4d0d-4f07-ae04-56bcb241b746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806001391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1806001391
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3895316293
Short name T724
Test name
Test status
Simulation time 186877178204 ps
CPU time 316.62 seconds
Started Jul 24 07:12:03 PM PDT 24
Finished Jul 24 07:17:20 PM PDT 24
Peak memory 201268 kb
Host smart-bc1ff4de-98f6-4f54-8ab6-c7a724294b6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895316293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3895316293
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1916971823
Short name T318
Test name
Test status
Simulation time 55011086141 ps
CPU time 123.63 seconds
Started Jul 24 07:12:02 PM PDT 24
Finished Jul 24 07:14:06 PM PDT 24
Peak memory 201512 kb
Host smart-fd1054eb-2aa1-4fc1-9fc6-d0cb49c77362
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916971823 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1916971823
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3558412394
Short name T159
Test name
Test status
Simulation time 402199967 ps
CPU time 1.49 seconds
Started Jul 24 07:12:20 PM PDT 24
Finished Jul 24 07:12:22 PM PDT 24
Peak memory 201060 kb
Host smart-10f17e82-eef9-42a1-8f7e-df948b77e294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558412394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3558412394
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3167781592
Short name T309
Test name
Test status
Simulation time 535862771643 ps
CPU time 1243.68 seconds
Started Jul 24 07:12:06 PM PDT 24
Finished Jul 24 07:32:50 PM PDT 24
Peak memory 201316 kb
Host smart-19fdc038-5709-4907-8b04-9972daee0040
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167781592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3167781592
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1219610647
Short name T315
Test name
Test status
Simulation time 335408528327 ps
CPU time 654.1 seconds
Started Jul 24 07:12:14 PM PDT 24
Finished Jul 24 07:23:08 PM PDT 24
Peak memory 201256 kb
Host smart-e59ea645-8146-4176-ba36-92f29e5598ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219610647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1219610647
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1158741236
Short name T3
Test name
Test status
Simulation time 168689965053 ps
CPU time 195.3 seconds
Started Jul 24 07:12:03 PM PDT 24
Finished Jul 24 07:15:19 PM PDT 24
Peak memory 201316 kb
Host smart-487c755d-530d-4696-9f50-ef04bb97c39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158741236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1158741236
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2624489751
Short name T631
Test name
Test status
Simulation time 159379910803 ps
CPU time 29.79 seconds
Started Jul 24 07:12:07 PM PDT 24
Finished Jul 24 07:12:37 PM PDT 24
Peak memory 201300 kb
Host smart-c5d1ea3e-ca41-4bfa-8bd1-072baf01830e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624489751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2624489751
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3764406650
Short name T140
Test name
Test status
Simulation time 484712583465 ps
CPU time 281.18 seconds
Started Jul 24 07:12:02 PM PDT 24
Finished Jul 24 07:16:43 PM PDT 24
Peak memory 201264 kb
Host smart-1bb532cd-6663-4dd1-8190-9bb7c4866110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764406650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3764406650
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3007500439
Short name T409
Test name
Test status
Simulation time 495954955676 ps
CPU time 329.56 seconds
Started Jul 24 07:12:02 PM PDT 24
Finished Jul 24 07:17:31 PM PDT 24
Peak memory 201232 kb
Host smart-fb6cbdb4-a82d-4da3-a09f-59f3fd126e86
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007500439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3007500439
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.425017970
Short name T772
Test name
Test status
Simulation time 201514185443 ps
CPU time 238.92 seconds
Started Jul 24 07:12:08 PM PDT 24
Finished Jul 24 07:16:07 PM PDT 24
Peak memory 201300 kb
Host smart-91827498-446f-41d4-9e95-6b32ab388883
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425017970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.425017970
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.676067469
Short name T198
Test name
Test status
Simulation time 132080275531 ps
CPU time 470.06 seconds
Started Jul 24 07:12:14 PM PDT 24
Finished Jul 24 07:20:04 PM PDT 24
Peak memory 201800 kb
Host smart-f9e6279e-d1fb-4fef-839d-3c0c586cb6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676067469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.676067469
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.4275763352
Short name T651
Test name
Test status
Simulation time 43195237894 ps
CPU time 53.38 seconds
Started Jul 24 07:12:14 PM PDT 24
Finished Jul 24 07:13:08 PM PDT 24
Peak memory 201040 kb
Host smart-b385272a-d42e-44fc-8ff8-d6b64f10188a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275763352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.4275763352
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3145166178
Short name T492
Test name
Test status
Simulation time 2791844082 ps
CPU time 7.13 seconds
Started Jul 24 07:12:16 PM PDT 24
Finished Jul 24 07:12:23 PM PDT 24
Peak memory 201092 kb
Host smart-8e94473b-ff73-46a4-843f-d82dfc03c55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145166178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3145166178
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.297346999
Short name T398
Test name
Test status
Simulation time 6082534252 ps
CPU time 4.6 seconds
Started Jul 24 07:12:02 PM PDT 24
Finished Jul 24 07:12:07 PM PDT 24
Peak memory 201136 kb
Host smart-72098ddd-b7a6-4822-af3f-48324414ba38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297346999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.297346999
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2421070673
Short name T472
Test name
Test status
Simulation time 5163741780 ps
CPU time 12.98 seconds
Started Jul 24 07:12:14 PM PDT 24
Finished Jul 24 07:12:28 PM PDT 24
Peak memory 201108 kb
Host smart-1376e523-8914-4459-836d-99423350a023
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421070673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2421070673
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2089707025
Short name T759
Test name
Test status
Simulation time 444906539614 ps
CPU time 626.57 seconds
Started Jul 24 07:12:14 PM PDT 24
Finished Jul 24 07:22:41 PM PDT 24
Peak memory 210048 kb
Host smart-289938a2-c727-4501-b5bc-d44e54e83d56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089707025 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2089707025
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1706812348
Short name T520
Test name
Test status
Simulation time 403107145 ps
CPU time 1 seconds
Started Jul 24 07:12:26 PM PDT 24
Finished Jul 24 07:12:28 PM PDT 24
Peak memory 201152 kb
Host smart-08a3e292-d35a-472c-b057-44054909ce8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706812348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1706812348
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1236585791
Short name T53
Test name
Test status
Simulation time 186984041451 ps
CPU time 128.12 seconds
Started Jul 24 07:12:27 PM PDT 24
Finished Jul 24 07:14:35 PM PDT 24
Peak memory 201232 kb
Host smart-d1479dba-0528-48d5-ae6d-45a84fb55664
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236585791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1236585791
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3331268094
Short name T307
Test name
Test status
Simulation time 518911778942 ps
CPU time 573.64 seconds
Started Jul 24 07:12:27 PM PDT 24
Finished Jul 24 07:22:01 PM PDT 24
Peak memory 201264 kb
Host smart-5b8c52e1-8a29-496e-90e0-27cee19e36e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331268094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3331268094
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1111663353
Short name T688
Test name
Test status
Simulation time 493157845457 ps
CPU time 1119.31 seconds
Started Jul 24 07:12:20 PM PDT 24
Finished Jul 24 07:31:00 PM PDT 24
Peak memory 201316 kb
Host smart-3b803a75-c47e-4b10-af24-bc62650068f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111663353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1111663353
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1566680210
Short name T384
Test name
Test status
Simulation time 479860583523 ps
CPU time 514.49 seconds
Started Jul 24 07:12:27 PM PDT 24
Finished Jul 24 07:21:02 PM PDT 24
Peak memory 201280 kb
Host smart-2783c9c6-718d-4487-967b-8cb2b839c877
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566680210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1566680210
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1929705066
Short name T783
Test name
Test status
Simulation time 481828685182 ps
CPU time 566.47 seconds
Started Jul 24 07:12:20 PM PDT 24
Finished Jul 24 07:21:48 PM PDT 24
Peak memory 201268 kb
Host smart-f07fa3ff-e0ad-48e5-8851-5770c1021ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929705066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1929705066
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.760811564
Short name T378
Test name
Test status
Simulation time 487295540113 ps
CPU time 1147.07 seconds
Started Jul 24 07:12:20 PM PDT 24
Finished Jul 24 07:31:27 PM PDT 24
Peak memory 201232 kb
Host smart-d8f0d719-80ab-4d9e-a4e5-523e7d85c540
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=760811564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.760811564
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3686586369
Short name T293
Test name
Test status
Simulation time 509897984738 ps
CPU time 1117.37 seconds
Started Jul 24 07:12:26 PM PDT 24
Finished Jul 24 07:31:04 PM PDT 24
Peak memory 201284 kb
Host smart-54493ae0-b622-4e65-84ed-c33ca341beec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686586369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3686586369
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1998857049
Short name T448
Test name
Test status
Simulation time 617085396684 ps
CPU time 1437.09 seconds
Started Jul 24 07:12:26 PM PDT 24
Finished Jul 24 07:36:24 PM PDT 24
Peak memory 201228 kb
Host smart-85ef685d-3d5a-4266-b2b2-357ee126b92b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998857049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1998857049
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2665568473
Short name T82
Test name
Test status
Simulation time 117124636255 ps
CPU time 487.14 seconds
Started Jul 24 07:12:26 PM PDT 24
Finished Jul 24 07:20:34 PM PDT 24
Peak memory 201792 kb
Host smart-d9c3f6de-5b63-4029-8a5f-51ff90e8f7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665568473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2665568473
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2267521631
Short name T793
Test name
Test status
Simulation time 33029339748 ps
CPU time 15.19 seconds
Started Jul 24 07:12:27 PM PDT 24
Finished Jul 24 07:12:43 PM PDT 24
Peak memory 201108 kb
Host smart-7b3c02ef-233a-4d91-8fd3-d37a57a28ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267521631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2267521631
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1756215584
Short name T546
Test name
Test status
Simulation time 3540824371 ps
CPU time 5.01 seconds
Started Jul 24 07:12:28 PM PDT 24
Finished Jul 24 07:12:33 PM PDT 24
Peak memory 201080 kb
Host smart-8a2e7f7a-f076-497d-9486-83e4d367748b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756215584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1756215584
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3635347241
Short name T628
Test name
Test status
Simulation time 5607930458 ps
CPU time 7.49 seconds
Started Jul 24 07:12:21 PM PDT 24
Finished Jul 24 07:12:28 PM PDT 24
Peak memory 201012 kb
Host smart-3a2e5af3-155c-4be1-b65c-8439ddbf0795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635347241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3635347241
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2091943729
Short name T270
Test name
Test status
Simulation time 348300560202 ps
CPU time 826.55 seconds
Started Jul 24 07:12:26 PM PDT 24
Finished Jul 24 07:26:13 PM PDT 24
Peak memory 201236 kb
Host smart-46f5d573-f83e-4d0e-9834-f3c1904baa61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091943729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2091943729
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2451576178
Short name T495
Test name
Test status
Simulation time 425939032 ps
CPU time 1.59 seconds
Started Jul 24 07:10:12 PM PDT 24
Finished Jul 24 07:10:14 PM PDT 24
Peak memory 200956 kb
Host smart-7e38aed4-63f4-4996-9e9b-e2b988fbbb7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451576178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2451576178
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.4170576467
Short name T303
Test name
Test status
Simulation time 568904979826 ps
CPU time 641.73 seconds
Started Jul 24 07:10:15 PM PDT 24
Finished Jul 24 07:20:57 PM PDT 24
Peak memory 201248 kb
Host smart-fdc9de19-c23d-407d-82ff-ec3519baeb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170576467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.4170576467
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2190674709
Short name T133
Test name
Test status
Simulation time 328009859552 ps
CPU time 752.02 seconds
Started Jul 24 07:10:08 PM PDT 24
Finished Jul 24 07:22:40 PM PDT 24
Peak memory 201240 kb
Host smart-b8395010-09aa-4534-8335-09f9f8ab6987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190674709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2190674709
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1234095922
Short name T547
Test name
Test status
Simulation time 322842277326 ps
CPU time 327.85 seconds
Started Jul 24 07:10:05 PM PDT 24
Finished Jul 24 07:15:33 PM PDT 24
Peak memory 201092 kb
Host smart-24365134-c5a8-414c-b455-1d8f23794d0d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234095922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.1234095922
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3283476529
Short name T47
Test name
Test status
Simulation time 330571088819 ps
CPU time 222.22 seconds
Started Jul 24 07:10:10 PM PDT 24
Finished Jul 24 07:13:53 PM PDT 24
Peak memory 201260 kb
Host smart-b7f18eef-1e9c-4bde-9974-e444eaa36a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283476529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3283476529
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1412341226
Short name T518
Test name
Test status
Simulation time 329721063494 ps
CPU time 363.17 seconds
Started Jul 24 07:10:09 PM PDT 24
Finished Jul 24 07:16:12 PM PDT 24
Peak memory 201188 kb
Host smart-ba60a92b-7107-4055-a678-9c3d0caf9bda
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412341226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1412341226
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1252149707
Short name T716
Test name
Test status
Simulation time 376671771235 ps
CPU time 222.47 seconds
Started Jul 24 07:10:12 PM PDT 24
Finished Jul 24 07:13:55 PM PDT 24
Peak memory 201256 kb
Host smart-760cfdc3-f93d-4cff-8403-781926db928b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252149707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1252149707
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.4071167330
Short name T687
Test name
Test status
Simulation time 197590572334 ps
CPU time 230.85 seconds
Started Jul 24 07:10:09 PM PDT 24
Finished Jul 24 07:14:00 PM PDT 24
Peak memory 201240 kb
Host smart-83317d88-279d-4cbf-b97d-6369e977431e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071167330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.4071167330
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3563452402
Short name T43
Test name
Test status
Simulation time 105094605140 ps
CPU time 345.51 seconds
Started Jul 24 07:10:10 PM PDT 24
Finished Jul 24 07:15:56 PM PDT 24
Peak memory 201692 kb
Host smart-332c10c4-d248-4a66-a94a-a7647376d03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563452402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3563452402
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2999932566
Short name T355
Test name
Test status
Simulation time 34027539428 ps
CPU time 19.83 seconds
Started Jul 24 07:10:12 PM PDT 24
Finished Jul 24 07:10:32 PM PDT 24
Peak memory 201128 kb
Host smart-f7ac71bf-b3ed-48fd-91dd-a19a790160eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999932566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2999932566
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2098190681
Short name T766
Test name
Test status
Simulation time 2875498890 ps
CPU time 4.4 seconds
Started Jul 24 07:10:07 PM PDT 24
Finished Jul 24 07:10:12 PM PDT 24
Peak memory 201112 kb
Host smart-55553cef-b98e-431d-aa83-7391c6ffd0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098190681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2098190681
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1174673408
Short name T73
Test name
Test status
Simulation time 3962626119 ps
CPU time 3.21 seconds
Started Jul 24 07:10:21 PM PDT 24
Finished Jul 24 07:10:25 PM PDT 24
Peak memory 217052 kb
Host smart-35ed95b7-6709-49e3-acce-30e3cf9aae87
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174673408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1174673408
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1233193037
Short name T393
Test name
Test status
Simulation time 5793702219 ps
CPU time 14.08 seconds
Started Jul 24 07:10:15 PM PDT 24
Finished Jul 24 07:10:29 PM PDT 24
Peak memory 201104 kb
Host smart-e709f340-2201-4cfd-b67f-5d77fecd0378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233193037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1233193037
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.451714943
Short name T263
Test name
Test status
Simulation time 344323304298 ps
CPU time 199.3 seconds
Started Jul 24 07:10:15 PM PDT 24
Finished Jul 24 07:13:35 PM PDT 24
Peak memory 201172 kb
Host smart-70bc4239-265f-4464-b4f4-3f56d1649032
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451714943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.451714943
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3844177566
Short name T248
Test name
Test status
Simulation time 75089218443 ps
CPU time 43.85 seconds
Started Jul 24 07:10:15 PM PDT 24
Finished Jul 24 07:10:59 PM PDT 24
Peak memory 209572 kb
Host smart-8fe34bfe-95ff-4932-963f-d42b0fa956f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844177566 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3844177566
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1424677029
Short name T571
Test name
Test status
Simulation time 341548097 ps
CPU time 0.87 seconds
Started Jul 24 07:12:41 PM PDT 24
Finished Jul 24 07:12:42 PM PDT 24
Peak memory 201036 kb
Host smart-9f20eda3-e7e0-43da-a5a6-adff92732184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424677029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1424677029
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3429780650
Short name T666
Test name
Test status
Simulation time 165378641094 ps
CPU time 97.86 seconds
Started Jul 24 07:12:32 PM PDT 24
Finished Jul 24 07:14:11 PM PDT 24
Peak memory 201248 kb
Host smart-b96aa03c-696f-43cc-a227-8c8ce8ea04d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429780650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3429780650
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2210710330
Short name T181
Test name
Test status
Simulation time 165901763609 ps
CPU time 82.15 seconds
Started Jul 24 07:12:33 PM PDT 24
Finished Jul 24 07:13:55 PM PDT 24
Peak memory 201224 kb
Host smart-e5b0de7f-32ac-4acc-a21a-2a96b06459a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210710330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2210710330
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3955441674
Short name T566
Test name
Test status
Simulation time 331355764532 ps
CPU time 799.55 seconds
Started Jul 24 07:12:29 PM PDT 24
Finished Jul 24 07:25:48 PM PDT 24
Peak memory 201352 kb
Host smart-abf050cf-fe55-4570-8c13-2a34c1051bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955441674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3955441674
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1511211291
Short name T169
Test name
Test status
Simulation time 488096175185 ps
CPU time 1042.62 seconds
Started Jul 24 07:12:28 PM PDT 24
Finished Jul 24 07:29:51 PM PDT 24
Peak memory 201192 kb
Host smart-42faacba-f8b3-4462-98ad-9868e2a7055e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511211291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1511211291
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3098782901
Short name T705
Test name
Test status
Simulation time 412800684692 ps
CPU time 493.82 seconds
Started Jul 24 07:12:35 PM PDT 24
Finished Jul 24 07:20:49 PM PDT 24
Peak memory 201248 kb
Host smart-8f600af0-5b3c-418c-aecd-13549a3452f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098782901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3098782901
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3224522901
Short name T437
Test name
Test status
Simulation time 594846967711 ps
CPU time 344.38 seconds
Started Jul 24 07:12:32 PM PDT 24
Finished Jul 24 07:18:17 PM PDT 24
Peak memory 201168 kb
Host smart-eb1c6430-1ab8-4f01-8bee-bf56b0b75222
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224522901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3224522901
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3030472242
Short name T690
Test name
Test status
Simulation time 71522747958 ps
CPU time 257.8 seconds
Started Jul 24 07:12:33 PM PDT 24
Finished Jul 24 07:16:51 PM PDT 24
Peak memory 201584 kb
Host smart-8ccaa8c4-2376-48bf-8b9c-4d86b9181189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030472242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3030472242
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.874503886
Short name T418
Test name
Test status
Simulation time 39149810810 ps
CPU time 5.95 seconds
Started Jul 24 07:12:37 PM PDT 24
Finished Jul 24 07:12:43 PM PDT 24
Peak memory 201128 kb
Host smart-3522c813-d07b-46c4-a28c-a0ced30bf2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874503886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.874503886
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.721854265
Short name T370
Test name
Test status
Simulation time 5375409129 ps
CPU time 3.97 seconds
Started Jul 24 07:12:34 PM PDT 24
Finished Jul 24 07:12:38 PM PDT 24
Peak memory 201076 kb
Host smart-4420bd71-ad6d-4c33-b7f4-60c0c4862196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721854265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.721854265
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3052272052
Short name T468
Test name
Test status
Simulation time 5799259813 ps
CPU time 4.09 seconds
Started Jul 24 07:12:29 PM PDT 24
Finished Jul 24 07:12:33 PM PDT 24
Peak memory 201072 kb
Host smart-b2a08aff-b34e-4662-aafb-41c5272beebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052272052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3052272052
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.912688503
Short name T32
Test name
Test status
Simulation time 33037715740 ps
CPU time 19.09 seconds
Started Jul 24 07:12:32 PM PDT 24
Finished Jul 24 07:12:52 PM PDT 24
Peak memory 201440 kb
Host smart-776a690d-6815-418d-8076-0e4704ed1399
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912688503 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.912688503
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1688221023
Short name T476
Test name
Test status
Simulation time 389923852 ps
CPU time 0.77 seconds
Started Jul 24 07:12:49 PM PDT 24
Finished Jul 24 07:12:50 PM PDT 24
Peak memory 201036 kb
Host smart-0650ba4c-37c4-4f08-9418-7ac7d29d0a82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688221023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1688221023
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2012346399
Short name T143
Test name
Test status
Simulation time 332129858523 ps
CPU time 139.23 seconds
Started Jul 24 07:12:39 PM PDT 24
Finished Jul 24 07:14:59 PM PDT 24
Peak memory 201272 kb
Host smart-119a9996-d81a-496d-9fd8-8cc524835af1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012346399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2012346399
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.235512103
Short name T158
Test name
Test status
Simulation time 326575414537 ps
CPU time 160.2 seconds
Started Jul 24 07:12:41 PM PDT 24
Finished Jul 24 07:15:22 PM PDT 24
Peak memory 201300 kb
Host smart-f81bee17-f5cb-4df0-8093-084da4f57220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235512103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.235512103
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.803553290
Short name T395
Test name
Test status
Simulation time 327029795995 ps
CPU time 747.07 seconds
Started Jul 24 07:12:40 PM PDT 24
Finished Jul 24 07:25:08 PM PDT 24
Peak memory 201272 kb
Host smart-58a6f7f1-be47-4a77-a30c-7c80f564f71a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=803553290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.803553290
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1387439396
Short name T510
Test name
Test status
Simulation time 488904932710 ps
CPU time 275.65 seconds
Started Jul 24 07:12:42 PM PDT 24
Finished Jul 24 07:17:18 PM PDT 24
Peak memory 201256 kb
Host smart-f4ef259c-896e-417c-831a-d133a446a7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387439396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1387439396
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.915416979
Short name T554
Test name
Test status
Simulation time 347850881903 ps
CPU time 221.25 seconds
Started Jul 24 07:12:42 PM PDT 24
Finished Jul 24 07:16:23 PM PDT 24
Peak memory 201200 kb
Host smart-ae6f3088-8f1e-481b-a5d4-afafdb0ab8b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=915416979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.915416979
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.929931461
Short name T323
Test name
Test status
Simulation time 204072583427 ps
CPU time 465.76 seconds
Started Jul 24 07:12:40 PM PDT 24
Finished Jul 24 07:20:26 PM PDT 24
Peak memory 201280 kb
Host smart-956128f4-ca85-46c4-9897-bd87d59658a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929931461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.929931461
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1810618312
Short name T411
Test name
Test status
Simulation time 200139692581 ps
CPU time 106.52 seconds
Started Jul 24 07:12:50 PM PDT 24
Finished Jul 24 07:14:37 PM PDT 24
Peak memory 201216 kb
Host smart-1dc7212a-0b38-450c-b678-1cdf77d46064
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810618312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1810618312
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3658715933
Short name T513
Test name
Test status
Simulation time 98902305236 ps
CPU time 357.9 seconds
Started Jul 24 07:12:48 PM PDT 24
Finished Jul 24 07:18:46 PM PDT 24
Peak memory 201736 kb
Host smart-20b3909a-21c7-4d97-9dc8-53abc96c74fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658715933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3658715933
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3005819214
Short name T419
Test name
Test status
Simulation time 40081287961 ps
CPU time 96.16 seconds
Started Jul 24 07:12:47 PM PDT 24
Finished Jul 24 07:14:23 PM PDT 24
Peak memory 201116 kb
Host smart-8459b0c4-eece-45c7-952e-1fa511dd0414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005819214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3005819214
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.387352950
Short name T636
Test name
Test status
Simulation time 4846745972 ps
CPU time 6.48 seconds
Started Jul 24 07:12:47 PM PDT 24
Finished Jul 24 07:12:54 PM PDT 24
Peak memory 201084 kb
Host smart-7a976b98-cf9a-4a73-9a5e-b9a7ec0ef15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387352950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.387352950
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2042009528
Short name T493
Test name
Test status
Simulation time 5868461665 ps
CPU time 14.33 seconds
Started Jul 24 07:12:50 PM PDT 24
Finished Jul 24 07:13:05 PM PDT 24
Peak memory 201096 kb
Host smart-0c03a5e4-3f4b-4544-80ee-5bb625c78ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042009528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2042009528
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1479994558
Short name T273
Test name
Test status
Simulation time 211567170187 ps
CPU time 320.43 seconds
Started Jul 24 07:12:48 PM PDT 24
Finished Jul 24 07:18:08 PM PDT 24
Peak memory 201208 kb
Host smart-e6cc1606-f09f-49a4-83d3-2c038d1c43e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479994558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1479994558
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1977746052
Short name T137
Test name
Test status
Simulation time 106161875751 ps
CPU time 189.69 seconds
Started Jul 24 07:12:49 PM PDT 24
Finished Jul 24 07:15:59 PM PDT 24
Peak memory 217464 kb
Host smart-712c6329-033b-46b8-81e8-5f3b5b7deccc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977746052 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1977746052
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3455131678
Short name T390
Test name
Test status
Simulation time 395876256 ps
CPU time 1.62 seconds
Started Jul 24 07:13:07 PM PDT 24
Finished Jul 24 07:13:09 PM PDT 24
Peak memory 201016 kb
Host smart-75520957-2fe1-440a-8c51-163f585cea4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455131678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3455131678
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.1895275446
Short name T781
Test name
Test status
Simulation time 179824934337 ps
CPU time 69.78 seconds
Started Jul 24 07:12:59 PM PDT 24
Finished Jul 24 07:14:09 PM PDT 24
Peak memory 201192 kb
Host smart-2fb9b41a-0d42-4826-ab19-2f5faed51868
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895275446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.1895275446
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2160653300
Short name T306
Test name
Test status
Simulation time 325768825181 ps
CPU time 465.77 seconds
Started Jul 24 07:12:59 PM PDT 24
Finished Jul 24 07:20:45 PM PDT 24
Peak memory 201132 kb
Host smart-e156d760-b5d5-4019-b5a7-137ecb499b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160653300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2160653300
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.373624533
Short name T102
Test name
Test status
Simulation time 164009416249 ps
CPU time 198.53 seconds
Started Jul 24 07:12:55 PM PDT 24
Finished Jul 24 07:16:14 PM PDT 24
Peak memory 201200 kb
Host smart-77b1bc8f-3aab-49b3-b9ff-b0df1aa3dea5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=373624533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.373624533
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1284292521
Short name T534
Test name
Test status
Simulation time 489833668877 ps
CPU time 1061.94 seconds
Started Jul 24 07:12:54 PM PDT 24
Finished Jul 24 07:30:36 PM PDT 24
Peak memory 201116 kb
Host smart-b401798d-63cd-4c19-be88-f4668b12b8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284292521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1284292521
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.743080832
Short name T454
Test name
Test status
Simulation time 159197407762 ps
CPU time 368.23 seconds
Started Jul 24 07:12:55 PM PDT 24
Finished Jul 24 07:19:04 PM PDT 24
Peak memory 201200 kb
Host smart-61d1a9b2-a0ac-4374-af16-843ff2f72569
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=743080832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.743080832
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3353268729
Short name T177
Test name
Test status
Simulation time 525722669330 ps
CPU time 202.86 seconds
Started Jul 24 07:12:58 PM PDT 24
Finished Jul 24 07:16:21 PM PDT 24
Peak memory 201232 kb
Host smart-41cc3bd0-ec29-4278-934c-dcc86a13f2bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353268729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3353268729
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3274030009
Short name T556
Test name
Test status
Simulation time 211519075070 ps
CPU time 486.81 seconds
Started Jul 24 07:12:54 PM PDT 24
Finished Jul 24 07:21:00 PM PDT 24
Peak memory 201408 kb
Host smart-ec8c53d3-bea5-4472-8c7e-e7715ad42de8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274030009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3274030009
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.614353213
Short name T473
Test name
Test status
Simulation time 76770987640 ps
CPU time 244.55 seconds
Started Jul 24 07:13:01 PM PDT 24
Finished Jul 24 07:17:06 PM PDT 24
Peak memory 201688 kb
Host smart-fe52fbe0-054b-4084-b149-cf2aa992535e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614353213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.614353213
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2218026515
Short name T542
Test name
Test status
Simulation time 42041362598 ps
CPU time 27.72 seconds
Started Jul 24 07:12:59 PM PDT 24
Finished Jul 24 07:13:27 PM PDT 24
Peak memory 201092 kb
Host smart-369a3eca-a7c5-4a42-9e12-e709bbe75134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218026515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2218026515
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3548574487
Short name T665
Test name
Test status
Simulation time 5131766020 ps
CPU time 11.53 seconds
Started Jul 24 07:13:00 PM PDT 24
Finished Jul 24 07:13:12 PM PDT 24
Peak memory 201068 kb
Host smart-b5449c87-e4dc-4116-9bd5-4db0e37b0052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548574487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3548574487
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.827169689
Short name T457
Test name
Test status
Simulation time 5983166172 ps
CPU time 7.95 seconds
Started Jul 24 07:12:52 PM PDT 24
Finished Jul 24 07:13:00 PM PDT 24
Peak memory 201120 kb
Host smart-6eacc5a4-12d0-493e-befd-4a4a64b308cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827169689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.827169689
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2450602658
Short name T582
Test name
Test status
Simulation time 42065602596 ps
CPU time 24.37 seconds
Started Jul 24 07:12:59 PM PDT 24
Finished Jul 24 07:13:24 PM PDT 24
Peak memory 201260 kb
Host smart-5653316c-d40e-4104-9065-07e2e81b58d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450602658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2450602658
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.4210402318
Short name T67
Test name
Test status
Simulation time 556591508 ps
CPU time 0.93 seconds
Started Jul 24 07:13:20 PM PDT 24
Finished Jul 24 07:13:21 PM PDT 24
Peak memory 201028 kb
Host smart-a956472e-80cb-441b-be41-0751f35085c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210402318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.4210402318
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3119499804
Short name T778
Test name
Test status
Simulation time 400737314598 ps
CPU time 184.46 seconds
Started Jul 24 07:13:12 PM PDT 24
Finished Jul 24 07:16:17 PM PDT 24
Peak memory 201208 kb
Host smart-d1e87d0c-2ad6-40ea-8c35-406534b64781
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119499804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3119499804
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.215455428
Short name T77
Test name
Test status
Simulation time 164496509147 ps
CPU time 364.26 seconds
Started Jul 24 07:13:06 PM PDT 24
Finished Jul 24 07:19:10 PM PDT 24
Peak memory 201364 kb
Host smart-d9118a67-8033-4739-8276-c6d5951f33fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215455428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.215455428
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1342602180
Short name T555
Test name
Test status
Simulation time 491325391104 ps
CPU time 243.55 seconds
Started Jul 24 07:13:07 PM PDT 24
Finished Jul 24 07:17:11 PM PDT 24
Peak memory 201276 kb
Host smart-23458e6f-e871-471e-b0fc-c2565b9bae04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342602180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1342602180
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2938316560
Short name T131
Test name
Test status
Simulation time 164081770767 ps
CPU time 189.73 seconds
Started Jul 24 07:13:05 PM PDT 24
Finished Jul 24 07:16:15 PM PDT 24
Peak memory 201172 kb
Host smart-d36ed76f-4118-489c-8e09-8b51b9c02f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938316560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2938316560
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2612830578
Short name T517
Test name
Test status
Simulation time 157488521765 ps
CPU time 183.86 seconds
Started Jul 24 07:13:07 PM PDT 24
Finished Jul 24 07:16:11 PM PDT 24
Peak memory 201216 kb
Host smart-895fae53-e473-41cd-a6a4-ad861cf078d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612830578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2612830578
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.4015021041
Short name T236
Test name
Test status
Simulation time 179728667833 ps
CPU time 416.03 seconds
Started Jul 24 07:13:05 PM PDT 24
Finished Jul 24 07:20:01 PM PDT 24
Peak memory 201288 kb
Host smart-9870646b-20d3-4d67-83b4-915be3f839d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015021041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.4015021041
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.838789565
Short name T31
Test name
Test status
Simulation time 399120356064 ps
CPU time 181.6 seconds
Started Jul 24 07:13:14 PM PDT 24
Finished Jul 24 07:16:16 PM PDT 24
Peak memory 201244 kb
Host smart-37c69ade-dacd-498e-8e93-62238e2d7b0e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838789565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.838789565
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3434431939
Short name T522
Test name
Test status
Simulation time 37339429611 ps
CPU time 82.72 seconds
Started Jul 24 07:13:18 PM PDT 24
Finished Jul 24 07:14:41 PM PDT 24
Peak memory 201048 kb
Host smart-f3bc1060-c3e8-4a28-96fb-f2de667a1ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434431939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3434431939
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.955042495
Short name T598
Test name
Test status
Simulation time 3836299062 ps
CPU time 5.01 seconds
Started Jul 24 07:13:13 PM PDT 24
Finished Jul 24 07:13:18 PM PDT 24
Peak memory 201204 kb
Host smart-0d68391e-ab63-47ea-bcc9-d996671457ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955042495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.955042495
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.719743300
Short name T568
Test name
Test status
Simulation time 5838076325 ps
CPU time 16.26 seconds
Started Jul 24 07:13:07 PM PDT 24
Finished Jul 24 07:13:23 PM PDT 24
Peak memory 201108 kb
Host smart-ee020a85-0d45-4bf7-8fc3-194e66488354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719743300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.719743300
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1100640780
Short name T54
Test name
Test status
Simulation time 363387889822 ps
CPU time 758.75 seconds
Started Jul 24 07:13:21 PM PDT 24
Finished Jul 24 07:26:00 PM PDT 24
Peak memory 201244 kb
Host smart-384500d1-29ec-4c37-b563-a3e2268891f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100640780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1100640780
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1994919029
Short name T17
Test name
Test status
Simulation time 3463266147297 ps
CPU time 792.52 seconds
Started Jul 24 07:13:20 PM PDT 24
Finished Jul 24 07:26:32 PM PDT 24
Peak memory 210076 kb
Host smart-ad9fe2fb-7289-4e54-9561-500994e5d4b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994919029 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1994919029
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2727440773
Short name T515
Test name
Test status
Simulation time 460978373 ps
CPU time 0.88 seconds
Started Jul 24 07:13:31 PM PDT 24
Finished Jul 24 07:13:32 PM PDT 24
Peak memory 201040 kb
Host smart-7d2dbfee-691d-4713-b475-8c3335f30282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727440773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2727440773
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.31588354
Short name T185
Test name
Test status
Simulation time 346544261331 ps
CPU time 140.91 seconds
Started Jul 24 07:13:26 PM PDT 24
Finished Jul 24 07:15:47 PM PDT 24
Peak memory 201232 kb
Host smart-52473b64-ab39-4ebe-9f4b-aa8be45db038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31588354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.31588354
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.460941231
Short name T603
Test name
Test status
Simulation time 163901020073 ps
CPU time 334.14 seconds
Started Jul 24 07:13:21 PM PDT 24
Finished Jul 24 07:18:55 PM PDT 24
Peak memory 201332 kb
Host smart-5cc990e2-3c3a-4a02-a08f-4b229f2371b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460941231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.460941231
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3518250092
Short name T529
Test name
Test status
Simulation time 496066570884 ps
CPU time 1199.62 seconds
Started Jul 24 07:13:28 PM PDT 24
Finished Jul 24 07:33:28 PM PDT 24
Peak memory 201236 kb
Host smart-210b3998-7504-4e18-9000-a9ee30f6b26d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518250092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3518250092
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3005225232
Short name T351
Test name
Test status
Simulation time 162595325278 ps
CPU time 337.54 seconds
Started Jul 24 07:13:19 PM PDT 24
Finished Jul 24 07:18:56 PM PDT 24
Peak memory 201228 kb
Host smart-4c33e101-8afb-4b21-92a6-2525ad690644
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005225232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3005225232
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1278693381
Short name T244
Test name
Test status
Simulation time 186698691158 ps
CPU time 436.44 seconds
Started Jul 24 07:13:26 PM PDT 24
Finished Jul 24 07:20:43 PM PDT 24
Peak memory 201252 kb
Host smart-1fa4e3e2-53bc-48f1-a9d4-2f121250f3e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278693381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1278693381
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1585430430
Short name T469
Test name
Test status
Simulation time 604177370593 ps
CPU time 1485.52 seconds
Started Jul 24 07:13:28 PM PDT 24
Finished Jul 24 07:38:13 PM PDT 24
Peak memory 201192 kb
Host smart-9ea27fe1-20e1-42c5-b3a7-e748e4e6da1f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585430430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1585430430
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2223211708
Short name T86
Test name
Test status
Simulation time 90618632442 ps
CPU time 408.26 seconds
Started Jul 24 07:13:26 PM PDT 24
Finished Jul 24 07:20:15 PM PDT 24
Peak memory 201704 kb
Host smart-72966451-d281-48f7-b3ed-8bbfa2ec202b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223211708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2223211708
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1106040196
Short name T553
Test name
Test status
Simulation time 28244370742 ps
CPU time 4.22 seconds
Started Jul 24 07:13:26 PM PDT 24
Finished Jul 24 07:13:30 PM PDT 24
Peak memory 201108 kb
Host smart-6de87de4-cb59-48b4-82c7-62f3362c1fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106040196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1106040196
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.4180252546
Short name T353
Test name
Test status
Simulation time 4638883024 ps
CPU time 9.24 seconds
Started Jul 24 07:13:27 PM PDT 24
Finished Jul 24 07:13:36 PM PDT 24
Peak memory 201020 kb
Host smart-e4858a10-54a4-4eee-89b7-27c282048a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180252546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.4180252546
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3844609181
Short name T671
Test name
Test status
Simulation time 6075404719 ps
CPU time 4.11 seconds
Started Jul 24 07:13:20 PM PDT 24
Finished Jul 24 07:13:24 PM PDT 24
Peak memory 201112 kb
Host smart-59f40862-cac1-42d8-925e-f7d056b9f53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844609181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3844609181
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3132978759
Short name T574
Test name
Test status
Simulation time 171263292603 ps
CPU time 117.24 seconds
Started Jul 24 07:13:34 PM PDT 24
Finished Jul 24 07:15:31 PM PDT 24
Peak memory 201220 kb
Host smart-794ef251-d067-4e00-8c5e-9c7c2e7ac6e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132978759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3132978759
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.4254681047
Short name T721
Test name
Test status
Simulation time 141140149833 ps
CPU time 85.3 seconds
Started Jul 24 07:13:27 PM PDT 24
Finished Jul 24 07:14:52 PM PDT 24
Peak memory 201376 kb
Host smart-534bcab3-b59d-45c2-884b-11cf37677a66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254681047 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.4254681047
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.696216234
Short name T64
Test name
Test status
Simulation time 521399327 ps
CPU time 1.23 seconds
Started Jul 24 07:13:43 PM PDT 24
Finished Jul 24 07:13:44 PM PDT 24
Peak memory 201064 kb
Host smart-2b77e714-0054-47e2-9da1-befc5b67d551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696216234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.696216234
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.4196430498
Short name T579
Test name
Test status
Simulation time 327142216145 ps
CPU time 479.43 seconds
Started Jul 24 07:13:38 PM PDT 24
Finished Jul 24 07:21:37 PM PDT 24
Peak memory 201320 kb
Host smart-79d38b9b-68c9-475c-8332-6c6d7d4c977e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196430498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.4196430498
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2846699274
Short name T284
Test name
Test status
Simulation time 494922826610 ps
CPU time 591.21 seconds
Started Jul 24 07:13:38 PM PDT 24
Finished Jul 24 07:23:29 PM PDT 24
Peak memory 201340 kb
Host smart-c1aac350-d699-46cb-8ae8-ca493faf66c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846699274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2846699274
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.948508680
Short name T421
Test name
Test status
Simulation time 494647431918 ps
CPU time 637.3 seconds
Started Jul 24 07:13:37 PM PDT 24
Finished Jul 24 07:24:14 PM PDT 24
Peak memory 201300 kb
Host smart-a0885e53-fbd5-41d1-adb7-354bb8f2ad53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=948508680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.948508680
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3805901543
Short name T320
Test name
Test status
Simulation time 328647119152 ps
CPU time 218.37 seconds
Started Jul 24 07:13:32 PM PDT 24
Finished Jul 24 07:17:10 PM PDT 24
Peak memory 201340 kb
Host smart-40cc9007-2495-4fbd-8b78-659b06bb6262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805901543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3805901543
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3802815475
Short name T785
Test name
Test status
Simulation time 325781007710 ps
CPU time 706.17 seconds
Started Jul 24 07:13:32 PM PDT 24
Finished Jul 24 07:25:18 PM PDT 24
Peak memory 201240 kb
Host smart-b5e1139f-4343-4f12-9d04-6d5c17989767
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802815475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3802815475
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.328780428
Short name T613
Test name
Test status
Simulation time 398080938870 ps
CPU time 225.67 seconds
Started Jul 24 07:13:39 PM PDT 24
Finished Jul 24 07:17:25 PM PDT 24
Peak memory 201224 kb
Host smart-22f88cfe-f57f-4125-bd10-877e77e7bdf0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328780428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.328780428
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2570724683
Short name T503
Test name
Test status
Simulation time 82999153025 ps
CPU time 277.05 seconds
Started Jul 24 07:13:50 PM PDT 24
Finished Jul 24 07:18:27 PM PDT 24
Peak memory 201680 kb
Host smart-44610d3c-6da4-4b3e-a7ef-bb6131aac03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570724683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2570724683
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2192347033
Short name T374
Test name
Test status
Simulation time 44527691468 ps
CPU time 54.12 seconds
Started Jul 24 07:13:46 PM PDT 24
Finished Jul 24 07:14:41 PM PDT 24
Peak memory 201084 kb
Host smart-aa95f45d-9247-4f93-8e84-e4a20bbdc2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192347033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2192347033
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1441718709
Short name T730
Test name
Test status
Simulation time 4613786484 ps
CPU time 3.35 seconds
Started Jul 24 07:13:47 PM PDT 24
Finished Jul 24 07:13:51 PM PDT 24
Peak memory 201072 kb
Host smart-f560d19f-22f9-43bf-8ebe-4cb6091d720a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441718709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1441718709
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.950510824
Short name T549
Test name
Test status
Simulation time 6092087130 ps
CPU time 4.12 seconds
Started Jul 24 07:13:34 PM PDT 24
Finished Jul 24 07:13:38 PM PDT 24
Peak memory 201120 kb
Host smart-ff569d88-e12f-4a58-a6de-7ba04eaaa673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950510824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.950510824
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2262060165
Short name T706
Test name
Test status
Simulation time 520655299439 ps
CPU time 559.98 seconds
Started Jul 24 07:13:47 PM PDT 24
Finished Jul 24 07:23:07 PM PDT 24
Peak memory 201260 kb
Host smart-6a332b54-907d-4432-b6cb-94a4e6766b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262060165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2262060165
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2398614155
Short name T583
Test name
Test status
Simulation time 244779015457 ps
CPU time 257.02 seconds
Started Jul 24 07:13:46 PM PDT 24
Finished Jul 24 07:18:04 PM PDT 24
Peak memory 210004 kb
Host smart-5edab9aa-843f-4df3-93de-67031acf937e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398614155 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2398614155
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1358225267
Short name T366
Test name
Test status
Simulation time 460381769 ps
CPU time 1.1 seconds
Started Jul 24 07:13:59 PM PDT 24
Finished Jul 24 07:14:01 PM PDT 24
Peak memory 201028 kb
Host smart-1b8130a7-989d-4cbf-a9b2-e4c32d481a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358225267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1358225267
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1850577906
Short name T92
Test name
Test status
Simulation time 550071982890 ps
CPU time 1082.54 seconds
Started Jul 24 07:13:56 PM PDT 24
Finished Jul 24 07:31:59 PM PDT 24
Peak memory 201320 kb
Host smart-cade002a-2ec1-4a21-afc2-610f8d330541
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850577906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1850577906
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3802302214
Short name T287
Test name
Test status
Simulation time 352277045112 ps
CPU time 395.16 seconds
Started Jul 24 07:13:52 PM PDT 24
Finished Jul 24 07:20:28 PM PDT 24
Peak memory 201296 kb
Host smart-4b5c9417-f3cf-4e8b-8f3b-2f319183e2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802302214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3802302214
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2628727786
Short name T184
Test name
Test status
Simulation time 325881398103 ps
CPU time 218.11 seconds
Started Jul 24 07:13:53 PM PDT 24
Finished Jul 24 07:17:31 PM PDT 24
Peak memory 201268 kb
Host smart-1702eafc-5ec9-4c27-abef-cedc264a6dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628727786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2628727786
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3647368178
Short name T683
Test name
Test status
Simulation time 334639759726 ps
CPU time 193.62 seconds
Started Jul 24 07:13:55 PM PDT 24
Finished Jul 24 07:17:09 PM PDT 24
Peak memory 201096 kb
Host smart-c246f506-06c8-4456-b9eb-23f668f1cf51
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647368178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3647368178
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2502482291
Short name T391
Test name
Test status
Simulation time 163842500800 ps
CPU time 377.25 seconds
Started Jul 24 07:13:53 PM PDT 24
Finished Jul 24 07:20:10 PM PDT 24
Peak memory 201228 kb
Host smart-905be0b1-ae7f-4726-9138-67ed8c405551
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502482291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2502482291
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1174819419
Short name T322
Test name
Test status
Simulation time 346580157174 ps
CPU time 190.91 seconds
Started Jul 24 07:13:53 PM PDT 24
Finished Jul 24 07:17:04 PM PDT 24
Peak memory 201216 kb
Host smart-296e169a-9b7a-47ec-98d4-58ada5adfae0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174819419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1174819419
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.101023216
Short name T738
Test name
Test status
Simulation time 412540218958 ps
CPU time 257.17 seconds
Started Jul 24 07:13:55 PM PDT 24
Finished Jul 24 07:18:12 PM PDT 24
Peak memory 201244 kb
Host smart-ca844e3d-e043-4b78-a197-c38f671d7bdf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101023216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.101023216
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1022808761
Short name T540
Test name
Test status
Simulation time 43172081512 ps
CPU time 32.04 seconds
Started Jul 24 07:13:52 PM PDT 24
Finished Jul 24 07:14:24 PM PDT 24
Peak memory 201088 kb
Host smart-9e540d89-2361-4d9f-b231-d2137d39e691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022808761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1022808761
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3186360137
Short name T460
Test name
Test status
Simulation time 4114216286 ps
CPU time 5.68 seconds
Started Jul 24 07:13:52 PM PDT 24
Finished Jul 24 07:13:58 PM PDT 24
Peak memory 201100 kb
Host smart-a64adbb7-d477-4615-8737-0d4c8cbdaa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186360137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3186360137
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2107950596
Short name T361
Test name
Test status
Simulation time 6037753649 ps
CPU time 7.39 seconds
Started Jul 24 07:13:48 PM PDT 24
Finished Jul 24 07:13:56 PM PDT 24
Peak memory 201104 kb
Host smart-a2d372e6-75d5-4854-9f33-075430da7445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107950596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2107950596
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.660081730
Short name T101
Test name
Test status
Simulation time 345458367577 ps
CPU time 405.97 seconds
Started Jul 24 07:13:59 PM PDT 24
Finished Jul 24 07:20:45 PM PDT 24
Peak memory 201360 kb
Host smart-6bafc3fd-43ba-4a26-9e16-66d855fe446c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660081730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
660081730
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3550922533
Short name T97
Test name
Test status
Simulation time 100455382381 ps
CPU time 187.14 seconds
Started Jul 24 07:13:57 PM PDT 24
Finished Jul 24 07:17:05 PM PDT 24
Peak memory 217440 kb
Host smart-d35128d0-e9c3-40c4-b224-a0778e8b117a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550922533 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3550922533
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.913984776
Short name T173
Test name
Test status
Simulation time 472279933 ps
CPU time 0.84 seconds
Started Jul 24 07:14:10 PM PDT 24
Finished Jul 24 07:14:11 PM PDT 24
Peak memory 201028 kb
Host smart-e2ff3cff-72be-4c6d-bf35-82de477087d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913984776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.913984776
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3921870545
Short name T331
Test name
Test status
Simulation time 539401242513 ps
CPU time 1333.94 seconds
Started Jul 24 07:14:06 PM PDT 24
Finished Jul 24 07:36:20 PM PDT 24
Peak memory 201212 kb
Host smart-6e3e316a-12ed-4d9c-852d-b568ce8f657e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921870545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3921870545
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3233668772
Short name T314
Test name
Test status
Simulation time 489413946197 ps
CPU time 505.6 seconds
Started Jul 24 07:14:04 PM PDT 24
Finished Jul 24 07:22:29 PM PDT 24
Peak memory 201316 kb
Host smart-cea119ef-cf49-4156-963c-d37befadd17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233668772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3233668772
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.693131876
Short name T694
Test name
Test status
Simulation time 322675039242 ps
CPU time 185.02 seconds
Started Jul 24 07:14:05 PM PDT 24
Finished Jul 24 07:17:10 PM PDT 24
Peak memory 201212 kb
Host smart-846004fb-aaa3-4660-85ba-2a466eb668ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=693131876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.693131876
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.535500088
Short name T548
Test name
Test status
Simulation time 324822571951 ps
CPU time 225.23 seconds
Started Jul 24 07:13:59 PM PDT 24
Finished Jul 24 07:17:44 PM PDT 24
Peak memory 201288 kb
Host smart-09abc6b5-ce7f-4595-894b-22f8b38adda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535500088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.535500088
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1070523765
Short name T552
Test name
Test status
Simulation time 165960977630 ps
CPU time 104.69 seconds
Started Jul 24 07:14:06 PM PDT 24
Finished Jul 24 07:15:51 PM PDT 24
Peak memory 201240 kb
Host smart-c0b6fe25-5f5f-479f-b3ad-b9d535a57548
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070523765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1070523765
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1455508651
Short name T130
Test name
Test status
Simulation time 174074427283 ps
CPU time 22.85 seconds
Started Jul 24 07:14:05 PM PDT 24
Finished Jul 24 07:14:28 PM PDT 24
Peak memory 201264 kb
Host smart-33e36fd4-c7a6-4b89-bbb7-15c4c831a2da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455508651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1455508651
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3082109523
Short name T480
Test name
Test status
Simulation time 196230536391 ps
CPU time 104.79 seconds
Started Jul 24 07:14:04 PM PDT 24
Finished Jul 24 07:15:49 PM PDT 24
Peak memory 201232 kb
Host smart-fe0b8276-9523-499b-b26c-7c2190e019d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082109523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3082109523
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1920723701
Short name T190
Test name
Test status
Simulation time 82991670920 ps
CPU time 283.63 seconds
Started Jul 24 07:14:11 PM PDT 24
Finished Jul 24 07:18:55 PM PDT 24
Peak memory 201696 kb
Host smart-8376e410-503b-4578-8670-95025d828412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920723701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1920723701
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2725523826
Short name T744
Test name
Test status
Simulation time 39916188695 ps
CPU time 12.28 seconds
Started Jul 24 07:14:12 PM PDT 24
Finished Jul 24 07:14:24 PM PDT 24
Peak memory 201068 kb
Host smart-e2002861-d2bb-404e-ab2b-fd179374bacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725523826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2725523826
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3929900535
Short name T742
Test name
Test status
Simulation time 3988222753 ps
CPU time 1.68 seconds
Started Jul 24 07:14:11 PM PDT 24
Finished Jul 24 07:14:12 PM PDT 24
Peak memory 201076 kb
Host smart-c68bad93-c209-4713-97a5-6e74e0ee5830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929900535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3929900535
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.775719796
Short name T394
Test name
Test status
Simulation time 5495820238 ps
CPU time 3.37 seconds
Started Jul 24 07:13:58 PM PDT 24
Finished Jul 24 07:14:02 PM PDT 24
Peak memory 201120 kb
Host smart-bc443bc7-813f-4dc3-8baa-d49d9c0c2d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775719796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.775719796
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3135925022
Short name T33
Test name
Test status
Simulation time 514099032499 ps
CPU time 289.18 seconds
Started Jul 24 07:14:12 PM PDT 24
Finished Jul 24 07:19:01 PM PDT 24
Peak memory 201232 kb
Host smart-f7e61ab0-4e2d-4d92-a43e-bc442513c1a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135925022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3135925022
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3125845820
Short name T22
Test name
Test status
Simulation time 90649456030 ps
CPU time 112.75 seconds
Started Jul 24 07:14:10 PM PDT 24
Finished Jul 24 07:16:03 PM PDT 24
Peak memory 211092 kb
Host smart-2903f8b2-3fbd-45ab-bef3-65f5123acd43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125845820 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3125845820
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1086720049
Short name T373
Test name
Test status
Simulation time 412453832 ps
CPU time 1.22 seconds
Started Jul 24 07:14:28 PM PDT 24
Finished Jul 24 07:14:29 PM PDT 24
Peak memory 201020 kb
Host smart-cae73550-e81a-40de-8aed-5aa1e172adf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086720049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1086720049
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1268390634
Short name T764
Test name
Test status
Simulation time 176219340744 ps
CPU time 22.77 seconds
Started Jul 24 07:14:16 PM PDT 24
Finished Jul 24 07:14:39 PM PDT 24
Peak memory 201284 kb
Host smart-73df9bd6-36fd-4705-9df4-729dccf93ebd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268390634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1268390634
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.135563226
Short name T787
Test name
Test status
Simulation time 488248635056 ps
CPU time 279.89 seconds
Started Jul 24 07:14:11 PM PDT 24
Finished Jul 24 07:18:51 PM PDT 24
Peak memory 201196 kb
Host smart-e2417528-e1a4-483d-aa01-ad08c4df653b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135563226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.135563226
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.4282632500
Short name T544
Test name
Test status
Simulation time 497081776436 ps
CPU time 1184.53 seconds
Started Jul 24 07:14:19 PM PDT 24
Finished Jul 24 07:34:04 PM PDT 24
Peak memory 201296 kb
Host smart-ff1146c7-7102-4387-9a31-35781da7d117
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282632500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.4282632500
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3295120798
Short name T606
Test name
Test status
Simulation time 483076205746 ps
CPU time 154.97 seconds
Started Jul 24 07:14:11 PM PDT 24
Finished Jul 24 07:16:46 PM PDT 24
Peak memory 201260 kb
Host smart-bd2f1d58-1e02-4b59-9073-515e8e85b1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295120798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3295120798
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3034379544
Short name T509
Test name
Test status
Simulation time 503753092967 ps
CPU time 1092.34 seconds
Started Jul 24 07:14:10 PM PDT 24
Finished Jul 24 07:32:22 PM PDT 24
Peak memory 201232 kb
Host smart-853d8fb6-f11a-402d-92fa-c208c55114aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034379544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3034379544
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1264537565
Short name T417
Test name
Test status
Simulation time 198155046452 ps
CPU time 472.83 seconds
Started Jul 24 07:14:18 PM PDT 24
Finished Jul 24 07:22:11 PM PDT 24
Peak memory 201240 kb
Host smart-e3f7d906-8135-47c5-be11-9e0f30613ab3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264537565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1264537565
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1552731361
Short name T383
Test name
Test status
Simulation time 116761780084 ps
CPU time 388.84 seconds
Started Jul 24 07:14:23 PM PDT 24
Finished Jul 24 07:20:52 PM PDT 24
Peak memory 201688 kb
Host smart-4a0415cf-8426-4dac-9174-7a578bcd5334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552731361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1552731361
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1277028617
Short name T467
Test name
Test status
Simulation time 41541137553 ps
CPU time 94.39 seconds
Started Jul 24 07:14:18 PM PDT 24
Finished Jul 24 07:15:52 PM PDT 24
Peak memory 201064 kb
Host smart-ff80f7e3-4d6a-42a6-9735-5a4265184c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277028617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1277028617
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3338850874
Short name T474
Test name
Test status
Simulation time 4278313099 ps
CPU time 9.96 seconds
Started Jul 24 07:14:15 PM PDT 24
Finished Jul 24 07:14:26 PM PDT 24
Peak memory 201040 kb
Host smart-2ddc61ff-7c7d-4175-bade-2f3856f29390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338850874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3338850874
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.101444694
Short name T693
Test name
Test status
Simulation time 6185863109 ps
CPU time 15.85 seconds
Started Jul 24 07:14:10 PM PDT 24
Finished Jul 24 07:14:26 PM PDT 24
Peak memory 201120 kb
Host smart-4335a121-c70f-4c94-b1a6-9e1e73250915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101444694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.101444694
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.4141515687
Short name T34
Test name
Test status
Simulation time 260394508476 ps
CPU time 43.05 seconds
Started Jul 24 07:14:23 PM PDT 24
Finished Jul 24 07:15:07 PM PDT 24
Peak memory 201232 kb
Host smart-32976638-b0a7-49aa-a8be-ef5ee2cf22a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141515687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.4141515687
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3404428483
Short name T668
Test name
Test status
Simulation time 107839533385 ps
CPU time 55.86 seconds
Started Jul 24 07:14:22 PM PDT 24
Finished Jul 24 07:15:18 PM PDT 24
Peak memory 209544 kb
Host smart-bbf6c5b3-9467-40bc-8afe-07252383263c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404428483 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3404428483
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.4154624445
Short name T431
Test name
Test status
Simulation time 532109500 ps
CPU time 0.91 seconds
Started Jul 24 07:14:36 PM PDT 24
Finished Jul 24 07:14:37 PM PDT 24
Peak memory 201008 kb
Host smart-51f16358-4416-4c58-8af6-90d3f93ae4e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154624445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.4154624445
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.125618936
Short name T779
Test name
Test status
Simulation time 512591115472 ps
CPU time 1204.01 seconds
Started Jul 24 07:14:29 PM PDT 24
Finished Jul 24 07:34:33 PM PDT 24
Peak memory 201268 kb
Host smart-b542c4f3-1bf6-4518-8576-fc62efec5ab6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125618936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.125618936
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3152234028
Short name T276
Test name
Test status
Simulation time 160749325268 ps
CPU time 93.86 seconds
Started Jul 24 07:14:37 PM PDT 24
Finished Jul 24 07:16:11 PM PDT 24
Peak memory 201244 kb
Host smart-a55b29d5-d642-46ad-b701-752d77e73499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152234028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3152234028
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3825476449
Short name T216
Test name
Test status
Simulation time 482925845009 ps
CPU time 539.37 seconds
Started Jul 24 07:14:22 PM PDT 24
Finished Jul 24 07:23:22 PM PDT 24
Peak memory 201284 kb
Host smart-39a751fe-da64-4c1d-b451-43527cdd8707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825476449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3825476449
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3427454190
Short name T479
Test name
Test status
Simulation time 493800769965 ps
CPU time 1060.12 seconds
Started Jul 24 07:14:30 PM PDT 24
Finished Jul 24 07:32:11 PM PDT 24
Peak memory 201304 kb
Host smart-ea9beacd-4368-441a-82be-fdc80d258a3d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427454190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3427454190
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1765139947
Short name T204
Test name
Test status
Simulation time 326342360191 ps
CPU time 785.87 seconds
Started Jul 24 07:14:24 PM PDT 24
Finished Jul 24 07:27:30 PM PDT 24
Peak memory 201336 kb
Host smart-0d33a568-f082-437f-8ad4-c51b68ca0bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765139947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1765139947
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.735963947
Short name T365
Test name
Test status
Simulation time 165007367572 ps
CPU time 372.71 seconds
Started Jul 24 07:14:29 PM PDT 24
Finished Jul 24 07:20:41 PM PDT 24
Peak memory 201220 kb
Host smart-e3586bc2-dcd5-4e28-8565-56041286716a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=735963947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.735963947
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.936864495
Short name T265
Test name
Test status
Simulation time 525737230949 ps
CPU time 300.31 seconds
Started Jul 24 07:14:29 PM PDT 24
Finished Jul 24 07:19:30 PM PDT 24
Peak memory 201320 kb
Host smart-60a481d6-656b-4c8d-8b93-479bb87db373
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936864495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.936864495
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2633971495
Short name T573
Test name
Test status
Simulation time 395204442359 ps
CPU time 873.01 seconds
Started Jul 24 07:14:33 PM PDT 24
Finished Jul 24 07:29:06 PM PDT 24
Peak memory 201244 kb
Host smart-484ed7a0-764a-4904-b8c8-23a6e218fed1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633971495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2633971495
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2556018620
Short name T196
Test name
Test status
Simulation time 71742868807 ps
CPU time 272.42 seconds
Started Jul 24 07:14:36 PM PDT 24
Finished Jul 24 07:19:08 PM PDT 24
Peak memory 201692 kb
Host smart-81eee96d-fd05-4b65-a57e-8e3667474eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556018620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2556018620
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1678287622
Short name T424
Test name
Test status
Simulation time 27563488472 ps
CPU time 66.42 seconds
Started Jul 24 07:14:35 PM PDT 24
Finished Jul 24 07:15:42 PM PDT 24
Peak memory 200940 kb
Host smart-2c6efbb6-44ef-4665-aa8d-898efbfc0f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678287622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1678287622
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.145071631
Short name T765
Test name
Test status
Simulation time 4058850163 ps
CPU time 9.54 seconds
Started Jul 24 07:14:35 PM PDT 24
Finished Jul 24 07:14:45 PM PDT 24
Peak memory 201080 kb
Host smart-29343f37-33e1-45d4-900d-e21ede2a74e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145071631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.145071631
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2258746960
Short name T80
Test name
Test status
Simulation time 6008979590 ps
CPU time 7.65 seconds
Started Jul 24 07:14:26 PM PDT 24
Finished Jul 24 07:14:33 PM PDT 24
Peak memory 201092 kb
Host smart-8caf6cf9-4ea7-4998-8b7f-e72e8d2a0902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258746960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2258746960
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3459462254
Short name T639
Test name
Test status
Simulation time 1789477849870 ps
CPU time 4251.76 seconds
Started Jul 24 07:14:36 PM PDT 24
Finished Jul 24 08:25:28 PM PDT 24
Peak memory 218168 kb
Host smart-53f306e5-393c-497b-83be-6c31feaebd88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459462254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3459462254
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2419311708
Short name T35
Test name
Test status
Simulation time 136581338070 ps
CPU time 390.81 seconds
Started Jul 24 07:14:37 PM PDT 24
Finished Jul 24 07:21:08 PM PDT 24
Peak memory 211052 kb
Host smart-5fb15954-9fe3-41bf-a4f0-537c640b9375
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419311708 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2419311708
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2785297824
Short name T642
Test name
Test status
Simulation time 499815256 ps
CPU time 1.2 seconds
Started Jul 24 07:10:15 PM PDT 24
Finished Jul 24 07:10:17 PM PDT 24
Peak memory 201060 kb
Host smart-64120342-8023-4b99-a288-2b3f6039fc14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785297824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2785297824
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1206844663
Short name T667
Test name
Test status
Simulation time 622326676316 ps
CPU time 1258.45 seconds
Started Jul 24 07:10:07 PM PDT 24
Finished Jul 24 07:31:06 PM PDT 24
Peak memory 201288 kb
Host smart-441700db-218d-4f2a-886a-e8a5880e4435
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206844663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1206844663
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.648437176
Short name T255
Test name
Test status
Simulation time 198196279288 ps
CPU time 435.94 seconds
Started Jul 24 07:10:04 PM PDT 24
Finished Jul 24 07:17:21 PM PDT 24
Peak memory 201184 kb
Host smart-cde2f3a8-97bf-45ea-850b-36c575da1cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648437176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.648437176
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3935146603
Short name T304
Test name
Test status
Simulation time 327433301513 ps
CPU time 800.9 seconds
Started Jul 24 07:10:13 PM PDT 24
Finished Jul 24 07:23:34 PM PDT 24
Peak memory 201204 kb
Host smart-5d2452e9-3b36-4d71-be11-9210fbb69ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935146603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3935146603
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1228686688
Short name T696
Test name
Test status
Simulation time 493933546753 ps
CPU time 1165.96 seconds
Started Jul 24 07:10:10 PM PDT 24
Finished Jul 24 07:29:36 PM PDT 24
Peak memory 201120 kb
Host smart-5cb229b9-4ea8-407e-b938-43c6c377c7c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228686688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1228686688
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1700721163
Short name T153
Test name
Test status
Simulation time 327890606027 ps
CPU time 44.92 seconds
Started Jul 24 07:10:07 PM PDT 24
Finished Jul 24 07:10:52 PM PDT 24
Peak memory 201252 kb
Host smart-d0866cbb-542b-474a-82c3-6d720d474519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700721163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1700721163
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.609909985
Short name T680
Test name
Test status
Simulation time 166247891963 ps
CPU time 70.35 seconds
Started Jul 24 07:10:11 PM PDT 24
Finished Jul 24 07:11:21 PM PDT 24
Peak memory 201232 kb
Host smart-459b8c2e-8329-46fd-bb83-a0eea4452e9c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=609909985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.609909985
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1036761743
Short name T527
Test name
Test status
Simulation time 354627008298 ps
CPU time 812.56 seconds
Started Jul 24 07:10:11 PM PDT 24
Finished Jul 24 07:23:44 PM PDT 24
Peak memory 201184 kb
Host smart-9a47db70-c352-4816-a8fd-3f96f443a6c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036761743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1036761743
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.47811208
Short name T512
Test name
Test status
Simulation time 422639773168 ps
CPU time 581.04 seconds
Started Jul 24 07:10:12 PM PDT 24
Finished Jul 24 07:19:53 PM PDT 24
Peak memory 201212 kb
Host smart-a684db29-41f9-4097-82f8-1f6c6bad1b96
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47811208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.ad
c_ctrl_filters_wakeup_fixed.47811208
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.249593102
Short name T756
Test name
Test status
Simulation time 109557732051 ps
CPU time 542.35 seconds
Started Jul 24 07:10:16 PM PDT 24
Finished Jul 24 07:19:19 PM PDT 24
Peak memory 201612 kb
Host smart-d854320d-12d6-4970-80c6-888347b45956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249593102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.249593102
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.761372105
Short name T397
Test name
Test status
Simulation time 34803240533 ps
CPU time 76.62 seconds
Started Jul 24 07:10:17 PM PDT 24
Finished Jul 24 07:11:34 PM PDT 24
Peak memory 201000 kb
Host smart-4b4d15dc-a872-463b-889e-2783a698b010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761372105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.761372105
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.711603273
Short name T160
Test name
Test status
Simulation time 5049555955 ps
CPU time 2.52 seconds
Started Jul 24 07:10:06 PM PDT 24
Finished Jul 24 07:10:08 PM PDT 24
Peak memory 201088 kb
Host smart-9aac5962-ad57-4804-8863-6148383bc5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711603273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.711603273
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3150289716
Short name T72
Test name
Test status
Simulation time 4277718202 ps
CPU time 3.11 seconds
Started Jul 24 07:10:16 PM PDT 24
Finished Jul 24 07:10:19 PM PDT 24
Peak memory 216848 kb
Host smart-49339b6e-9a5d-4760-977d-8f8ca1265adf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150289716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3150289716
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.153796191
Short name T425
Test name
Test status
Simulation time 5933736010 ps
CPU time 3.25 seconds
Started Jul 24 07:10:07 PM PDT 24
Finished Jul 24 07:10:10 PM PDT 24
Peak memory 201132 kb
Host smart-9445b93f-2c03-432b-ac9a-139358bc029b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153796191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.153796191
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.396487258
Short name T595
Test name
Test status
Simulation time 232397612423 ps
CPU time 260.03 seconds
Started Jul 24 07:10:13 PM PDT 24
Finished Jul 24 07:14:33 PM PDT 24
Peak memory 201264 kb
Host smart-cfa56019-636b-49ec-b6b9-871092389377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396487258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.396487258
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2829457724
Short name T575
Test name
Test status
Simulation time 405731108 ps
CPU time 0.86 seconds
Started Jul 24 07:14:49 PM PDT 24
Finished Jul 24 07:14:50 PM PDT 24
Peak memory 201008 kb
Host smart-ddce3c06-e858-4d19-b642-ec0b99ce9fe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829457724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2829457724
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2809139371
Short name T165
Test name
Test status
Simulation time 503425692818 ps
CPU time 285.4 seconds
Started Jul 24 07:14:42 PM PDT 24
Finished Jul 24 07:19:28 PM PDT 24
Peak memory 201288 kb
Host smart-a402d3cf-29c7-495d-8789-0d97a4a161b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809139371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2809139371
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1868551287
Short name T562
Test name
Test status
Simulation time 488983798734 ps
CPU time 278.37 seconds
Started Jul 24 07:14:41 PM PDT 24
Finished Jul 24 07:19:20 PM PDT 24
Peak memory 201428 kb
Host smart-f683e975-03fd-4a96-b742-0dd94204df9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868551287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1868551287
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.370206746
Short name T294
Test name
Test status
Simulation time 493394264451 ps
CPU time 254.5 seconds
Started Jul 24 07:14:37 PM PDT 24
Finished Jul 24 07:18:51 PM PDT 24
Peak memory 201296 kb
Host smart-f0dafac4-4993-4116-9f0e-856f231b85da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370206746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.370206746
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3429193242
Short name T588
Test name
Test status
Simulation time 325222212878 ps
CPU time 199.9 seconds
Started Jul 24 07:14:35 PM PDT 24
Finished Jul 24 07:17:55 PM PDT 24
Peak memory 201296 kb
Host smart-102fc544-a3d6-4bfa-82d6-6d518c93c74a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429193242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3429193242
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3006506254
Short name T333
Test name
Test status
Simulation time 558933369453 ps
CPU time 156.6 seconds
Started Jul 24 07:14:42 PM PDT 24
Finished Jul 24 07:17:19 PM PDT 24
Peak memory 201280 kb
Host smart-3d767de6-35a3-4d51-8361-6b859daaee14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006506254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3006506254
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1447216085
Short name T650
Test name
Test status
Simulation time 397379221105 ps
CPU time 250.39 seconds
Started Jul 24 07:14:42 PM PDT 24
Finished Jul 24 07:18:53 PM PDT 24
Peak memory 201244 kb
Host smart-70ca50fb-b0de-489c-9207-862c07af0623
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447216085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1447216085
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1328176351
Short name T413
Test name
Test status
Simulation time 87321335371 ps
CPU time 333.16 seconds
Started Jul 24 07:14:43 PM PDT 24
Finished Jul 24 07:20:17 PM PDT 24
Peak memory 201680 kb
Host smart-11bb62d2-67bb-41cc-b877-990bf6bfd25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328176351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1328176351
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.4283804350
Short name T76
Test name
Test status
Simulation time 22855586337 ps
CPU time 54.01 seconds
Started Jul 24 07:14:44 PM PDT 24
Finished Jul 24 07:15:38 PM PDT 24
Peak memory 201088 kb
Host smart-a777b24c-a4b0-4609-889e-1cb1fdec8a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283804350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.4283804350
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1159156821
Short name T536
Test name
Test status
Simulation time 4201995586 ps
CPU time 10.36 seconds
Started Jul 24 07:14:41 PM PDT 24
Finished Jul 24 07:14:52 PM PDT 24
Peak memory 201116 kb
Host smart-6ca6ea99-f306-40e2-b6a5-acd04f10128d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159156821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1159156821
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3896333950
Short name T734
Test name
Test status
Simulation time 5614865894 ps
CPU time 14.13 seconds
Started Jul 24 07:14:35 PM PDT 24
Finished Jul 24 07:14:50 PM PDT 24
Peak memory 201116 kb
Host smart-1d98b0dc-b61a-4b76-80a2-6aa8970f38bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896333950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3896333950
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.4219735658
Short name T183
Test name
Test status
Simulation time 236675588771 ps
CPU time 116.06 seconds
Started Jul 24 07:14:48 PM PDT 24
Finished Jul 24 07:16:44 PM PDT 24
Peak memory 201300 kb
Host smart-cf9f43a4-22e5-4102-a1b5-8711f14f53ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219735658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.4219735658
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1545071730
Short name T723
Test name
Test status
Simulation time 465871874 ps
CPU time 0.68 seconds
Started Jul 24 07:14:55 PM PDT 24
Finished Jul 24 07:14:55 PM PDT 24
Peak memory 201048 kb
Host smart-f3c1bf43-7333-42cd-ac2d-89a7004b3317
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545071730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1545071730
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3523047293
Short name T224
Test name
Test status
Simulation time 353970953209 ps
CPU time 386.44 seconds
Started Jul 24 07:14:48 PM PDT 24
Finished Jul 24 07:21:14 PM PDT 24
Peak memory 201228 kb
Host smart-d9fdaec8-2e6f-4d5f-93f1-ebb3ebe46e23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523047293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3523047293
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3462390484
Short name T710
Test name
Test status
Simulation time 497874666408 ps
CPU time 509.97 seconds
Started Jul 24 07:14:50 PM PDT 24
Finished Jul 24 07:23:20 PM PDT 24
Peak memory 201236 kb
Host smart-21e7b053-eb12-4056-869c-5b0ebb376e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462390484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3462390484
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3295561725
Short name T246
Test name
Test status
Simulation time 165676938781 ps
CPU time 186.25 seconds
Started Jul 24 07:14:48 PM PDT 24
Finished Jul 24 07:17:55 PM PDT 24
Peak memory 201276 kb
Host smart-9ab55650-4ac2-44e6-be03-400f333be487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295561725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3295561725
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3389498621
Short name T477
Test name
Test status
Simulation time 162515004372 ps
CPU time 103.26 seconds
Started Jul 24 07:14:48 PM PDT 24
Finished Jul 24 07:16:31 PM PDT 24
Peak memory 201224 kb
Host smart-336012f4-3e56-4c36-9e83-cb8e4dddf2ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389498621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3389498621
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2868549678
Short name T300
Test name
Test status
Simulation time 494843365347 ps
CPU time 1169.2 seconds
Started Jul 24 07:14:49 PM PDT 24
Finished Jul 24 07:34:18 PM PDT 24
Peak memory 201232 kb
Host smart-5e97147e-3288-4d21-9a1a-9291166ee837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868549678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2868549678
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.4168804947
Short name T485
Test name
Test status
Simulation time 325149148265 ps
CPU time 772.34 seconds
Started Jul 24 07:14:49 PM PDT 24
Finished Jul 24 07:27:42 PM PDT 24
Peak memory 201208 kb
Host smart-e31dff50-d0ed-487d-be4a-4d143094803d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168804947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.4168804947
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2388412086
Short name T786
Test name
Test status
Simulation time 557795634949 ps
CPU time 557.21 seconds
Started Jul 24 07:14:48 PM PDT 24
Finished Jul 24 07:24:06 PM PDT 24
Peak memory 201292 kb
Host smart-7092ff5f-e370-4336-b6d0-5995d6f10d06
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388412086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2388412086
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.4277809627
Short name T414
Test name
Test status
Simulation time 397316023209 ps
CPU time 484.94 seconds
Started Jul 24 07:14:50 PM PDT 24
Finished Jul 24 07:22:55 PM PDT 24
Peak memory 201288 kb
Host smart-e0e580c7-ab38-491f-a34c-9533bde8dce3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277809627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.4277809627
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.672006461
Short name T7
Test name
Test status
Simulation time 105193290751 ps
CPU time 281.71 seconds
Started Jul 24 07:14:56 PM PDT 24
Finished Jul 24 07:19:38 PM PDT 24
Peak memory 201744 kb
Host smart-995a2c03-29bd-46b6-b4b2-c5534d7ec52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672006461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.672006461
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2033737261
Short name T494
Test name
Test status
Simulation time 31535350785 ps
CPU time 36.94 seconds
Started Jul 24 07:14:50 PM PDT 24
Finished Jul 24 07:15:27 PM PDT 24
Peak memory 201084 kb
Host smart-3de8740e-9c26-4690-a22c-863dde66b049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033737261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2033737261
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.4086303357
Short name T381
Test name
Test status
Simulation time 4697554540 ps
CPU time 12.01 seconds
Started Jul 24 07:14:48 PM PDT 24
Finished Jul 24 07:15:00 PM PDT 24
Peak memory 201092 kb
Host smart-3d439c2d-4f4a-4469-beb5-b9e0b04ce09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086303357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.4086303357
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3241296142
Short name T491
Test name
Test status
Simulation time 5869309290 ps
CPU time 7.44 seconds
Started Jul 24 07:14:48 PM PDT 24
Finished Jul 24 07:14:56 PM PDT 24
Peak memory 201072 kb
Host smart-ce9c8c65-3414-4aad-aba9-0784917ae709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241296142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3241296142
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1555065042
Short name T247
Test name
Test status
Simulation time 388221069836 ps
CPU time 156.09 seconds
Started Jul 24 07:14:56 PM PDT 24
Finished Jul 24 07:17:32 PM PDT 24
Peak memory 201232 kb
Host smart-50847108-bd32-444a-954b-8e5cb51ca287
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555065042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1555065042
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.354982461
Short name T663
Test name
Test status
Simulation time 465350965 ps
CPU time 1.81 seconds
Started Jul 24 07:15:07 PM PDT 24
Finished Jul 24 07:15:09 PM PDT 24
Peak memory 200988 kb
Host smart-31455f5e-410f-41b7-90e2-660859866eb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354982461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.354982461
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3811071476
Short name T682
Test name
Test status
Simulation time 162620565980 ps
CPU time 98.85 seconds
Started Jul 24 07:15:02 PM PDT 24
Finished Jul 24 07:16:40 PM PDT 24
Peak memory 201220 kb
Host smart-29193d69-3e6f-4709-96c3-dc6124434944
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811071476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3811071476
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.22396824
Short name T215
Test name
Test status
Simulation time 560489493957 ps
CPU time 738.76 seconds
Started Jul 24 07:15:07 PM PDT 24
Finished Jul 24 07:27:26 PM PDT 24
Peak memory 201228 kb
Host smart-1d4aee08-b90d-4d71-9f62-d933b4697a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22396824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.22396824
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2122639559
Short name T578
Test name
Test status
Simulation time 499794583055 ps
CPU time 596.39 seconds
Started Jul 24 07:15:04 PM PDT 24
Finished Jul 24 07:25:01 PM PDT 24
Peak memory 201284 kb
Host smart-9eb96bea-3f10-4eda-9f4a-865480bcb377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122639559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2122639559
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2823683330
Short name T450
Test name
Test status
Simulation time 165468195932 ps
CPU time 361.53 seconds
Started Jul 24 07:15:01 PM PDT 24
Finished Jul 24 07:21:03 PM PDT 24
Peak memory 201224 kb
Host smart-7c429cac-3071-4bf5-a398-eb9b012421d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823683330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2823683330
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1924542078
Short name T277
Test name
Test status
Simulation time 335540504884 ps
CPU time 354.91 seconds
Started Jul 24 07:15:00 PM PDT 24
Finished Jul 24 07:20:55 PM PDT 24
Peak memory 201288 kb
Host smart-3a1ccf12-8a48-474b-9325-1f48abe9e79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924542078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1924542078
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3287950299
Short name T659
Test name
Test status
Simulation time 320788730320 ps
CPU time 218.93 seconds
Started Jul 24 07:15:01 PM PDT 24
Finished Jul 24 07:18:40 PM PDT 24
Peak memory 201268 kb
Host smart-187aace5-6659-43cb-8af7-41a5854a743a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287950299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3287950299
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3236566205
Short name T238
Test name
Test status
Simulation time 169051021070 ps
CPU time 181.25 seconds
Started Jul 24 07:15:05 PM PDT 24
Finished Jul 24 07:18:06 PM PDT 24
Peak memory 201208 kb
Host smart-5c8ca273-039a-4ebc-ad59-961c49bd5b64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236566205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3236566205
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.696815892
Short name T134
Test name
Test status
Simulation time 203584218563 ps
CPU time 122.33 seconds
Started Jul 24 07:15:01 PM PDT 24
Finished Jul 24 07:17:03 PM PDT 24
Peak memory 201236 kb
Host smart-3f1d777b-be3e-4e2b-9923-b7620ecb188f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696815892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.696815892
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.544763844
Short name T684
Test name
Test status
Simulation time 97564292716 ps
CPU time 412.38 seconds
Started Jul 24 07:15:05 PM PDT 24
Finished Jul 24 07:21:58 PM PDT 24
Peak memory 201704 kb
Host smart-0e72f6a0-ffcc-44cd-9dbf-021ca3749c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544763844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.544763844
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2779118150
Short name T616
Test name
Test status
Simulation time 38316990188 ps
CPU time 22.17 seconds
Started Jul 24 07:15:06 PM PDT 24
Finished Jul 24 07:15:28 PM PDT 24
Peak memory 201068 kb
Host smart-c0335b4b-fc86-4fa0-b6a7-77198c47459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779118150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2779118150
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.96915074
Short name T380
Test name
Test status
Simulation time 2766129292 ps
CPU time 7.35 seconds
Started Jul 24 07:15:06 PM PDT 24
Finished Jul 24 07:15:13 PM PDT 24
Peak memory 201112 kb
Host smart-1d073cc5-d94e-4307-a6b5-3b06f78161a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96915074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.96915074
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.512074351
Short name T416
Test name
Test status
Simulation time 5623939727 ps
CPU time 2.36 seconds
Started Jul 24 07:15:04 PM PDT 24
Finished Jul 24 07:15:07 PM PDT 24
Peak memory 201084 kb
Host smart-997e06e1-e49f-4b85-9d38-f0cab21b6250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512074351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.512074351
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.4040887694
Short name T622
Test name
Test status
Simulation time 203387676633 ps
CPU time 482.16 seconds
Started Jul 24 07:15:05 PM PDT 24
Finished Jul 24 07:23:08 PM PDT 24
Peak memory 201200 kb
Host smart-98ae6171-0657-4969-9235-36ba45822348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040887694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.4040887694
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1126507366
Short name T747
Test name
Test status
Simulation time 70873627871 ps
CPU time 147.65 seconds
Started Jul 24 07:15:07 PM PDT 24
Finished Jul 24 07:17:35 PM PDT 24
Peak memory 217680 kb
Host smart-c30217fb-4571-45a8-8b2e-571fbfdb0988
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126507366 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1126507366
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.4047059869
Short name T376
Test name
Test status
Simulation time 515690924 ps
CPU time 1.71 seconds
Started Jul 24 07:15:23 PM PDT 24
Finished Jul 24 07:15:25 PM PDT 24
Peak memory 200988 kb
Host smart-01feb3ad-860c-43d9-8612-a197c4314145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047059869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.4047059869
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.897106653
Short name T660
Test name
Test status
Simulation time 166061850873 ps
CPU time 128.4 seconds
Started Jul 24 07:15:16 PM PDT 24
Finished Jul 24 07:17:25 PM PDT 24
Peak memory 201192 kb
Host smart-cc5cac4f-7406-45f4-9023-e9f7a44853c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897106653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.897106653
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.775043106
Short name T504
Test name
Test status
Simulation time 323646373380 ps
CPU time 336.57 seconds
Started Jul 24 07:15:13 PM PDT 24
Finished Jul 24 07:20:50 PM PDT 24
Peak memory 201256 kb
Host smart-de2d0975-d1b7-4bf6-8c2f-130707ebbc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775043106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.775043106
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2705894035
Short name T570
Test name
Test status
Simulation time 332788544835 ps
CPU time 710.58 seconds
Started Jul 24 07:15:16 PM PDT 24
Finished Jul 24 07:27:07 PM PDT 24
Peak memory 201176 kb
Host smart-20d2fb96-2ce6-4e69-9f09-67537172c230
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705894035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2705894035
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2795753505
Short name T203
Test name
Test status
Simulation time 165783837752 ps
CPU time 97.88 seconds
Started Jul 24 07:15:12 PM PDT 24
Finished Jul 24 07:16:50 PM PDT 24
Peak memory 201252 kb
Host smart-16612a41-066b-4e7f-9cc4-6e67de519e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795753505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2795753505
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3763423359
Short name T594
Test name
Test status
Simulation time 487599570202 ps
CPU time 301.01 seconds
Started Jul 24 07:15:14 PM PDT 24
Finished Jul 24 07:20:15 PM PDT 24
Peak memory 201212 kb
Host smart-48c743c9-12de-45e0-b7de-5103f217ee4a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763423359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3763423359
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1404072876
Short name T368
Test name
Test status
Simulation time 391421909821 ps
CPU time 254.67 seconds
Started Jul 24 07:15:13 PM PDT 24
Finished Jul 24 07:19:28 PM PDT 24
Peak memory 201260 kb
Host smart-379aecd9-b515-44a1-92c1-0066d7aa7ec5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404072876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1404072876
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3563686154
Short name T565
Test name
Test status
Simulation time 81821004936 ps
CPU time 285.34 seconds
Started Jul 24 07:15:20 PM PDT 24
Finished Jul 24 07:20:05 PM PDT 24
Peak memory 201672 kb
Host smart-bb20c1c7-00f6-490e-845a-ca5797c4f7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563686154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3563686154
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2406376480
Short name T531
Test name
Test status
Simulation time 30223285704 ps
CPU time 18.37 seconds
Started Jul 24 07:15:15 PM PDT 24
Finished Jul 24 07:15:34 PM PDT 24
Peak memory 201044 kb
Host smart-e865ffa2-e22d-416f-a7a8-a9ec7d5b87ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406376480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2406376480
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1127274105
Short name T458
Test name
Test status
Simulation time 3695702762 ps
CPU time 7.34 seconds
Started Jul 24 07:15:13 PM PDT 24
Finished Jul 24 07:15:20 PM PDT 24
Peak memory 201048 kb
Host smart-a4d6ffee-3db8-4738-9ecc-f5db7069a256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127274105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1127274105
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1268401478
Short name T405
Test name
Test status
Simulation time 5941440660 ps
CPU time 4.62 seconds
Started Jul 24 07:15:06 PM PDT 24
Finished Jul 24 07:15:10 PM PDT 24
Peak memory 200996 kb
Host smart-fcc8e09b-635c-4bd2-aa30-ebd7fa788e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268401478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1268401478
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3410812141
Short name T500
Test name
Test status
Simulation time 393175639 ps
CPU time 1.12 seconds
Started Jul 24 07:15:39 PM PDT 24
Finished Jul 24 07:15:40 PM PDT 24
Peak memory 201020 kb
Host smart-5a4a5811-e363-4a80-a95d-2ef2c37be745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410812141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3410812141
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1192965042
Short name T711
Test name
Test status
Simulation time 168556133893 ps
CPU time 397.42 seconds
Started Jul 24 07:15:29 PM PDT 24
Finished Jul 24 07:22:07 PM PDT 24
Peak memory 201196 kb
Host smart-384826f8-693e-4a97-b2ec-e7b31432e358
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192965042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1192965042
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3884341407
Short name T633
Test name
Test status
Simulation time 160865011779 ps
CPU time 125.94 seconds
Started Jul 24 07:15:19 PM PDT 24
Finished Jul 24 07:17:25 PM PDT 24
Peak memory 201256 kb
Host smart-4126db24-0b1d-4856-86e9-ee4ca751d91a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884341407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3884341407
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3811687718
Short name T590
Test name
Test status
Simulation time 168813974621 ps
CPU time 387.91 seconds
Started Jul 24 07:15:20 PM PDT 24
Finished Jul 24 07:21:48 PM PDT 24
Peak memory 201252 kb
Host smart-6807b6ac-47c7-41d4-be53-3587141b6db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811687718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3811687718
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2046835566
Short name T646
Test name
Test status
Simulation time 491333526475 ps
CPU time 1074.87 seconds
Started Jul 24 07:15:18 PM PDT 24
Finished Jul 24 07:33:13 PM PDT 24
Peak memory 201296 kb
Host smart-a4070066-a0c2-4087-840a-6257f8bec63f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046835566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2046835566
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2015979083
Short name T673
Test name
Test status
Simulation time 360427444277 ps
CPU time 449.3 seconds
Started Jul 24 07:15:29 PM PDT 24
Finished Jul 24 07:22:58 PM PDT 24
Peak memory 201236 kb
Host smart-c5e96db9-697d-4d19-ba91-4a701bc37ed1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015979083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2015979083
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2062048788
Short name T415
Test name
Test status
Simulation time 207189602117 ps
CPU time 102.17 seconds
Started Jul 24 07:15:27 PM PDT 24
Finished Jul 24 07:17:09 PM PDT 24
Peak memory 201256 kb
Host smart-cd96c611-1fc5-4437-b7a7-ae8c3a361a26
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062048788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2062048788
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2268458095
Short name T780
Test name
Test status
Simulation time 98302107137 ps
CPU time 331.37 seconds
Started Jul 24 07:15:33 PM PDT 24
Finished Jul 24 07:21:04 PM PDT 24
Peak memory 201720 kb
Host smart-743a7a41-ec7b-459a-96c8-c373a4622564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268458095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2268458095
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1756512096
Short name T363
Test name
Test status
Simulation time 31497547363 ps
CPU time 18.67 seconds
Started Jul 24 07:15:56 PM PDT 24
Finished Jul 24 07:16:15 PM PDT 24
Peak memory 201064 kb
Host smart-d3f8a565-89c2-46b7-af1e-ae49804aedcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756512096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1756512096
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2146331236
Short name T653
Test name
Test status
Simulation time 3563587719 ps
CPU time 7.73 seconds
Started Jul 24 07:15:33 PM PDT 24
Finished Jul 24 07:15:41 PM PDT 24
Peak memory 201092 kb
Host smart-65ae3824-70ff-463e-9917-b89fdbb3224c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146331236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2146331236
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.444539351
Short name T420
Test name
Test status
Simulation time 5559381316 ps
CPU time 3.6 seconds
Started Jul 24 07:15:21 PM PDT 24
Finished Jul 24 07:15:25 PM PDT 24
Peak memory 201068 kb
Host smart-874268b6-15e6-4516-9f90-c877bb304576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444539351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.444539351
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1591904358
Short name T139
Test name
Test status
Simulation time 484204931041 ps
CPU time 1029.82 seconds
Started Jul 24 07:15:32 PM PDT 24
Finished Jul 24 07:32:42 PM PDT 24
Peak memory 209872 kb
Host smart-722f321a-6e17-463c-8474-b389b5f5469a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591904358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1591904358
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.431265346
Short name T763
Test name
Test status
Simulation time 63632084312 ps
CPU time 146.14 seconds
Started Jul 24 07:15:53 PM PDT 24
Finished Jul 24 07:18:19 PM PDT 24
Peak memory 216420 kb
Host smart-dc4020af-dedd-4def-8431-08c22b94f914
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431265346 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.431265346
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3111755428
Short name T362
Test name
Test status
Simulation time 526179697 ps
CPU time 1.75 seconds
Started Jul 24 07:15:48 PM PDT 24
Finished Jul 24 07:15:50 PM PDT 24
Peak memory 201012 kb
Host smart-e677c74e-8b41-49a4-9271-5cfcbc8f5a90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111755428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3111755428
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1169396394
Short name T78
Test name
Test status
Simulation time 188229781270 ps
CPU time 383.85 seconds
Started Jul 24 07:15:41 PM PDT 24
Finished Jul 24 07:22:05 PM PDT 24
Peak memory 201192 kb
Host smart-15f740b1-b0f4-438a-86a8-c1f54a2adb6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169396394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1169396394
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1875793472
Short name T225
Test name
Test status
Simulation time 348116811911 ps
CPU time 229.87 seconds
Started Jul 24 07:15:59 PM PDT 24
Finished Jul 24 07:19:49 PM PDT 24
Peak memory 201260 kb
Host smart-639e2a29-21b0-411c-be5d-6246435f1609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875793472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1875793472
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.351038565
Short name T228
Test name
Test status
Simulation time 162952850134 ps
CPU time 94.96 seconds
Started Jul 24 07:15:41 PM PDT 24
Finished Jul 24 07:17:16 PM PDT 24
Peak memory 201344 kb
Host smart-4f917352-c50f-4eef-b721-6efcca36d8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351038565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.351038565
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1358517099
Short name T627
Test name
Test status
Simulation time 483322877729 ps
CPU time 872.7 seconds
Started Jul 24 07:15:41 PM PDT 24
Finished Jul 24 07:30:13 PM PDT 24
Peak memory 201288 kb
Host smart-2f4f3b06-a5e6-4203-974c-b9c0312c368a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358517099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1358517099
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.755915388
Short name T302
Test name
Test status
Simulation time 159371961761 ps
CPU time 90.3 seconds
Started Jul 24 07:15:43 PM PDT 24
Finished Jul 24 07:17:14 PM PDT 24
Peak memory 201212 kb
Host smart-907f187f-d0d1-4007-b86b-8c17bdba5fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755915388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.755915388
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2950442254
Short name T717
Test name
Test status
Simulation time 168398989872 ps
CPU time 397.42 seconds
Started Jul 24 07:15:41 PM PDT 24
Finished Jul 24 07:22:18 PM PDT 24
Peak memory 201212 kb
Host smart-f6310a8d-c0d0-4ab0-9894-df9aa60c6bde
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950442254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2950442254
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.473020384
Short name T634
Test name
Test status
Simulation time 218257501575 ps
CPU time 193.37 seconds
Started Jul 24 07:15:40 PM PDT 24
Finished Jul 24 07:18:53 PM PDT 24
Peak memory 201280 kb
Host smart-3fe0136a-0721-46a0-a625-08a036ae8773
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473020384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_
wakeup.473020384
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2669982254
Short name T453
Test name
Test status
Simulation time 407535835134 ps
CPU time 244.94 seconds
Started Jul 24 07:15:40 PM PDT 24
Finished Jul 24 07:19:45 PM PDT 24
Peak memory 201220 kb
Host smart-914c2a4c-ceaf-410c-bf28-e2bc77fd5f7e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669982254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2669982254
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3881984929
Short name T617
Test name
Test status
Simulation time 37671846183 ps
CPU time 9.98 seconds
Started Jul 24 07:15:51 PM PDT 24
Finished Jul 24 07:16:01 PM PDT 24
Peak memory 201092 kb
Host smart-ef34956a-3140-408e-a09f-bae031c09b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881984929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3881984929
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.1048728607
Short name T447
Test name
Test status
Simulation time 4968112593 ps
CPU time 3.29 seconds
Started Jul 24 07:15:45 PM PDT 24
Finished Jul 24 07:15:49 PM PDT 24
Peak memory 201176 kb
Host smart-64eb03f0-416a-417e-aff1-7cdab6dd3770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048728607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1048728607
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2524055803
Short name T48
Test name
Test status
Simulation time 5821684090 ps
CPU time 4.36 seconds
Started Jul 24 07:15:39 PM PDT 24
Finished Jul 24 07:15:44 PM PDT 24
Peak memory 201096 kb
Host smart-1178d7e3-fc15-4847-afa4-4a3712668bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524055803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2524055803
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2536598110
Short name T670
Test name
Test status
Simulation time 283479621344 ps
CPU time 335.34 seconds
Started Jul 24 07:15:47 PM PDT 24
Finished Jul 24 07:21:23 PM PDT 24
Peak memory 201696 kb
Host smart-7e49d34f-5a84-4854-b9e4-484115652525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536598110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2536598110
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3743517791
Short name T84
Test name
Test status
Simulation time 21165377925 ps
CPU time 72.21 seconds
Started Jul 24 07:15:47 PM PDT 24
Finished Jul 24 07:17:00 PM PDT 24
Peak memory 210252 kb
Host smart-64af196c-9efd-4b5e-af8b-fc227233ffb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743517791 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3743517791
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.4072130645
Short name T452
Test name
Test status
Simulation time 536132669 ps
CPU time 0.95 seconds
Started Jul 24 07:16:00 PM PDT 24
Finished Jul 24 07:16:01 PM PDT 24
Peak memory 201060 kb
Host smart-470f4ba9-14cf-4f26-aa40-9adae2206c5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072130645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.4072130645
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1005982818
Short name T211
Test name
Test status
Simulation time 191060197545 ps
CPU time 436.16 seconds
Started Jul 24 07:15:55 PM PDT 24
Finished Jul 24 07:23:12 PM PDT 24
Peak memory 201244 kb
Host smart-d6aadaa4-67ba-43a0-8474-d9064f61f89e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005982818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1005982818
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.594073911
Short name T757
Test name
Test status
Simulation time 165052322356 ps
CPU time 203.89 seconds
Started Jul 24 07:15:53 PM PDT 24
Finished Jul 24 07:19:17 PM PDT 24
Peak memory 201288 kb
Host smart-7f0f3114-93ed-4855-9283-ec42a021ffc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594073911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.594073911
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3786108009
Short name T382
Test name
Test status
Simulation time 491139847328 ps
CPU time 1129.44 seconds
Started Jul 24 07:15:54 PM PDT 24
Finished Jul 24 07:34:44 PM PDT 24
Peak memory 201208 kb
Host smart-ae0ffd85-0dc9-498a-a01b-04d7d85297b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786108009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3786108009
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.768665896
Short name T245
Test name
Test status
Simulation time 162349433220 ps
CPU time 89.02 seconds
Started Jul 24 07:16:06 PM PDT 24
Finished Jul 24 07:17:35 PM PDT 24
Peak memory 201256 kb
Host smart-edfe7ab1-428e-49fb-a9d6-d75f83ba73c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768665896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.768665896
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1410208146
Short name T592
Test name
Test status
Simulation time 494786657705 ps
CPU time 186.64 seconds
Started Jul 24 07:15:52 PM PDT 24
Finished Jul 24 07:18:59 PM PDT 24
Peak memory 201252 kb
Host smart-11899b8a-61bf-4c68-9920-de6729d4ba2e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410208146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1410208146
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.4132425904
Short name T281
Test name
Test status
Simulation time 522943617980 ps
CPU time 288.6 seconds
Started Jul 24 07:15:54 PM PDT 24
Finished Jul 24 07:20:43 PM PDT 24
Peak memory 201116 kb
Host smart-f31df3b7-6ded-4924-b323-952b8205399d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132425904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.4132425904
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1081948388
Short name T400
Test name
Test status
Simulation time 199160094053 ps
CPU time 417.23 seconds
Started Jul 24 07:15:53 PM PDT 24
Finished Jul 24 07:22:51 PM PDT 24
Peak memory 201228 kb
Host smart-89a3fa8a-4772-456e-8f35-94356af2cdb3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081948388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1081948388
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3328562661
Short name T188
Test name
Test status
Simulation time 74451135912 ps
CPU time 391.43 seconds
Started Jul 24 07:16:00 PM PDT 24
Finished Jul 24 07:22:31 PM PDT 24
Peak memory 201712 kb
Host smart-6d112c68-f8e7-4505-bbae-c466521720be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328562661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3328562661
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2365230533
Short name T737
Test name
Test status
Simulation time 42655588636 ps
CPU time 28.65 seconds
Started Jul 24 07:15:59 PM PDT 24
Finished Jul 24 07:16:28 PM PDT 24
Peak memory 201068 kb
Host smart-9103580f-1954-43ae-8a01-96235c47735a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365230533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2365230533
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3145271395
Short name T739
Test name
Test status
Simulation time 4194400346 ps
CPU time 9.97 seconds
Started Jul 24 07:15:58 PM PDT 24
Finished Jul 24 07:16:08 PM PDT 24
Peak memory 201064 kb
Host smart-b13f8c87-0230-43f8-91b8-b45b213b42ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145271395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3145271395
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3550691465
Short name T386
Test name
Test status
Simulation time 6107424008 ps
CPU time 4.15 seconds
Started Jul 24 07:15:59 PM PDT 24
Finished Jul 24 07:16:04 PM PDT 24
Peak memory 201072 kb
Host smart-b3319ed8-3e64-427e-9f0a-88196d3b1b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550691465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3550691465
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.538491707
Short name T98
Test name
Test status
Simulation time 39190976459 ps
CPU time 90.54 seconds
Started Jul 24 07:15:59 PM PDT 24
Finished Jul 24 07:17:29 PM PDT 24
Peak memory 209628 kb
Host smart-cd146b11-69ae-4e1b-9da5-a92a620636ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538491707 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.538491707
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3730942185
Short name T490
Test name
Test status
Simulation time 291319779 ps
CPU time 1.18 seconds
Started Jul 24 07:16:15 PM PDT 24
Finished Jul 24 07:16:17 PM PDT 24
Peak memory 201048 kb
Host smart-27062908-3be9-45bd-9e43-eb2a0b411a0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730942185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3730942185
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3356492018
Short name T231
Test name
Test status
Simulation time 330395263373 ps
CPU time 803.76 seconds
Started Jul 24 07:16:07 PM PDT 24
Finished Jul 24 07:29:31 PM PDT 24
Peak memory 201256 kb
Host smart-e1827ab7-311d-427b-beb9-1c82834e216d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356492018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3356492018
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2237309033
Short name T443
Test name
Test status
Simulation time 164186595202 ps
CPU time 184.59 seconds
Started Jul 24 07:16:06 PM PDT 24
Finished Jul 24 07:19:11 PM PDT 24
Peak memory 201280 kb
Host smart-1095de05-237a-4bd3-ac32-c1fb9e5887b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237309033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2237309033
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2548844382
Short name T267
Test name
Test status
Simulation time 484984251034 ps
CPU time 1060.09 seconds
Started Jul 24 07:16:02 PM PDT 24
Finished Jul 24 07:33:43 PM PDT 24
Peak memory 201200 kb
Host smart-ee9cf2b0-b204-424a-8f0a-34389065427a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548844382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2548844382
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.758210574
Short name T587
Test name
Test status
Simulation time 167951781033 ps
CPU time 98.51 seconds
Started Jul 24 07:16:33 PM PDT 24
Finished Jul 24 07:18:11 PM PDT 24
Peak memory 201236 kb
Host smart-7e7d6272-b233-48e0-8d91-b7654ebca361
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=758210574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.758210574
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2715876201
Short name T755
Test name
Test status
Simulation time 618293296386 ps
CPU time 706.29 seconds
Started Jul 24 07:16:07 PM PDT 24
Finished Jul 24 07:27:54 PM PDT 24
Peak memory 201284 kb
Host smart-4e625aeb-2a2f-4180-8b66-5effdf275586
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715876201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2715876201
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3412471646
Short name T704
Test name
Test status
Simulation time 207906787883 ps
CPU time 95.87 seconds
Started Jul 24 07:16:07 PM PDT 24
Finished Jul 24 07:17:43 PM PDT 24
Peak memory 201160 kb
Host smart-98bde9be-8d34-42ea-b94c-7e48b93a5266
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412471646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3412471646
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2148765735
Short name T195
Test name
Test status
Simulation time 113854587888 ps
CPU time 524.03 seconds
Started Jul 24 07:16:16 PM PDT 24
Finished Jul 24 07:25:00 PM PDT 24
Peak memory 201668 kb
Host smart-723dc0d7-ec55-4f1b-b99e-6ab020230149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148765735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2148765735
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.963905030
Short name T465
Test name
Test status
Simulation time 34597113481 ps
CPU time 8.23 seconds
Started Jul 24 07:16:07 PM PDT 24
Finished Jul 24 07:16:15 PM PDT 24
Peak memory 201076 kb
Host smart-19e43a75-e4c2-4993-846a-d85057e69daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963905030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.963905030
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3350746415
Short name T367
Test name
Test status
Simulation time 5123608833 ps
CPU time 3.89 seconds
Started Jul 24 07:16:07 PM PDT 24
Finished Jul 24 07:16:11 PM PDT 24
Peak memory 201108 kb
Host smart-d478a0bb-65de-48bc-937f-b75828925c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350746415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3350746415
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2562843294
Short name T89
Test name
Test status
Simulation time 5663179398 ps
CPU time 15.39 seconds
Started Jul 24 07:15:59 PM PDT 24
Finished Jul 24 07:16:15 PM PDT 24
Peak memory 201112 kb
Host smart-73e45f00-d727-43f0-a48a-146ec0952ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562843294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2562843294
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1870118681
Short name T39
Test name
Test status
Simulation time 251270191077 ps
CPU time 562.96 seconds
Started Jul 24 07:16:14 PM PDT 24
Finished Jul 24 07:25:37 PM PDT 24
Peak memory 210268 kb
Host smart-a99d1e4e-6be4-4aa4-b5d4-9fbf70223e1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870118681 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1870118681
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2371944582
Short name T377
Test name
Test status
Simulation time 367423467 ps
CPU time 1.05 seconds
Started Jul 24 07:16:26 PM PDT 24
Finished Jul 24 07:16:27 PM PDT 24
Peak memory 200900 kb
Host smart-d5d75882-de05-4c20-b304-6bef19239661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371944582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2371944582
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2749052279
Short name T291
Test name
Test status
Simulation time 167618416481 ps
CPU time 97.05 seconds
Started Jul 24 07:16:26 PM PDT 24
Finished Jul 24 07:18:04 PM PDT 24
Peak memory 201220 kb
Host smart-0d5c6227-e4d4-43af-b724-8cd9b0bbcc9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749052279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2749052279
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2817760743
Short name T208
Test name
Test status
Simulation time 167253941019 ps
CPU time 198.38 seconds
Started Jul 24 07:16:29 PM PDT 24
Finished Jul 24 07:19:47 PM PDT 24
Peak memory 201252 kb
Host smart-c03a29d8-8f5b-4d23-b656-623cd30098f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817760743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2817760743
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.219148764
Short name T316
Test name
Test status
Simulation time 164898394352 ps
CPU time 193.62 seconds
Started Jul 24 07:16:21 PM PDT 24
Finished Jul 24 07:19:35 PM PDT 24
Peak memory 201228 kb
Host smart-b29c0379-650a-47e2-a75a-c59026e42de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219148764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.219148764
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.439530377
Short name T620
Test name
Test status
Simulation time 330090351139 ps
CPU time 187.97 seconds
Started Jul 24 07:16:20 PM PDT 24
Finished Jul 24 07:19:28 PM PDT 24
Peak memory 201296 kb
Host smart-41547460-9755-4780-8378-8c5b3b9d7763
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=439530377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.439530377
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2184478938
Short name T656
Test name
Test status
Simulation time 484471611058 ps
CPU time 1121.52 seconds
Started Jul 24 07:16:20 PM PDT 24
Finished Jul 24 07:35:02 PM PDT 24
Peak memory 201244 kb
Host smart-256d66a3-fb5a-4895-a4e9-0b8bda431666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184478938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2184478938
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.114971312
Short name T144
Test name
Test status
Simulation time 325309976460 ps
CPU time 101.22 seconds
Started Jul 24 07:16:20 PM PDT 24
Finished Jul 24 07:18:02 PM PDT 24
Peak memory 201120 kb
Host smart-dd0e42f4-3534-4d15-bf92-1065893473e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=114971312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.114971312
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3161846756
Short name T301
Test name
Test status
Simulation time 207086195637 ps
CPU time 261.9 seconds
Started Jul 24 07:16:21 PM PDT 24
Finished Jul 24 07:20:43 PM PDT 24
Peak memory 201244 kb
Host smart-0ae5da2f-12ae-4f78-93a5-9c48eb5e92d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161846756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3161846756
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3851312965
Short name T718
Test name
Test status
Simulation time 199156663399 ps
CPU time 241.2 seconds
Started Jul 24 07:16:27 PM PDT 24
Finished Jul 24 07:20:28 PM PDT 24
Peak memory 201224 kb
Host smart-8a35131a-0c16-49b1-9d0a-9c5a5da10a0f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851312965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3851312965
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3844601102
Short name T464
Test name
Test status
Simulation time 112596177289 ps
CPU time 561.72 seconds
Started Jul 24 07:16:28 PM PDT 24
Finished Jul 24 07:25:50 PM PDT 24
Peak memory 201692 kb
Host smart-69323ca7-810f-467b-bee4-dfb1d5fecffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844601102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3844601102
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1449901566
Short name T607
Test name
Test status
Simulation time 29292624941 ps
CPU time 62.56 seconds
Started Jul 24 07:16:26 PM PDT 24
Finished Jul 24 07:17:28 PM PDT 24
Peak memory 201100 kb
Host smart-dc584683-0074-4b6a-8ca8-a66683bc0106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449901566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1449901566
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1014250175
Short name T360
Test name
Test status
Simulation time 5332071426 ps
CPU time 13.82 seconds
Started Jul 24 07:16:28 PM PDT 24
Finished Jul 24 07:16:42 PM PDT 24
Peak memory 201080 kb
Host smart-a9d29a9c-be2a-4178-92b4-ab0f802c2ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014250175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1014250175
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2383530177
Short name T750
Test name
Test status
Simulation time 6010641349 ps
CPU time 12.77 seconds
Started Jul 24 07:16:16 PM PDT 24
Finished Jul 24 07:16:28 PM PDT 24
Peak memory 201180 kb
Host smart-0e533fbc-ebf6-4139-a3a9-b68857e08ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383530177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2383530177
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.170805992
Short name T19
Test name
Test status
Simulation time 262266117373 ps
CPU time 233.14 seconds
Started Jul 24 07:16:28 PM PDT 24
Finished Jul 24 07:20:22 PM PDT 24
Peak memory 218184 kb
Host smart-4e38e9c3-fd15-4bfe-9393-8fada6bc019b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170805992 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.170805992
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2504685484
Short name T162
Test name
Test status
Simulation time 375071693 ps
CPU time 1.39 seconds
Started Jul 24 07:16:44 PM PDT 24
Finished Jul 24 07:16:46 PM PDT 24
Peak memory 200992 kb
Host smart-e22d56e5-565c-4b51-9944-d80cd180f834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504685484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2504685484
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1785615340
Short name T74
Test name
Test status
Simulation time 491911328049 ps
CPU time 229.21 seconds
Started Jul 24 07:16:39 PM PDT 24
Finished Jul 24 07:20:28 PM PDT 24
Peak memory 201304 kb
Host smart-18ab3ade-0794-48ee-97c7-c23c018b85a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785615340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1785615340
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.913013367
Short name T148
Test name
Test status
Simulation time 356004533173 ps
CPU time 60.22 seconds
Started Jul 24 07:16:38 PM PDT 24
Finished Jul 24 07:17:38 PM PDT 24
Peak memory 201236 kb
Host smart-7ba06362-f60b-4f92-8938-5d0c212f8b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913013367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.913013367
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1084697134
Short name T776
Test name
Test status
Simulation time 484324641643 ps
CPU time 1044.4 seconds
Started Jul 24 07:16:34 PM PDT 24
Finished Jul 24 07:33:58 PM PDT 24
Peak memory 201324 kb
Host smart-475528d8-0c69-4034-9f96-e1f3a7112b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084697134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1084697134
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.316480864
Short name T768
Test name
Test status
Simulation time 490665681646 ps
CPU time 181.87 seconds
Started Jul 24 07:16:33 PM PDT 24
Finished Jul 24 07:19:36 PM PDT 24
Peak memory 201264 kb
Host smart-8d197c90-91ee-4e07-b4e9-aa26a7d03af7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=316480864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.316480864
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3223891421
Short name T681
Test name
Test status
Simulation time 160100697582 ps
CPU time 173.58 seconds
Started Jul 24 07:16:33 PM PDT 24
Finished Jul 24 07:19:27 PM PDT 24
Peak memory 201272 kb
Host smart-85c86220-a6c3-4e4c-aba4-ee89e4aa930b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223891421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3223891421
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1433875650
Short name T358
Test name
Test status
Simulation time 321504952747 ps
CPU time 65.63 seconds
Started Jul 24 07:16:38 PM PDT 24
Finished Jul 24 07:17:43 PM PDT 24
Peak memory 201252 kb
Host smart-8d70e826-3cfd-4f28-ad73-1f01c8c5d543
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433875650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1433875650
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3171027199
Short name T640
Test name
Test status
Simulation time 171956090370 ps
CPU time 408.51 seconds
Started Jul 24 07:16:35 PM PDT 24
Finished Jul 24 07:23:23 PM PDT 24
Peak memory 201292 kb
Host smart-9b8126ec-1e3a-4c10-b72e-101989238c0b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171027199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3171027199
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1149299866
Short name T40
Test name
Test status
Simulation time 391189429989 ps
CPU time 438.12 seconds
Started Jul 24 07:16:35 PM PDT 24
Finished Jul 24 07:23:53 PM PDT 24
Peak memory 201236 kb
Host smart-1c823366-e671-4e53-a53b-8ad864a437a2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149299866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1149299866
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1902890078
Short name T507
Test name
Test status
Simulation time 87193840597 ps
CPU time 291.88 seconds
Started Jul 24 07:16:39 PM PDT 24
Finished Jul 24 07:21:32 PM PDT 24
Peak memory 201692 kb
Host smart-7f53cc96-b10b-4cbb-a83e-97e5fc0925bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902890078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1902890078
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2470488673
Short name T753
Test name
Test status
Simulation time 44140747566 ps
CPU time 106.07 seconds
Started Jul 24 07:16:39 PM PDT 24
Finished Jul 24 07:18:25 PM PDT 24
Peak memory 201092 kb
Host smart-5dde45b7-8a60-47c6-a699-a82de336dd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470488673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2470488673
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1461245573
Short name T379
Test name
Test status
Simulation time 5081414552 ps
CPU time 6.55 seconds
Started Jul 24 07:16:38 PM PDT 24
Finished Jul 24 07:16:45 PM PDT 24
Peak memory 201080 kb
Host smart-2072d4a0-f478-4d2f-b35b-b73565449e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461245573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1461245573
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.542439823
Short name T644
Test name
Test status
Simulation time 5775093900 ps
CPU time 1.86 seconds
Started Jul 24 07:16:32 PM PDT 24
Finished Jul 24 07:16:34 PM PDT 24
Peak memory 201056 kb
Host smart-4d4b9f70-2100-434a-adff-f3ee269e38fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542439823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.542439823
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.464482414
Short name T790
Test name
Test status
Simulation time 571337422612 ps
CPU time 1510.35 seconds
Started Jul 24 07:16:45 PM PDT 24
Finished Jul 24 07:41:55 PM PDT 24
Peak memory 201640 kb
Host smart-0e562abd-a1e8-44bc-8c54-182e679d6e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464482414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
464482414
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1510412735
Short name T698
Test name
Test status
Simulation time 508518551 ps
CPU time 1.19 seconds
Started Jul 24 07:10:08 PM PDT 24
Finished Jul 24 07:10:10 PM PDT 24
Peak memory 201044 kb
Host smart-80e7461b-bfaa-474a-be3d-24ec034f7420
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510412735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1510412735
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2486799784
Short name T261
Test name
Test status
Simulation time 351502530175 ps
CPU time 424.54 seconds
Started Jul 24 07:10:16 PM PDT 24
Finished Jul 24 07:17:21 PM PDT 24
Peak memory 201240 kb
Host smart-2efe5373-5344-423f-9899-f14d258d2c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486799784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2486799784
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3787126429
Short name T250
Test name
Test status
Simulation time 327052740538 ps
CPU time 198.13 seconds
Started Jul 24 07:10:11 PM PDT 24
Finished Jul 24 07:13:29 PM PDT 24
Peak memory 201212 kb
Host smart-8be651b2-e3a0-4a83-a3a0-de5d592a224d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787126429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3787126429
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2125843385
Short name T530
Test name
Test status
Simulation time 167587872130 ps
CPU time 310.64 seconds
Started Jul 24 07:10:11 PM PDT 24
Finished Jul 24 07:15:22 PM PDT 24
Peak memory 201196 kb
Host smart-e3e82c75-8174-409b-b3d0-79d78543f103
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125843385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2125843385
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2807184247
Short name T202
Test name
Test status
Simulation time 326211060107 ps
CPU time 408.92 seconds
Started Jul 24 07:10:16 PM PDT 24
Finished Jul 24 07:17:05 PM PDT 24
Peak memory 201276 kb
Host smart-c80552d4-071c-4a5b-b9d6-a35f09d48bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807184247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2807184247
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1256883284
Short name T760
Test name
Test status
Simulation time 335901222072 ps
CPU time 738.8 seconds
Started Jul 24 07:10:18 PM PDT 24
Finished Jul 24 07:22:37 PM PDT 24
Peak memory 201208 kb
Host smart-c18be079-9d4a-4e7e-822d-a1dce5a0d8ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256883284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1256883284
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2488824236
Short name T75
Test name
Test status
Simulation time 343344127077 ps
CPU time 219.71 seconds
Started Jul 24 07:10:16 PM PDT 24
Finished Jul 24 07:13:56 PM PDT 24
Peak memory 201236 kb
Host smart-c0556e8b-dbd0-4a5c-877c-919537fe2b87
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488824236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2488824236
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.4148442876
Short name T532
Test name
Test status
Simulation time 191081461928 ps
CPU time 114.45 seconds
Started Jul 24 07:10:10 PM PDT 24
Finished Jul 24 07:12:05 PM PDT 24
Peak memory 201244 kb
Host smart-9e8e84e7-30d9-460b-8057-b50c4cc99b8f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148442876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.4148442876
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2392586017
Short name T686
Test name
Test status
Simulation time 84675209786 ps
CPU time 433.87 seconds
Started Jul 24 07:10:10 PM PDT 24
Finished Jul 24 07:17:24 PM PDT 24
Peak memory 201684 kb
Host smart-9c9e26b0-5324-4dff-b47b-62e2d7a716cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392586017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2392586017
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1171334760
Short name T401
Test name
Test status
Simulation time 36832413426 ps
CPU time 81.89 seconds
Started Jul 24 07:10:19 PM PDT 24
Finished Jul 24 07:11:41 PM PDT 24
Peak memory 201120 kb
Host smart-a65c5f9f-a8cf-4915-81e6-67d9fa7bc8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171334760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1171334760
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.253606728
Short name T635
Test name
Test status
Simulation time 3230552261 ps
CPU time 3.74 seconds
Started Jul 24 07:10:18 PM PDT 24
Finished Jul 24 07:10:22 PM PDT 24
Peak memory 200988 kb
Host smart-922cb71e-385f-4b48-ba3c-a3706a61e256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253606728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.253606728
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1324030786
Short name T551
Test name
Test status
Simulation time 5784554692 ps
CPU time 14.78 seconds
Started Jul 24 07:10:14 PM PDT 24
Finished Jul 24 07:10:29 PM PDT 24
Peak memory 201112 kb
Host smart-fba9454a-fdf1-46b7-ac23-6971c48ca2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324030786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1324030786
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2950698835
Short name T657
Test name
Test status
Simulation time 327987887054 ps
CPU time 338.15 seconds
Started Jul 24 07:10:17 PM PDT 24
Finished Jul 24 07:15:55 PM PDT 24
Peak memory 201248 kb
Host smart-a10f9dab-9257-4347-a2a3-10ed3bc3b1ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950698835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2950698835
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2655725239
Short name T83
Test name
Test status
Simulation time 19389862203 ps
CPU time 47.65 seconds
Started Jul 24 07:10:10 PM PDT 24
Finished Jul 24 07:10:58 PM PDT 24
Peak memory 201412 kb
Host smart-e79ee350-c82a-4c4f-a20d-5a131aa6cee8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655725239 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2655725239
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3213272180
Short name T535
Test name
Test status
Simulation time 416453297 ps
CPU time 1.56 seconds
Started Jul 24 07:10:12 PM PDT 24
Finished Jul 24 07:10:14 PM PDT 24
Peak memory 201056 kb
Host smart-7323eaa9-3587-4858-8f93-69a8e9a5d66d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213272180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3213272180
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2476880293
Short name T230
Test name
Test status
Simulation time 329250343957 ps
CPU time 119.92 seconds
Started Jul 24 07:10:13 PM PDT 24
Finished Jul 24 07:12:13 PM PDT 24
Peak memory 201240 kb
Host smart-236f3408-16f6-4c9a-ae49-56c49f1292ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476880293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2476880293
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.736366612
Short name T186
Test name
Test status
Simulation time 164367646583 ps
CPU time 203.95 seconds
Started Jul 24 07:10:15 PM PDT 24
Finished Jul 24 07:13:39 PM PDT 24
Peak memory 201208 kb
Host smart-fb47f564-fdab-4a62-b6e7-b79c57879543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736366612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.736366612
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.800142688
Short name T310
Test name
Test status
Simulation time 161155304279 ps
CPU time 360.69 seconds
Started Jul 24 07:10:13 PM PDT 24
Finished Jul 24 07:16:14 PM PDT 24
Peak memory 201196 kb
Host smart-372fca8a-64ff-4fd8-9df1-36c1d73ffd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800142688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.800142688
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3471453460
Short name T484
Test name
Test status
Simulation time 498445206945 ps
CPU time 1125.34 seconds
Started Jul 24 07:10:15 PM PDT 24
Finished Jul 24 07:29:01 PM PDT 24
Peak memory 201196 kb
Host smart-d40453d6-7d04-4526-a686-c7a58b1a589b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471453460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3471453460
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1334777759
Short name T141
Test name
Test status
Simulation time 491710589656 ps
CPU time 1168.45 seconds
Started Jul 24 07:10:15 PM PDT 24
Finished Jul 24 07:29:44 PM PDT 24
Peak memory 201252 kb
Host smart-942b2b55-09f1-4fdb-ac24-56c9f8df3bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334777759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1334777759
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3050200518
Short name T652
Test name
Test status
Simulation time 162187871520 ps
CPU time 350.4 seconds
Started Jul 24 07:10:17 PM PDT 24
Finished Jul 24 07:16:07 PM PDT 24
Peak memory 201248 kb
Host smart-eb9f38d0-8422-453f-8a42-183161998ccf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050200518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3050200518
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.710644026
Short name T769
Test name
Test status
Simulation time 177581433108 ps
CPU time 428 seconds
Started Jul 24 07:10:12 PM PDT 24
Finished Jul 24 07:17:20 PM PDT 24
Peak memory 201244 kb
Host smart-257182aa-4762-4aa5-8c14-112764e31b66
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710644026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_w
akeup.710644026
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.65596738
Short name T713
Test name
Test status
Simulation time 410449939987 ps
CPU time 884.42 seconds
Started Jul 24 07:10:17 PM PDT 24
Finished Jul 24 07:25:01 PM PDT 24
Peak memory 201144 kb
Host smart-a9b07002-47cd-4d5b-9d46-d8a4ad5e092c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65596738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.ad
c_ctrl_filters_wakeup_fixed.65596738
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1692804747
Short name T729
Test name
Test status
Simulation time 132740893667 ps
CPU time 649.35 seconds
Started Jul 24 07:10:12 PM PDT 24
Finished Jul 24 07:21:02 PM PDT 24
Peak memory 201760 kb
Host smart-8e7857b0-b884-44e8-ab3d-9ed232151bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692804747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1692804747
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3868584331
Short name T486
Test name
Test status
Simulation time 22142525201 ps
CPU time 48.22 seconds
Started Jul 24 07:10:13 PM PDT 24
Finished Jul 24 07:11:01 PM PDT 24
Peak memory 201036 kb
Host smart-e34561dd-3a04-40f9-8249-9d5009c9a52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868584331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3868584331
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.673883629
Short name T669
Test name
Test status
Simulation time 5019520909 ps
CPU time 6.38 seconds
Started Jul 24 07:10:14 PM PDT 24
Finished Jul 24 07:10:20 PM PDT 24
Peak memory 201172 kb
Host smart-922a5229-bb99-4a9e-a1f9-6e5d0811d392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673883629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.673883629
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.94830636
Short name T427
Test name
Test status
Simulation time 5688332862 ps
CPU time 8.89 seconds
Started Jul 24 07:10:13 PM PDT 24
Finished Jul 24 07:10:22 PM PDT 24
Peak memory 201068 kb
Host smart-7f9616ef-d1cc-4976-b405-552cc0aaf1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94830636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.94830636
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3833101996
Short name T726
Test name
Test status
Simulation time 292732388197 ps
CPU time 677.42 seconds
Started Jul 24 07:10:13 PM PDT 24
Finished Jul 24 07:21:31 PM PDT 24
Peak memory 201244 kb
Host smart-a245bba9-293e-4f4c-8b4d-2648ac87bc56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833101996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3833101996
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2019760035
Short name T285
Test name
Test status
Simulation time 154924296415 ps
CPU time 206.68 seconds
Started Jul 24 07:10:18 PM PDT 24
Finished Jul 24 07:13:45 PM PDT 24
Peak memory 210096 kb
Host smart-c6e99a70-d325-41b9-95d3-b55862687863
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019760035 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2019760035
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.82094480
Short name T538
Test name
Test status
Simulation time 336971019 ps
CPU time 0.83 seconds
Started Jul 24 07:10:16 PM PDT 24
Finished Jul 24 07:10:17 PM PDT 24
Peak memory 201052 kb
Host smart-37210031-56be-473a-8141-6937adbc1ba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82094480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.82094480
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1382431131
Short name T221
Test name
Test status
Simulation time 342587445722 ps
CPU time 194.86 seconds
Started Jul 24 07:10:17 PM PDT 24
Finished Jul 24 07:13:32 PM PDT 24
Peak memory 201264 kb
Host smart-454e35b1-cdff-4dcd-9240-9d10839aa124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382431131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1382431131
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3143145954
Short name T253
Test name
Test status
Simulation time 335915763064 ps
CPU time 789.63 seconds
Started Jul 24 07:10:11 PM PDT 24
Finished Jul 24 07:23:21 PM PDT 24
Peak memory 201328 kb
Host smart-3c7a7380-063a-473e-80ad-7d9bd7e3d334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143145954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3143145954
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3354014740
Short name T487
Test name
Test status
Simulation time 321691165373 ps
CPU time 198.03 seconds
Started Jul 24 07:10:13 PM PDT 24
Finished Jul 24 07:13:31 PM PDT 24
Peak memory 201172 kb
Host smart-54683fb1-e9e3-422b-adcc-c83e24f3c014
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354014740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3354014740
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.377090789
Short name T775
Test name
Test status
Simulation time 166020362846 ps
CPU time 93.72 seconds
Started Jul 24 07:10:13 PM PDT 24
Finished Jul 24 07:11:47 PM PDT 24
Peak memory 201276 kb
Host smart-7c84de77-6751-49b2-ab32-ceb83bc19898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377090789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.377090789
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2131951138
Short name T761
Test name
Test status
Simulation time 161336948254 ps
CPU time 399.8 seconds
Started Jul 24 07:10:12 PM PDT 24
Finished Jul 24 07:16:52 PM PDT 24
Peak memory 201292 kb
Host smart-c4d98820-e152-442a-968b-91e11cebe4a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131951138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2131951138
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.4123171486
Short name T332
Test name
Test status
Simulation time 553529455780 ps
CPU time 544.5 seconds
Started Jul 24 07:10:19 PM PDT 24
Finished Jul 24 07:19:24 PM PDT 24
Peak memory 201224 kb
Host smart-c6b5133e-9e41-4728-aae3-185830f16514
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123171486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.4123171486
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1892918917
Short name T444
Test name
Test status
Simulation time 205337860565 ps
CPU time 495.45 seconds
Started Jul 24 07:10:17 PM PDT 24
Finished Jul 24 07:18:33 PM PDT 24
Peak memory 201148 kb
Host smart-e3abdc73-3bea-4315-b2f2-9359951a924f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892918917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1892918917
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2544443736
Short name T576
Test name
Test status
Simulation time 103853779608 ps
CPU time 378.5 seconds
Started Jul 24 07:10:19 PM PDT 24
Finished Jul 24 07:16:38 PM PDT 24
Peak memory 201636 kb
Host smart-25f4338b-5ad4-4f52-ba73-e61155755196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544443736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2544443736
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2790423409
Short name T372
Test name
Test status
Simulation time 40687832890 ps
CPU time 22.36 seconds
Started Jul 24 07:10:11 PM PDT 24
Finished Jul 24 07:10:34 PM PDT 24
Peak memory 201084 kb
Host smart-228ba33a-0841-41ee-b6eb-de82e5cce81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790423409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2790423409
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1201201485
Short name T596
Test name
Test status
Simulation time 3762253069 ps
CPU time 9.18 seconds
Started Jul 24 07:10:12 PM PDT 24
Finished Jul 24 07:10:22 PM PDT 24
Peak memory 201040 kb
Host smart-f3084fe5-9632-4900-a0c5-03d8cb638496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201201485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1201201485
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3538526388
Short name T408
Test name
Test status
Simulation time 5716041124 ps
CPU time 13.1 seconds
Started Jul 24 07:10:13 PM PDT 24
Finished Jul 24 07:10:27 PM PDT 24
Peak memory 201104 kb
Host smart-538e2e0a-fe2c-44e8-9749-d99be2d7352e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538526388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3538526388
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.398714214
Short name T709
Test name
Test status
Simulation time 379547433143 ps
CPU time 891.11 seconds
Started Jul 24 07:10:18 PM PDT 24
Finished Jul 24 07:25:10 PM PDT 24
Peak memory 201276 kb
Host smart-b34974b6-5f60-4bc6-b435-6fa3ad9e97ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398714214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.398714214
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1099094019
Short name T298
Test name
Test status
Simulation time 27759944902 ps
CPU time 90.66 seconds
Started Jul 24 07:10:18 PM PDT 24
Finished Jul 24 07:11:48 PM PDT 24
Peak memory 210040 kb
Host smart-2a711fd1-0870-413b-9ae3-fcdeb3994136
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099094019 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1099094019
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1819511581
Short name T770
Test name
Test status
Simulation time 394050141 ps
CPU time 0.74 seconds
Started Jul 24 07:10:21 PM PDT 24
Finished Jul 24 07:10:21 PM PDT 24
Peak memory 201032 kb
Host smart-669f84e6-b29c-4750-9016-aa0643472ed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819511581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1819511581
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.190397863
Short name T280
Test name
Test status
Simulation time 167499972047 ps
CPU time 402.21 seconds
Started Jul 24 07:10:22 PM PDT 24
Finished Jul 24 07:17:05 PM PDT 24
Peak memory 201248 kb
Host smart-b142bffb-a9d1-4c69-8d97-3dd20ab92445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190397863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.190397863
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2912966230
Short name T430
Test name
Test status
Simulation time 327334764842 ps
CPU time 364.65 seconds
Started Jul 24 07:10:23 PM PDT 24
Finished Jul 24 07:16:28 PM PDT 24
Peak memory 201224 kb
Host smart-7f7d7342-de35-41fa-810c-1482466eeeb4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912966230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2912966230
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2506224048
Short name T784
Test name
Test status
Simulation time 325631526798 ps
CPU time 169.92 seconds
Started Jul 24 07:10:14 PM PDT 24
Finished Jul 24 07:13:04 PM PDT 24
Peak memory 201260 kb
Host smart-8ea9d3df-abb9-4eac-9fd7-a4a51bd9da7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506224048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2506224048
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1691154608
Short name T746
Test name
Test status
Simulation time 165200308346 ps
CPU time 370.34 seconds
Started Jul 24 07:10:16 PM PDT 24
Finished Jul 24 07:16:26 PM PDT 24
Peak memory 201124 kb
Host smart-c6b2dc52-ee5a-4382-9e62-5647a07b4bfe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691154608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1691154608
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1551313715
Short name T789
Test name
Test status
Simulation time 204534133286 ps
CPU time 452.25 seconds
Started Jul 24 07:10:23 PM PDT 24
Finished Jul 24 07:17:55 PM PDT 24
Peak memory 201232 kb
Host smart-cafbb687-404f-4fbf-8ab2-225b2aec8ac1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551313715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1551313715
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2455705358
Short name T632
Test name
Test status
Simulation time 399921825126 ps
CPU time 896.87 seconds
Started Jul 24 07:10:34 PM PDT 24
Finished Jul 24 07:25:31 PM PDT 24
Peak memory 201224 kb
Host smart-ed2be70e-5e65-4a02-8986-58f9275c43fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455705358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2455705358
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1943599031
Short name T369
Test name
Test status
Simulation time 38200853600 ps
CPU time 84.01 seconds
Started Jul 24 07:10:22 PM PDT 24
Finished Jul 24 07:11:47 PM PDT 24
Peak memory 201204 kb
Host smart-24303ecc-cf12-4fa7-a510-0c9688e58006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943599031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1943599031
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2655265640
Short name T442
Test name
Test status
Simulation time 3659216323 ps
CPU time 8.7 seconds
Started Jul 24 07:10:22 PM PDT 24
Finished Jul 24 07:10:31 PM PDT 24
Peak memory 201116 kb
Host smart-dc4fb0aa-f85b-447a-b948-4a6771920a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655265640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2655265640
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1887488295
Short name T676
Test name
Test status
Simulation time 5641210242 ps
CPU time 3.5 seconds
Started Jul 24 07:10:13 PM PDT 24
Finished Jul 24 07:10:17 PM PDT 24
Peak memory 201084 kb
Host smart-e6632388-c91e-4799-bf23-1275d8e5c822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887488295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1887488295
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1167871967
Short name T624
Test name
Test status
Simulation time 338825202249 ps
CPU time 518.73 seconds
Started Jul 24 07:10:39 PM PDT 24
Finished Jul 24 07:19:18 PM PDT 24
Peak memory 211788 kb
Host smart-d40375a6-e35b-4064-beb7-75610d8a11dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167871967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1167871967
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3096479336
Short name T16
Test name
Test status
Simulation time 73926132143 ps
CPU time 45.9 seconds
Started Jul 24 07:10:39 PM PDT 24
Finished Jul 24 07:11:25 PM PDT 24
Peak memory 210076 kb
Host smart-e6575e06-62c3-48bc-93ab-93f3ccdaae5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096479336 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3096479336
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2867508499
Short name T679
Test name
Test status
Simulation time 506838129 ps
CPU time 1.22 seconds
Started Jul 24 07:10:20 PM PDT 24
Finished Jul 24 07:10:22 PM PDT 24
Peak memory 201048 kb
Host smart-a10d8b99-3fc0-4243-9739-8ea4de534ceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867508499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2867508499
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2163406208
Short name T237
Test name
Test status
Simulation time 347275088412 ps
CPU time 219.99 seconds
Started Jul 24 07:10:23 PM PDT 24
Finished Jul 24 07:14:03 PM PDT 24
Peak memory 201252 kb
Host smart-c8478609-9c30-4027-9f57-6e2d92d47a0c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163406208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2163406208
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.911640498
Short name T580
Test name
Test status
Simulation time 197333944748 ps
CPU time 466.07 seconds
Started Jul 24 07:10:40 PM PDT 24
Finished Jul 24 07:18:26 PM PDT 24
Peak memory 201296 kb
Host smart-e6f77d60-d3ab-424e-adb6-9f6d3974f520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911640498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.911640498
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2511311711
Short name T335
Test name
Test status
Simulation time 497226317015 ps
CPU time 438.82 seconds
Started Jul 24 07:10:19 PM PDT 24
Finished Jul 24 07:17:38 PM PDT 24
Peak memory 201228 kb
Host smart-6501ccac-2e03-4ff7-b0a9-3df620fea178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511311711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2511311711
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3053881280
Short name T182
Test name
Test status
Simulation time 327472558272 ps
CPU time 165.78 seconds
Started Jul 24 07:10:23 PM PDT 24
Finished Jul 24 07:13:09 PM PDT 24
Peak memory 201236 kb
Host smart-eccf1c64-71e1-4e2f-9b07-ce7eb43c9142
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053881280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3053881280
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.907446321
Short name T157
Test name
Test status
Simulation time 488897855153 ps
CPU time 272.81 seconds
Started Jul 24 07:10:21 PM PDT 24
Finished Jul 24 07:14:54 PM PDT 24
Peak memory 201288 kb
Host smart-a5a8615a-8cd2-4585-8f49-3b801fd106b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907446321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.907446321
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2736864016
Short name T695
Test name
Test status
Simulation time 162720958860 ps
CPU time 355.82 seconds
Started Jul 24 07:10:24 PM PDT 24
Finished Jul 24 07:16:20 PM PDT 24
Peak memory 201104 kb
Host smart-bdab8dce-a1b2-434d-bd19-dd1d8f04d729
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736864016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2736864016
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1505282525
Short name T337
Test name
Test status
Simulation time 387621848705 ps
CPU time 857.69 seconds
Started Jul 24 07:10:40 PM PDT 24
Finished Jul 24 07:24:58 PM PDT 24
Peak memory 201272 kb
Host smart-b0385174-2c21-4375-96ad-1326ae777564
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505282525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1505282525
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3498599106
Short name T563
Test name
Test status
Simulation time 389845023189 ps
CPU time 143.57 seconds
Started Jul 24 07:10:23 PM PDT 24
Finished Jul 24 07:12:47 PM PDT 24
Peak memory 201260 kb
Host smart-f4414189-cd5d-4daf-8a4f-49ca873566d1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498599106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3498599106
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1676344978
Short name T749
Test name
Test status
Simulation time 35638534999 ps
CPU time 86.64 seconds
Started Jul 24 07:10:20 PM PDT 24
Finished Jul 24 07:11:47 PM PDT 24
Peak memory 201100 kb
Host smart-c2ba47b4-5724-403a-bebc-9b7ce9c9e364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676344978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1676344978
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3777918603
Short name T109
Test name
Test status
Simulation time 5093074514 ps
CPU time 2.39 seconds
Started Jul 24 07:10:26 PM PDT 24
Finished Jul 24 07:10:29 PM PDT 24
Peak memory 201088 kb
Host smart-81536351-e4a0-42a4-b25c-98b7cc37e728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777918603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3777918603
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2611687287
Short name T4
Test name
Test status
Simulation time 5932626741 ps
CPU time 14.74 seconds
Started Jul 24 07:10:19 PM PDT 24
Finished Jul 24 07:10:34 PM PDT 24
Peak memory 201260 kb
Host smart-9a598a03-2528-4ed4-bb37-5b7c7a95e873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611687287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2611687287
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.4087402315
Short name T615
Test name
Test status
Simulation time 573863444419 ps
CPU time 289.08 seconds
Started Jul 24 07:10:18 PM PDT 24
Finished Jul 24 07:15:08 PM PDT 24
Peak memory 201312 kb
Host smart-b414afc5-b87e-4ffa-8c49-903e0cd0ca30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087402315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
4087402315
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2308411178
Short name T79
Test name
Test status
Simulation time 220532219956 ps
CPU time 465.77 seconds
Started Jul 24 07:10:37 PM PDT 24
Finished Jul 24 07:18:23 PM PDT 24
Peak memory 210020 kb
Host smart-5e677a5f-d4ab-4a5f-a1fe-9d7bdf2c813d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308411178 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2308411178
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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