Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1225261	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1194516

1

T1

351

T2

2010

T3

1372

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2111766	1			T2	4037		T3	2460		T4	1640
values[0x0]	153675	1			T1	419		T2	91		T3	150
values[0x1]	154336	1			T1	477		T2	102		T3	149

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	981994	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1437783

1

T1

420

T2

2453

T3

1641

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7639	1			T2	15		T3	5		T4	4
valid_sources[0x01]	15653	1			T2	13		T3	24		T4	5
valid_sources[0x02]	8161	1			T2	16		T3	17		T4	2
valid_sources[0x03]	7152	1			T2	11		T3	13		T4	1
valid_sources[0x04]	8435	1			T2	2		T3	14		T4	4
valid_sources[0x05]	8596	1			T2	12		T3	3		T4	1
valid_sources[0x06]	7607	1			T2	14		T3	4		T4	2
valid_sources[0x07]	7162	1			T2	12		T3	12		T4	6
valid_sources[0x08]	12293	1			T2	19		T3	6		T4	2
valid_sources[0x09]	7387	1			T2	8		T3	35		T4	10
valid_sources[0x0a]	11964	1			T2	19		T3	1		T4	2
valid_sources[0x0b]	7383	1			T2	33		T3	2		T4	3
valid_sources[0x0c]	7008	1			T2	12		T3	7		T4	5
valid_sources[0x0d]	6913	1			T2	21		T3	1		T4	4
valid_sources[0x0e]	11605	1			T2	25		T3	3		T5	9
valid_sources[0x0f]	7353	1			T2	15		T3	1		T4	4
valid_sources[0x10]	8918	1			T2	16		T4	2		T5	12
valid_sources[0x11]	11141	1			T2	22		T3	5		T4	2
valid_sources[0x12]	7252	1			T2	19		T3	21		T4	3
valid_sources[0x13]	7451	1			T2	13		T3	13		T4	1
valid_sources[0x14]	7212	1			T2	15		T3	6		T4	8
valid_sources[0x15]	7281	1			T2	18		T3	4		T4	7
valid_sources[0x16]	8103	1			T2	13		T3	1		T4	2
valid_sources[0x17]	7164	1			T2	21		T3	4		T4	4
valid_sources[0x18]	9061	1			T2	5		T3	2		T4	7
valid_sources[0x19]	7481	1			T2	20		T3	20		T4	3
valid_sources[0x1a]	10004	1			T2	30		T3	8		T5	17
valid_sources[0x1b]	8933	1			T2	13		T3	11		T5	9
valid_sources[0x1c]	12677	1			T2	9		T3	2		T4	3
valid_sources[0x1d]	10199	1			T2	9		T3	5		T4	7
valid_sources[0x1e]	8197	1			T2	10		T3	3		T4	2
valid_sources[0x1f]	11736	1			T2	17		T3	1		T4	1
valid_sources[0x20]	8237	1			T2	16		T3	3		T4	6
valid_sources[0x21]	7295	1			T2	20		T3	11		T4	3
valid_sources[0x22]	11183	1			T2	8		T3	3		T4	1
valid_sources[0x23]	7097	1			T2	42		T3	4		T4	5
valid_sources[0x24]	7696	1			T2	37		T3	4		T4	3
valid_sources[0x25]	7580	1			T2	13		T3	7		T4	3
valid_sources[0x26]	7304	1			T2	19		T3	2		T4	3
valid_sources[0x27]	11957	1			T2	16		T3	4		T4	2
valid_sources[0x28]	7066	1			T2	23		T3	3		T4	2
valid_sources[0x29]	8474	1			T2	18		T3	19		T4	1
valid_sources[0x2a]	7482	1			T2	21		T3	8		T4	6
valid_sources[0x2b]	7764	1			T2	17		T3	6		T4	6
valid_sources[0x2c]	7320	1			T2	16		T3	15		T4	3
valid_sources[0x2d]	8416	1			T2	18		T3	4		T4	5
valid_sources[0x2e]	6971	1			T2	19		T3	15		T4	3
valid_sources[0x2f]	7033	1			T2	18		T3	3		T4	4
valid_sources[0x30]	11470	1			T2	19		T3	8		T4	2
valid_sources[0x31]	7286	1			T2	15		T3	12		T4	4
valid_sources[0x32]	8222	1			T2	6		T4	3		T5	15
valid_sources[0x33]	17927	1			T1	896		T2	6		T3	40
valid_sources[0x34]	7542	1			T2	14		T3	2		T4	3
valid_sources[0x35]	7239	1			T2	9		T3	6		T4	2
valid_sources[0x36]	24055	1			T2	20		T3	3		T4	4
valid_sources[0x37]	8319	1			T2	18		T3	6		T4	2
valid_sources[0x38]	7478	1			T2	9		T3	8		T4	5
valid_sources[0x39]	7161	1			T2	17		T4	3		T5	11
valid_sources[0x3a]	7466	1			T2	25		T3	9		T4	2
valid_sources[0x3b]	7526	1			T2	6		T3	10		T4	2
valid_sources[0x3c]	8234	1			T2	20		T3	2		T4	8
valid_sources[0x3d]	7135	1			T2	8		T3	9		T4	7
valid_sources[0x3e]	7067	1			T2	32		T3	3		T4	1
valid_sources[0x3f]	7427	1			T2	22		T3	8		T4	5
valid_sources[0x40]	11488	1			T2	10		T3	8		T4	1
valid_sources[0x41]	7809	1			T2	21		T3	2		T4	8
valid_sources[0x42]	13738	1			T2	15		T3	6		T4	3
valid_sources[0x43]	7201	1			T2	18		T3	4		T4	1
valid_sources[0x44]	11838	1			T2	12		T3	3		T4	6
valid_sources[0x45]	7147	1			T2	10		T3	6		T4	2
valid_sources[0x46]	7130	1			T2	9		T3	8		T4	7
valid_sources[0x47]	12328	1			T2	12		T3	4		T4	2
valid_sources[0x48]	7549	1			T2	11		T3	2		T4	2
valid_sources[0x49]	11094	1			T2	20		T3	1		T4	5
valid_sources[0x4a]	10299	1			T2	7		T4	7		T5	18
valid_sources[0x4b]	7634	1			T2	12		T3	5		T4	2
valid_sources[0x4c]	8916	1			T2	10		T3	3		T4	9
valid_sources[0x4d]	7712	1			T2	13		T3	3		T4	2
valid_sources[0x4e]	21063	1			T2	29		T3	5		T4	3
valid_sources[0x4f]	8388	1			T2	11		T3	3		T4	3
valid_sources[0x50]	9159	1			T2	17		T4	6		T5	7
valid_sources[0x51]	7864	1			T2	25		T3	4		T4	5
valid_sources[0x52]	12023	1			T2	14		T3	5		T4	2
valid_sources[0x53]	20408	1			T2	12		T3	3		T4	6
valid_sources[0x54]	8860	1			T2	20		T3	6		T4	6
valid_sources[0x55]	7546	1			T2	18		T3	9		T4	2
valid_sources[0x56]	9504	1			T2	11		T3	8		T4	6
valid_sources[0x57]	8360	1			T2	14		T3	6		T4	3
valid_sources[0x58]	11841	1			T2	15		T3	29		T4	3
valid_sources[0x59]	7288	1			T2	19		T3	18		T4	2
valid_sources[0x5a]	8807	1			T2	19		T3	7		T4	4
valid_sources[0x5b]	11518	1			T2	17		T3	3		T4	3
valid_sources[0x5c]	9829	1			T2	23		T3	4		T4	2
valid_sources[0x5d]	7477	1			T2	13		T3	2		T4	3
valid_sources[0x5e]	9426	1			T2	36		T3	1		T4	1
valid_sources[0x5f]	7433	1			T2	9		T3	40		T4	1
valid_sources[0x60]	7070	1			T2	29		T3	4		T4	2
valid_sources[0x61]	8666	1			T2	22		T3	3		T5	6
valid_sources[0x62]	19499	1			T2	16		T3	6		T4	5
valid_sources[0x63]	7283	1			T2	16		T3	3		T4	7
valid_sources[0x64]	7201	1			T2	12		T3	3		T4	1
valid_sources[0x65]	6891	1			T2	20		T3	4		T4	5
valid_sources[0x66]	11790	1			T2	15		T3	4		T4	2
valid_sources[0x67]	7319	1			T2	21		T3	14		T4	3
valid_sources[0x68]	9333	1			T2	18		T3	942		T4	2
valid_sources[0x69]	9947	1			T2	9		T3	2		T4	3
valid_sources[0x6a]	7230	1			T2	12		T3	4		T5	20
valid_sources[0x6b]	7563	1			T2	22		T3	1		T4	5
valid_sources[0x6c]	7693	1			T2	15		T4	3		T5	3
valid_sources[0x6d]	7479	1			T2	19		T3	11		T4	4
valid_sources[0x6e]	6819	1			T2	18		T3	7		T4	4
valid_sources[0x6f]	13524	1			T2	16		T3	46		T4	4
valid_sources[0x70]	11510	1			T2	23		T3	13		T4	3
valid_sources[0x71]	14037	1			T2	16		T3	4		T4	8
valid_sources[0x72]	7630	1			T2	31		T3	5		T5	30
valid_sources[0x73]	8745	1			T2	21		T3	1		T4	2
valid_sources[0x74]	8021	1			T2	11		T3	4		T4	1
valid_sources[0x75]	12645	1			T2	21		T3	2		T4	3
valid_sources[0x76]	9123	1			T2	19		T3	1		T4	5
valid_sources[0x77]	20777	1			T2	18		T3	22		T4	5
valid_sources[0x78]	7440	1			T2	14		T3	20		T4	5
valid_sources[0x79]	12596	1			T2	7		T3	32		T4	7
valid_sources[0x7a]	7787	1			T2	12		T3	3		T4	6
valid_sources[0x7b]	11875	1			T2	16		T3	3		T4	11
valid_sources[0x7c]	7135	1			T2	14		T3	20		T4	5
valid_sources[0x7d]	11466	1			T2	14		T3	3		T4	4
valid_sources[0x7e]	19141	1			T2	18		T3	7		T4	2
valid_sources[0x7f]	7251	1			T2	15		T3	6		T4	3
valid_sources[0x80]	7274	1			T2	25		T4	1		T5	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1050816

1

T2

1938

T3

1211

T4

847

values[0x0]

all_enables

biggest_size

83595

1

T1

191

T2

47

T3

94

values[0x1]

all_enables

biggest_size

60105

1

T1

160

T2

25

T3

67