Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	31286	1			T1	237		T2	8		T3	21
auto[PWRUP]	124	1			T1	1		T45	2		T15	2
auto[ONEST_0]	75	1			T1	2		T45	2		T16	1
auto[ONEST_021]	20	1			T1	1		T44	1		T97	2
auto[ONEST_1]	90	1			T1	1		T46	2		T196	3
auto[ONEST_DONE]	3	1			T197	1		T198	1		T199	1
auto[LP_0]	125	1			T1	1		T44	1		T45	2
auto[LP_021]	23	1			T1	1		T44	1		T45	1
auto[LP_1]	135	1			T1	4		T44	1		T45	3
auto[LP_EVAL]	76	1			T1	1		T16	2		T196	1
auto[LP_SLP]	572	1			T1	3		T44	8		T45	9
auto[LP_PWRUP]	31	1			T1	1		T45	1		T34	1
auto[NP_0]	169	1			T44	2		T45	1		T15	1
auto[NP_021]	27	1			T46	1		T18	2		T200	1
auto[NP_1]	181	1			T1	4		T44	2		T45	1
auto[NP_EVAL]	44	1			T34	1		T46	1		T175	2
auto[NP_DONE]	1	1			T21	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T45

1

T196

1

T97

2

min

30717

1

T1

230

T2

8

T3

21

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30726	1			T1	231		T2	8		T3	21
pow[0x1]	10	1			T17	1		T18	1		T200	1
pow[0x2]	16	1			T201	1		T202	1		T203	1
pow[0x3]	32	1			T45	1		T201	1		T202	1
pow[0x4]	80	1			T45	4		T202	1		T17	1
pow[0x5]	123	1			T1	2		T44	1		T45	1
pow[0x6]	274	1			T1	3		T44	4		T45	4
pow[0x7]	547	1			T1	4		T44	3		T45	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

200

1

T44

2

T45

3

T15

1

min

30192

1

T1

228

T2

8

T3

21

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30192	1			T1	228		T2	8		T3	21
pow[0x5]	3	1			T45	1		T204	1		T205	1
pow[0x6]	1	1			T197	1		-	-		-	-
pow[0x7]	1	1			T206	1		-	-		-	-
pow[0x8]	6	1			T48	1		T207	1		T208	1
pow[0x9]	8	1			T1	1		T21	1		T204	1
pow[0xa]	19	1			T44	2		T202	1		T209	1
pow[0xb]	28	1			T175	1		T48	2		T18	2
pow[0xc]	87	1			T44	1		T15	1		T46	1
pow[0xd]	161	1			T1	1		T44	1		T45	3
pow[0xe]	308	1			T1	2		T45	4		T15	1
pow[0xf]	665	1			T1	9		T44	9		T45	10