Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2427	1			T1	12		T13	3		T67	3
auto[PWRUP]	138	1			T1	3		T44	1		T45	3
auto[ONEST_0]	96	1			T1	1		T44	2		T45	2
auto[ONEST_021]	23	1			T15	1		T175	1		T20	1
auto[ONEST_1]	110	1			T1	2		T45	1		T14	1
auto[ONEST_DONE]	6	1			T341	1		T342	1		T343	1
auto[LP_0]	158	1			T44	2		T45	3		T15	2
auto[LP_021]	33	1			T34	1		T196	1		T175	1
auto[LP_1]	160	1			T1	1		T44	2		T45	1
auto[LP_EVAL]	64	1			T1	1		T44	1		T34	1
auto[LP_SLP]	515	1			T1	8		T44	5		T45	6
auto[LP_PWRUP]	39	1			T44	1		T45	1		T34	1
auto[NP_0]	226	1			T1	2		T44	4		T45	3
auto[NP_021]	59	1			T45	1		T35	1		T36	1
auto[NP_1]	254	1			T1	5		T44	4		T45	2
auto[NP_EVAL]	24	1			T14	1		T16	1		T175	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T196

1

T47

1

T18

2

min

1962

1

T1

9

T13

3

T67

3

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1973	1			T1	9		T13	3		T67	3
pow[0x1]	11	1			T207	1		T255	1		T203	1
pow[0x2]	23	1			T44	1		T16	1		T36	1
pow[0x3]	38	1			T1	1		T35	1		T175	1
pow[0x4]	71	1			T44	1		T175	1		T201	1
pow[0x5]	143	1			T1	2		T44	2		T45	4
pow[0x6]	305	1			T1	4		T44	7		T45	5
pow[0x7]	606	1			T1	4		T44	6		T45	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

236

1

T1

3

T44

6

T45

4

min

1349

1

T1

2

T13

3

T67

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1354	1			T1	2		T13	3		T67	3
pow[0x1]	16	1			T16	1		T303	2		T21	1
pow[0x2]	24	1			T14	3		T15	2		T16	1
pow[0x3]	67	1			T15	1		T34	2		T16	2
pow[0x4]	51	1			T1	1		T35	3		T16	1
pow[0x5]	1	1			T155	1		-	-		-	-
pow[0x6]	4	1			T15	1		T18	1		T199	1
pow[0x7]	2	1			T344	1		T330	1		-	-
pow[0x8]	7	1			T17	1		T200	1		T255	1
pow[0x9]	13	1			T1	2		T201	2		T202	1
pow[0xa]	20	1			T45	1		T46	1		T17	1
pow[0xb]	49	1			T45	1		T46	1		T196	1
pow[0xc]	100	1			T1	1		T46	1		T196	1
pow[0xd]	181	1			T1	4		T44	2		T45	2
pow[0xe]	312	1			T1	2		T44	4		T45	4
pow[0xf]	627	1			T1	9		T44	9		T45	9