Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1252176	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1220696

1

T1

36

T4

3

T2

6370

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2181118	1			T4	1		T2	12096		T3	860
values[0x0]	145368	1			T1	32		T4	4		T2	413
values[0x1]	146386	1			T1	29		T4	4		T2	423

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1002108	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1470764

1

T1

41

T4

3

T2

7662

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11946	1			T2	30		T3	4		T5	34
valid_sources[0x01]	11737	1			T2	44		T3	4		T5	25
valid_sources[0x02]	8288	1			T1	1		T2	40		T3	7
valid_sources[0x03]	7421	1			T2	44		T3	1		T5	29
valid_sources[0x04]	8725	1			T1	1		T2	59		T3	6
valid_sources[0x05]	10413	1			T2	40		T3	1		T5	36
valid_sources[0x06]	8438	1			T2	34		T3	6		T5	33
valid_sources[0x07]	20272	1			T2	75		T3	2		T5	30
valid_sources[0x08]	7932	1			T2	78		T3	4		T5	26
valid_sources[0x09]	7531	1			T2	37		T3	1		T5	42
valid_sources[0x0a]	7754	1			T2	68		T3	7		T5	37
valid_sources[0x0b]	7501	1			T1	1		T2	36		T3	6
valid_sources[0x0c]	8479	1			T2	57		T3	5		T5	26
valid_sources[0x0d]	12096	1			T2	73		T3	7		T5	31
valid_sources[0x0e]	8349	1			T2	49		T3	4		T5	29
valid_sources[0x0f]	7143	1			T2	22		T3	2		T5	37
valid_sources[0x10]	7909	1			T2	38		T3	5		T5	32
valid_sources[0x11]	7630	1			T2	76		T3	1		T5	28
valid_sources[0x12]	7514	1			T1	2		T2	42		T3	4
valid_sources[0x13]	7466	1			T2	38		T3	4		T5	36
valid_sources[0x14]	8427	1			T2	53		T3	7		T5	25
valid_sources[0x15]	11695	1			T4	1		T2	80		T3	5
valid_sources[0x16]	9090	1			T4	1		T2	53		T3	2
valid_sources[0x17]	9527	1			T2	57		T3	8		T5	30
valid_sources[0x18]	12819	1			T2	51		T3	2		T5	36
valid_sources[0x19]	7834	1			T2	84		T3	9		T5	35
valid_sources[0x1a]	11716	1			T2	79		T3	9		T5	37
valid_sources[0x1b]	7177	1			T1	1		T2	35		T3	1
valid_sources[0x1c]	8415	1			T2	52		T3	3		T5	28
valid_sources[0x1d]	11901	1			T2	53		T3	1		T5	33
valid_sources[0x1e]	7485	1			T2	27		T3	7		T5	28
valid_sources[0x1f]	7892	1			T2	55		T3	3		T5	37
valid_sources[0x20]	9187	1			T2	35		T3	5		T5	32
valid_sources[0x21]	7471	1			T2	27		T3	5		T5	40
valid_sources[0x22]	11355	1			T2	53		T3	3		T5	33
valid_sources[0x23]	8942	1			T2	28		T3	3		T5	23
valid_sources[0x24]	8304	1			T1	1		T2	64		T3	9
valid_sources[0x25]	7412	1			T2	30		T3	2		T5	34
valid_sources[0x26]	8317	1			T2	58		T3	1		T5	35
valid_sources[0x27]	8471	1			T2	36		T3	2		T5	37
valid_sources[0x28]	7288	1			T2	60		T3	1		T5	35
valid_sources[0x29]	7655	1			T4	1		T2	55		T3	2
valid_sources[0x2a]	10237	1			T2	42		T3	3		T5	36
valid_sources[0x2b]	9659	1			T2	54		T3	2		T5	26
valid_sources[0x2c]	8868	1			T2	30		T3	2		T5	29
valid_sources[0x2d]	7809	1			T2	53		T3	6		T5	33
valid_sources[0x2e]	23248	1			T2	67		T3	5		T5	24
valid_sources[0x2f]	16588	1			T2	66		T3	2		T5	25
valid_sources[0x30]	7800	1			T2	47		T3	3		T5	32
valid_sources[0x31]	7358	1			T2	30		T3	2		T5	34
valid_sources[0x32]	7624	1			T2	105		T3	9		T5	25
valid_sources[0x33]	7519	1			T2	132		T3	1		T5	32
valid_sources[0x34]	11686	1			T1	1		T2	26		T3	6
valid_sources[0x35]	7651	1			T2	47		T3	3		T5	21
valid_sources[0x36]	8119	1			T2	66		T3	2		T5	33
valid_sources[0x37]	7457	1			T2	61		T3	7		T5	29
valid_sources[0x38]	7584	1			T2	34		T3	2		T5	39
valid_sources[0x39]	8102	1			T2	70		T3	2		T5	26
valid_sources[0x3a]	9331	1			T2	89		T3	7		T5	26
valid_sources[0x3b]	8087	1			T2	42		T3	1		T5	39
valid_sources[0x3c]	7520	1			T2	47		T3	2		T5	34
valid_sources[0x3d]	9202	1			T2	39		T3	6		T5	42
valid_sources[0x3e]	12399	1			T2	64		T3	3		T5	34
valid_sources[0x3f]	7795	1			T2	35		T5	26		T7	62
valid_sources[0x40]	8392	1			T1	3		T2	37		T3	1
valid_sources[0x41]	7929	1			T2	78		T3	5		T5	22
valid_sources[0x42]	9609	1			T2	38		T5	31		T6	1
valid_sources[0x43]	10581	1			T2	20		T3	6		T5	29
valid_sources[0x44]	8826	1			T2	57		T3	4		T5	25
valid_sources[0x45]	8051	1			T2	40		T3	1		T5	34
valid_sources[0x46]	8890	1			T1	1		T2	49		T3	4
valid_sources[0x47]	7353	1			T2	33		T3	3		T5	25
valid_sources[0x48]	7943	1			T2	51		T3	4		T5	32
valid_sources[0x49]	7537	1			T2	40		T3	3		T5	36
valid_sources[0x4a]	9731	1			T4	1		T2	43		T5	26
valid_sources[0x4b]	7807	1			T2	37		T3	4		T5	30
valid_sources[0x4c]	8627	1			T1	2		T2	44		T3	3
valid_sources[0x4d]	8160	1			T2	37		T3	3		T5	16
valid_sources[0x4e]	13581	1			T1	1		T2	55		T3	2
valid_sources[0x4f]	7785	1			T2	28		T3	2		T5	40
valid_sources[0x50]	12022	1			T2	65		T3	1		T5	35
valid_sources[0x51]	12089	1			T2	37		T3	2		T5	28
valid_sources[0x52]	16405	1			T2	41		T3	2		T5	38
valid_sources[0x53]	9099	1			T2	60		T3	3		T5	35
valid_sources[0x54]	7766	1			T2	44		T3	4		T5	38
valid_sources[0x55]	8533	1			T2	56		T3	5		T5	29
valid_sources[0x56]	10597	1			T2	67		T3	4		T5	22
valid_sources[0x57]	11987	1			T2	43		T3	2		T5	30
valid_sources[0x58]	7714	1			T2	40		T5	21		T6	19
valid_sources[0x59]	7550	1			T4	1		T2	50		T3	7
valid_sources[0x5a]	9930	1			T2	64		T3	5		T5	27
valid_sources[0x5b]	8122	1			T2	75		T3	5		T5	27
valid_sources[0x5c]	7734	1			T2	45		T3	5		T5	41
valid_sources[0x5d]	7349	1			T2	24		T3	7		T5	22
valid_sources[0x5e]	8825	1			T2	25		T3	3		T5	35
valid_sources[0x5f]	7382	1			T2	74		T3	2		T5	30
valid_sources[0x60]	7705	1			T2	56		T3	2		T5	36
valid_sources[0x61]	7356	1			T2	31		T3	3		T5	20
valid_sources[0x62]	7399	1			T2	57		T3	4		T5	26
valid_sources[0x63]	8031	1			T2	86		T3	4		T5	26
valid_sources[0x64]	11942	1			T2	63		T3	7		T5	39
valid_sources[0x65]	7620	1			T2	69		T3	2		T5	34
valid_sources[0x66]	13395	1			T1	1		T2	50		T3	2
valid_sources[0x67]	7861	1			T1	2		T4	1		T2	51
valid_sources[0x68]	9216	1			T2	32		T3	5		T5	36
valid_sources[0x69]	12839	1			T2	69		T3	4		T5	23
valid_sources[0x6a]	9209	1			T2	69		T3	2		T5	27
valid_sources[0x6b]	11602	1			T2	45		T3	1		T5	35
valid_sources[0x6c]	21001	1			T2	52		T3	3		T5	21
valid_sources[0x6d]	7520	1			T2	46		T5	27		T6	30
valid_sources[0x6e]	11847	1			T2	63		T3	7		T5	42
valid_sources[0x6f]	13488	1			T2	54		T3	8		T5	33
valid_sources[0x70]	11983	1			T2	69		T3	6		T5	31
valid_sources[0x71]	7302	1			T2	49		T3	10		T5	37
valid_sources[0x72]	10369	1			T1	1		T2	31		T3	3
valid_sources[0x73]	7424	1			T2	44		T3	5		T5	30
valid_sources[0x74]	8508	1			T2	49		T3	7		T5	39
valid_sources[0x75]	10837	1			T2	37		T3	2		T5	19
valid_sources[0x76]	7379	1			T1	1		T2	36		T3	5
valid_sources[0x77]	7940	1			T2	50		T3	6		T5	35
valid_sources[0x78]	12252	1			T2	69		T3	7		T5	31
valid_sources[0x79]	7941	1			T1	1		T2	67		T3	5
valid_sources[0x7a]	7638	1			T2	28		T3	5		T5	29
valid_sources[0x7b]	13750	1			T2	53		T3	3		T5	25
valid_sources[0x7c]	7601	1			T2	55		T3	5		T5	34
valid_sources[0x7d]	8842	1			T2	36		T3	2		T5	35
valid_sources[0x7e]	7770	1			T2	39		T3	4		T5	30
valid_sources[0x7f]	13947	1			T2	34		T3	2		T5	36
valid_sources[0x80]	9770	1			T2	55		T3	5		T5	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1085895

1

T2

6058

T3

427

T5

3506

values[0x0]

all_enables

biggest_size

78601

1

T1

20

T4

2

T2

194

values[0x1]

all_enables

biggest_size

56200

1

T1

16

T4

1

T2

118