Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
84.44	84.44	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	84.44	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	7	38	84.44

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	6	10	62.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28618	1			T2	21		T3	7		T5	21
auto[PWRUP]	108	1			T6	2		T7	3		T28	4
auto[ONEST_0]	70	1			T6	1		T7	2		T45	1
auto[ONEST_021]	16	1			T37	1		T197	2		T198	1
auto[ONEST_1]	73	1			T6	1		T7	2		T45	1
auto[ONEST_DONE]	6	1			T199	1		T200	1		T201	1
auto[LP_0]	119	1			T6	1		T7	1		T45	2
auto[LP_021]	26	1			T25	1		T202	1		T191	1
auto[LP_1]	112	1			T7	1		T45	3		T28	3
auto[LP_EVAL]	75	1			T7	1		T45	2		T25	1
auto[LP_SLP]	486	1			T6	3		T7	11		T45	8
auto[LP_PWRUP]	25	1			T7	1		T14	1		T203	1
auto[NP_0]	157	1			T6	1		T7	3		T45	1
auto[NP_021]	36	1			T6	1		T7	1		T45	1
auto[NP_1]	153	1			T7	2		T45	1		T25	1
auto[NP_EVAL]	29	1			T14	1		T28	2		T204	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T7

1

T15

1

T205

1

min

28177

1

T2

21

T3

7

T5

21

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28184	1			T2	21		T3	7		T5	21
pow[0x1]	8	1			T206	1		T207	1		T208	1
pow[0x2]	9	1			T209	1		T210	1		T211	1
pow[0x3]	21	1			T37	1		T212	1		T46	1
pow[0x4]	56	1			T25	3		T28	2		T31	1
pow[0x5]	132	1			T7	2		T45	1		T14	1
pow[0x6]	264	1			T6	2		T7	7		T45	1
pow[0x7]	472	1			T6	3		T7	7		T45	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

178

1

T7

5

T25

3

T28

2

min

27722

1

T2

21

T3

7

T5

21

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	6	10	62.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27722	1			T2	21		T3	7		T5	21
pow[0x6]	1	1			T210	1		-	-		-	-
pow[0x8]	2	1			T202	1		T213	1		-	-
pow[0x9]	9	1			T45	1		T28	1		T214	2
pow[0xa]	17	1			T209	1		T37	1		T212	1
pow[0xb]	36	1			T7	1		T45	1		T28	2
pow[0xc]	51	1			T45	2		T202	1		T212	1
pow[0xd]	143	1			T6	1		T7	5		T45	2
pow[0xe]	283	1			T6	1		T7	5		T45	4
pow[0xf]	543	1			T6	7		T7	14		T45	5