Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2207	1			T2	3		T6	25		T7	23
auto[PWRUP]	121	1			T6	1		T7	1		T25	1
auto[ONEST_0]	62	1			T6	2		T25	2		T28	2
auto[ONEST_021]	18	1			T14	1		T38	1		T204	1
auto[ONEST_1]	73	1			T6	1		T45	3		T25	1
auto[ONEST_DONE]	1	1			T14	1		-	-		-	-
auto[LP_0]	140	1			T6	1		T7	1		T45	1
auto[LP_021]	25	1			T7	1		T14	1		T25	1
auto[LP_1]	138	1			T6	1		T7	4		T45	1
auto[LP_EVAL]	67	1			T6	1		T45	1		T28	1
auto[LP_SLP]	461	1			T6	4		T7	14		T45	4
auto[LP_PWRUP]	28	1			T6	2		T45	1		T14	1
auto[NP_0]	215	1			T6	3		T7	4		T45	3
auto[NP_021]	55	1			T7	1		T31	1		T36	1
auto[NP_1]	215	1			T6	1		T7	2		T45	1
auto[NP_EVAL]	32	1			T14	1		T15	1		T202	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

4

1

T337

1

T338

1

T339

1

min

1952

1

T2

3

T6

25

T7

20

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1967	1			T2	3		T6	25		T7	20
pow[0x1]	5	1			T45	1		T340	1		T200	1
pow[0x2]	17	1			T202	1		T231	1		T257	1
pow[0x3]	31	1			T6	1		T7	1		T15	1
pow[0x4]	58	1			T6	1		T7	1		T45	1
pow[0x5]	135	1			T6	2		T7	1		T45	2
pow[0x6]	219	1			T6	3		T7	5		T45	3
pow[0x7]	467	1			T6	3		T7	7		T45	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

193

1

T7

5

T45

4

T25

1

min

1392

1

T2

3

T6

22

T7

7

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1396	1			T2	3		T6	22		T7	7
pow[0x1]	10	1			T37	1		T39	1		T282	1
pow[0x2]	26	1			T15	1		T38	1		T16	4
pow[0x3]	43	1			T14	5		T31	2		T36	3
pow[0x4]	70	1			T37	2		T38	1		T39	6
pow[0x5]	1	1			T337	1		-	-		-	-
pow[0x6]	2	1			T214	1		T341	1		-	-
pow[0x7]	1	1			T342	1		-	-		-	-
pow[0x8]	3	1			T28	1		T210	1		T200	1
pow[0x9]	9	1			T343	1		T211	1		T200	1
pow[0xa]	15	1			T45	1		T37	1		T191	1
pow[0xb]	44	1			T6	1		T7	2		T45	1
pow[0xc]	80	1			T6	1		T7	2		T25	1
pow[0xd]	130	1			T7	3		T45	3		T14	1
pow[0xe]	295	1			T6	5		T7	3		T45	4
pow[0xf]	466	1			T6	8		T7	7		T45	7