Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2242	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2121	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2144	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1965	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1971	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2113	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1995	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2081	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2269	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2068	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2066	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2161	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1822	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1969	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2024	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2048	0	0
adc_en_ctl_rd_A	2147483647	1525	0	0
adc_fsm_rst_rd_A	2147483647	1351	0	0
adc_intr_ctl_rd_A	2147483647	1828	0	0
adc_lp_sample_ctl_rd_A	2147483647	1329	0	0
adc_pd_ctl_rd_A	2147483647	1784	0	0
adc_sample_ctl_rd_A	2147483647	1268	0	0
adc_wakeup_ctl_rd_A	2147483647	1514	0	0
intr_enable_rd_A	2147483647	2036	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2242	0	0
T14	351762	33	0	0
T15	547197	13	0	0
T16	0	28	0	0
T17	0	29	0	0
T18	0	31	0	0
T19	0	17	0	0
T20	0	43	0	0
T21	0	21	0	0
T22	0	23	0	0
T23	0	24	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2121	0	0
T14	351762	31	0	0
T15	547197	20	0	0
T16	0	48	0	0
T17	0	14	0	0
T18	0	31	0	0
T19	0	24	0	0
T20	0	30	0	0
T21	0	25	0	0
T22	0	10	0	0
T23	0	43	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2144	0	0
T14	351762	32	0	0
T15	547197	25	0	0
T16	0	59	0	0
T17	0	24	0	0
T18	0	34	0	0
T19	0	30	0	0
T20	0	29	0	0
T21	0	22	0	0
T22	0	9	0	0
T23	0	36	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1965	0	0
T14	351762	41	0	0
T15	547197	14	0	0
T16	0	21	0	0
T17	0	12	0	0
T18	0	39	0	0
T19	0	25	0	0
T20	0	32	0	0
T21	0	13	0	0
T22	0	6	0	0
T23	0	28	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1971	0	0
T14	351762	41	0	0
T15	547197	20	0	0
T16	0	55	0	0
T17	0	21	0	0
T18	0	30	0	0
T19	0	30	0	0
T20	0	39	0	0
T21	0	15	0	0
T22	0	12	0	0
T23	0	20	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2113	0	0
T14	351762	44	0	0
T15	547197	34	0	0
T16	0	28	0	0
T17	0	20	0	0
T18	0	44	0	0
T19	0	23	0	0
T20	0	37	0	0
T21	0	6	0	0
T22	0	16	0	0
T23	0	6	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1995	0	0
T14	351762	19	0	0
T15	547197	14	0	0
T16	0	37	0	0
T17	0	9	0	0
T18	0	41	0	0
T19	0	21	0	0
T20	0	20	0	0
T21	0	14	0	0
T22	0	10	0	0
T23	0	7	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2081	0	0
T14	351762	38	0	0
T15	547197	25	0	0
T16	0	31	0	0
T17	0	22	0	0
T18	0	40	0	0
T19	0	17	0	0
T20	0	32	0	0
T21	0	18	0	0
T22	0	17	0	0
T23	0	16	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2269	0	0
T14	351762	42	0	0
T15	547197	18	0	0
T16	0	30	0	0
T17	0	18	0	0
T18	0	45	0	0
T19	0	15	0	0
T20	0	32	0	0
T21	0	14	0	0
T22	0	14	0	0
T23	0	16	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2068	0	0
T14	351762	35	0	0
T15	547197	21	0	0
T16	0	45	0	0
T17	0	22	0	0
T18	0	60	0	0
T19	0	24	0	0
T20	0	21	0	0
T21	0	15	0	0
T22	0	6	0	0
T23	0	14	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2066	0	0
T14	351762	43	0	0
T15	547197	21	0	0
T16	0	51	0	0
T17	0	29	0	0
T18	0	35	0	0
T19	0	21	0	0
T20	0	36	0	0
T21	0	22	0	0
T22	0	20	0	0
T23	0	12	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2161	0	0
T14	351762	38	0	0
T15	547197	23	0	0
T16	0	44	0	0
T17	0	25	0	0
T18	0	57	0	0
T19	0	12	0	0
T20	0	35	0	0
T21	0	24	0	0
T22	0	12	0	0
T23	0	24	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1822	0	0
T14	351762	44	0	0
T15	547197	29	0	0
T16	0	33	0	0
T17	0	7	0	0
T18	0	33	0	0
T19	0	16	0	0
T20	0	44	0	0
T21	0	20	0	0
T22	0	10	0	0
T23	0	20	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1969	0	0
T14	351762	26	0	0
T15	547197	9	0	0
T16	0	22	0	0
T17	0	19	0	0
T18	0	24	0	0
T19	0	12	0	0
T20	0	34	0	0
T21	0	20	0	0
T22	0	12	0	0
T23	0	18	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2024	0	0
T14	351762	33	0	0
T15	547197	25	0	0
T16	0	35	0	0
T17	0	6	0	0
T18	0	55	0	0
T19	0	24	0	0
T20	0	28	0	0
T21	0	23	0	0
T22	0	11	0	0
T23	0	27	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2048	0	0
T14	351762	15	0	0
T15	547197	13	0	0
T16	0	44	0	0
T17	0	19	0	0
T18	0	31	0	0
T19	0	17	0	0
T20	0	18	0	0
T21	0	14	0	0
T22	0	7	0	0
T23	0	18	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1525	0	0
T14	351762	40	0	0
T15	547197	6	0	0
T16	0	36	0	0
T17	0	16	0	0
T18	0	31	0	0
T19	0	12	0	0
T20	0	49	0	0
T21	0	20	0	0
T23	0	8	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0
T32	0	14	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1351	0	0
T14	351762	29	0	0
T15	547197	29	0	0
T16	0	37	0	0
T17	0	29	0	0
T18	0	38	0	0
T19	0	20	0	0
T20	0	32	0	0
T21	0	9	0	0
T22	0	7	0	0
T23	0	17	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1828	0	0
T14	351762	33	0	0
T15	547197	25	0	0
T16	0	36	0	0
T17	0	21	0	0
T18	0	31	0	0
T19	0	21	0	0
T20	0	48	0	0
T21	0	9	0	0
T22	0	13	0	0
T23	0	23	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1329	0	0
T14	351762	30	0	0
T15	547197	21	0	0
T16	0	33	0	0
T17	0	25	0	0
T18	0	30	0	0
T19	0	18	0	0
T20	0	27	0	0
T21	0	25	0	0
T22	0	6	0	0
T23	0	19	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1784	0	0
T14	351762	43	0	0
T15	547197	10	0	0
T16	0	35	0	0
T17	0	6	0	0
T18	0	43	0	0
T19	0	24	0	0
T20	0	42	0	0
T21	0	23	0	0
T22	0	17	0	0
T23	0	23	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1268	0	0
T14	351762	36	0	0
T15	547197	14	0	0
T16	0	41	0	0
T17	0	6	0	0
T18	0	29	0	0
T19	0	14	0	0
T20	0	32	0	0
T21	0	22	0	0
T22	0	8	0	0
T23	0	8	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1514	0	0
T14	351762	39	0	0
T15	547197	20	0	0
T16	0	32	0	0
T17	0	19	0	0
T18	0	39	0	0
T19	0	22	0	0
T20	0	41	0	0
T21	0	17	0	0
T22	0	1	0	0
T23	0	25	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2036	0	0
T14	351762	62	0	0
T15	547197	17	0	0
T16	0	61	0	0
T17	0	20	0	0
T18	0	56	0	0
T19	0	33	0	0
T20	0	40	0	0
T24	125579	0	0	0
T25	141738	0	0	0
T26	331840	0	0	0
T27	421980	0	0	0
T28	317935	0	0	0
T29	580336	0	0	0
T30	145959	0	0	0
T31	500474	0	0	0
T33	0	19	0	0
T34	0	54	0	0
T35	0	15	0	0