Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1255181	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1228098

1

T1

493

T2

6417

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2179009	1			T2	12324		T4	842		T15	1
values[0x0]	151708	1			T1	636		T2	344		T3	15
values[0x1]	152562	1			T1	626		T2	373		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1005313	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1477966

1

T1

598

T2

7699

T3

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6824	1			T1	5		T2	68		T6	1
valid_sources[0x01]	12138	1			T1	2		T2	49		T6	3
valid_sources[0x02]	7432	1			T1	5		T2	53		T5	1
valid_sources[0x03]	11900	1			T1	2		T2	36		T5	2
valid_sources[0x04]	7871	1			T1	4		T2	54		T5	3
valid_sources[0x05]	9472	1			T1	8		T2	29		T7	11
valid_sources[0x06]	8536	1			T1	3		T2	58		T5	1
valid_sources[0x07]	8934	1			T1	7		T2	56		T6	1
valid_sources[0x08]	6954	1			T1	4		T2	42		T7	7
valid_sources[0x09]	7298	1			T1	4		T2	48		T8	45
valid_sources[0x0a]	8004	1			T1	3		T2	52		T7	5
valid_sources[0x0b]	7085	1			T1	2		T2	54		T6	2
valid_sources[0x0c]	7680	1			T1	6		T2	71		T7	3
valid_sources[0x0d]	16290	1			T1	3		T2	71		T6	1
valid_sources[0x0e]	7114	1			T1	4		T2	44		T7	5
valid_sources[0x0f]	9938	1			T1	4		T2	52		T6	1
valid_sources[0x10]	16226	1			T1	9		T2	54		T6	1
valid_sources[0x11]	8836	1			T1	5		T2	42		T5	2
valid_sources[0x12]	7505	1			T1	7		T2	50		T6	1
valid_sources[0x13]	7617	1			T1	7		T2	41		T5	1
valid_sources[0x14]	11632	1			T1	10		T2	40		T7	23
valid_sources[0x15]	8458	1			T1	4		T2	45		T8	53
valid_sources[0x16]	7594	1			T1	2		T2	60		T5	3
valid_sources[0x17]	11486	1			T1	3		T2	48		T6	1
valid_sources[0x18]	8412	1			T1	6		T2	49		T6	3
valid_sources[0x19]	7410	1			T1	5		T2	53		T5	1
valid_sources[0x1a]	7017	1			T1	4		T2	46		T7	10
valid_sources[0x1b]	7502	1			T1	2		T2	54		T7	18
valid_sources[0x1c]	7018	1			T1	6		T2	51		T7	24
valid_sources[0x1d]	28399	1			T1	3		T2	44		T4	948
valid_sources[0x1e]	8954	1			T1	7		T2	63		T7	11
valid_sources[0x1f]	12803	1			T1	8		T2	64		T5	1
valid_sources[0x20]	7223	1			T1	4		T2	61		T5	1
valid_sources[0x21]	7631	1			T1	4		T2	67		T8	52
valid_sources[0x22]	8446	1			T1	7		T2	44		T8	62
valid_sources[0x23]	8514	1			T1	6		T2	45		T6	1
valid_sources[0x24]	8349	1			T1	5		T2	50		T5	3
valid_sources[0x25]	7149	1			T1	5		T2	35		T6	5
valid_sources[0x26]	7261	1			T1	6		T2	32		T5	4
valid_sources[0x27]	6917	1			T1	5		T2	43		T6	4
valid_sources[0x28]	11838	1			T1	5		T2	43		T8	55
valid_sources[0x29]	8530	1			T1	1		T2	50		T6	2
valid_sources[0x2a]	21169	1			T1	4		T2	43		T5	1
valid_sources[0x2b]	8682	1			T1	5		T2	59		T7	11
valid_sources[0x2c]	8769	1			T1	13		T2	42		T5	1
valid_sources[0x2d]	7323	1			T1	3		T2	52		T6	5
valid_sources[0x2e]	7456	1			T1	3		T2	39		T5	1
valid_sources[0x2f]	7459	1			T1	3		T2	44		T5	4
valid_sources[0x30]	12502	1			T1	7		T2	58		T6	1
valid_sources[0x31]	6955	1			T1	2		T2	61		T5	1
valid_sources[0x32]	16639	1			T1	5		T2	51		T5	2
valid_sources[0x33]	10481	1			T1	3		T2	61		T5	2
valid_sources[0x34]	7053	1			T1	3		T2	45		T6	1
valid_sources[0x35]	6891	1			T1	3		T2	38		T7	17
valid_sources[0x36]	6766	1			T1	1		T2	61		T5	2
valid_sources[0x37]	9723	1			T1	5		T2	41		T5	1
valid_sources[0x38]	7000	1			T1	5		T2	65		T7	4
valid_sources[0x39]	10273	1			T1	4		T2	51		T6	1
valid_sources[0x3a]	16343	1			T1	8		T2	62		T8	60
valid_sources[0x3b]	9173	1			T1	6		T2	51		T7	1
valid_sources[0x3c]	8050	1			T1	3		T2	42		T7	12
valid_sources[0x3d]	12196	1			T1	4		T2	47		T5	1
valid_sources[0x3e]	11410	1			T1	4		T2	52		T7	38
valid_sources[0x3f]	7103	1			T1	8		T2	44		T7	16
valid_sources[0x40]	11384	1			T1	2		T2	46		T5	2
valid_sources[0x41]	12194	1			T1	6		T2	69		T7	5
valid_sources[0x42]	7727	1			T1	4		T2	45		T7	16
valid_sources[0x43]	12821	1			T1	2		T2	53		T7	14
valid_sources[0x44]	7877	1			T1	8		T2	57		T5	1
valid_sources[0x45]	11321	1			T1	3		T2	49		T7	5
valid_sources[0x46]	7291	1			T1	7		T2	46		T8	45
valid_sources[0x47]	7555	1			T1	10		T2	48		T3	37
valid_sources[0x48]	11651	1			T1	3		T2	55		T6	5
valid_sources[0x49]	8754	1			T1	4		T2	60		T5	1
valid_sources[0x4a]	7529	1			T1	5		T2	62		T6	2
valid_sources[0x4b]	8387	1			T1	1		T2	48		T6	1
valid_sources[0x4c]	8196	1			T1	3		T2	51		T7	12
valid_sources[0x4d]	8739	1			T1	2		T2	56		T5	1
valid_sources[0x4e]	7887	1			T1	8		T2	44		T6	2
valid_sources[0x4f]	7824	1			T1	3		T2	46		T6	6
valid_sources[0x50]	7131	1			T1	2		T2	51		T7	7
valid_sources[0x51]	15513	1			T1	7		T2	54		T7	10
valid_sources[0x52]	7230	1			T1	3		T2	66		T5	1
valid_sources[0x53]	14216	1			T1	5		T2	62		T7	7
valid_sources[0x54]	14380	1			T1	8		T2	58		T5	1
valid_sources[0x55]	7223	1			T1	5		T2	39		T5	7
valid_sources[0x56]	16000	1			T1	7		T2	43		T5	1
valid_sources[0x57]	6863	1			T1	6		T2	57		T6	1
valid_sources[0x58]	7225	1			T1	3		T2	51		T6	1
valid_sources[0x59]	10359	1			T1	1		T2	53		T7	9
valid_sources[0x5a]	8114	1			T1	3		T2	51		T7	7
valid_sources[0x5b]	7086	1			T1	7		T2	57		T8	76
valid_sources[0x5c]	7400	1			T1	5		T2	56		T8	42
valid_sources[0x5d]	7260	1			T1	8		T2	50		T7	2
valid_sources[0x5e]	11213	1			T1	6		T2	46		T6	1
valid_sources[0x5f]	7485	1			T1	5		T2	51		T7	24
valid_sources[0x60]	7436	1			T1	4		T2	35		T6	8
valid_sources[0x61]	13145	1			T1	7		T2	70		T8	42
valid_sources[0x62]	7123	1			T1	4		T2	56		T7	15
valid_sources[0x63]	9252	1			T1	3		T2	55		T6	2
valid_sources[0x64]	11588	1			T1	3		T2	53		T6	1
valid_sources[0x65]	7349	1			T1	7		T2	79		T7	10
valid_sources[0x66]	11469	1			T1	1		T2	47		T6	1
valid_sources[0x67]	7638	1			T1	1		T2	30		T7	28
valid_sources[0x68]	7473	1			T1	7		T2	54		T5	2
valid_sources[0x69]	7363	1			T1	3		T2	57		T7	6
valid_sources[0x6a]	11853	1			T1	8		T2	74		T5	4
valid_sources[0x6b]	10311	1			T1	6		T2	60		T5	2
valid_sources[0x6c]	8589	1			T1	9		T2	36		T7	13
valid_sources[0x6d]	14664	1			T1	8		T2	61		T7	8
valid_sources[0x6e]	7145	1			T1	9		T2	48		T7	11
valid_sources[0x6f]	7028	1			T1	2		T2	40		T5	1
valid_sources[0x70]	7624	1			T1	10		T2	67		T6	2
valid_sources[0x71]	11884	1			T1	3		T2	79		T7	11
valid_sources[0x72]	15415	1			T1	3		T2	56		T7	2
valid_sources[0x73]	7519	1			T1	3		T2	52		T6	1
valid_sources[0x74]	11385	1			T1	5		T2	39		T7	11
valid_sources[0x75]	11389	1			T1	5		T2	63		T7	6
valid_sources[0x76]	7072	1			T1	9		T2	36		T5	3
valid_sources[0x77]	10073	1			T1	2		T2	51		T6	2
valid_sources[0x78]	7380	1			T1	1		T2	57		T7	8
valid_sources[0x79]	11761	1			T1	9		T2	56		T8	47
valid_sources[0x7a]	8875	1			T1	5		T2	43		T6	3
valid_sources[0x7b]	7175	1			T1	3		T2	50		T7	17
valid_sources[0x7c]	14640	1			T1	7		T2	47		T8	41
valid_sources[0x7d]	7215	1			T1	5		T2	49		T5	1
valid_sources[0x7e]	9798	1			T1	12		T2	45		T7	17
valid_sources[0x7f]	7199	1			T1	8		T2	59		T7	1
valid_sources[0x80]	7343	1			T1	4		T2	31		T5	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1084270

1

T2

6127

T4

419

T5

43

values[0x0]

all_enables

biggest_size

83392

1

T1

299

T2

173

T3

5

values[0x1]

all_enables

biggest_size

60436

1

T1

194

T2

117

T3

11